From: Guangbin Huang huangguangbin2@huawei.com
driver inclusion category: bugfix bugzilla: NA CVE: NA
In order to get register status earlier, this patch modifies the code timing to read register firstly and then go to sleep to wait.
Signed-off-by: Guangbin Huang huangguangbin2@huawei.com Reviewed-by: Peng Li lipeng321@huawei.com Reviewed-by: Zhong Zhaohui zhongzhaohui@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 2e1fbcc..33f7045 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -3304,11 +3304,12 @@ static int hclge_reset_wait(struct hclge_dev *hdev) return -EINVAL; }
- do { + val = hclge_read_dev(&hdev->hw, reg); + while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { msleep(HCLGE_RESET_WATI_MS); val = hclge_read_dev(&hdev->hw, reg); cnt++; - } while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT); + }
if (cnt >= HCLGE_RESET_WAIT_CNT) { dev_warn(&hdev->pdev->dev,