From: Luoyouming luoyouming@huawei.com
driver inclusion category: bugfix bugzilla: https://gitee.com/src-openeuler/rdma-core/issues/I7A5Y5
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The code does not use the head position of sq to set the owner bit, but uses the head after adding 1 to cause an owner bit error. When the wqe queue has not been flipped, the hardware has flipped based on the owner bit judgment, resulting in failure to obtain wqe, unable to send, and unable to generate cqe. This patch will set the onwer bit ahead of time before the head value increases.
Fixes: 36446a56eea5 ("libhns: Extended QP supports the new post send mechanism") Signed-off-by: Luoyouming luoyouming@huawei.com --- providers/hns/hns_roce_u_hw_v2.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c index 61c7c00..ad97eb8 100644 --- a/providers/hns/hns_roce_u_hw_v2.c +++ b/providers/hns/hns_roce_u_hw_v2.c @@ -2221,6 +2221,9 @@ init_rc_wqe(struct hns_roce_qp *qp, uint64_t wr_id, unsigned int opcode)
qp->sq.wrid[wqe_idx] = wr_id; qp->cur_wqe = wqe; + + enable_wqe(qp, wqe, qp->sq.head); + qp->sq.head++;
return wqe; @@ -2242,9 +2245,6 @@ static void wr_set_sge_rc(struct ibv_qp_ex *ibv_qp, uint32_t lkey, wqe->msg_len = htole32(length); hr_reg_write(wqe, RCWQE_LEN0, length); hr_reg_write(wqe, RCWQE_SGE_NUM, !!length); - /* ignore ex sge start index */ - - enable_wqe(qp, wqe, qp->sq.head); }
static void set_sgl_rc(struct hns_roce_v2_wqe_data_seg *dseg, @@ -2554,6 +2554,9 @@ init_ud_wqe(struct hns_roce_qp *qp, uint64_t wr_id, unsigned int opcode)
qp->sq.wrid[wqe_idx] = wr_id; qp->cur_wqe = wqe; + + enable_wqe(qp, wqe, qp->sq.head); + qp->sq.head++;
return wqe; @@ -2623,7 +2626,6 @@ static void wr_set_sge_ud(struct ibv_qp_ex *ibv_qp, uint32_t lkey, dseg->len = htole32(length);
qp->sge_info.start_idx++; - enable_wqe(qp, wqe, qp->sq.head); }
static void wr_set_sge_list_ud(struct ibv_qp_ex *ibv_qp, size_t num_sge,