From: LeoLiu-oc LeoLiu-oc@zhaoxin.com
mainline inclusion from mainline-5.2 commit f8c0e061cb83bd528ff0843e717bcebc846d4838 category: x86/acpi/cstate bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA
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Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all recent Zhaoxin platforms ARB_DISABLE is a nop. So set related flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc TonyWWang-oc@zhaoxin.com Signed-off-by: Thomas Gleixner tglx@linutronix.de Cc: "hpa@zytor.com" hpa@zytor.com Cc: "gregkh@linuxfoundation.org" gregkh@linuxfoundation.org Cc: "rjw@rjwysocki.net" rjw@rjwysocki.net Cc: "lenb@kernel.org" lenb@kernel.org Cc: David Wang DavidWang@zhaoxin.com Cc: "Cooper Yan(BJ-RD)" CooperYan@zhaoxin.com Cc: "Qiyuan Wang(BJ-RD)" QiyuanWang@zhaoxin.com Cc: "Herry Yang(BJ-RD)" HerryYang@zhaoxin.com Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5e98@zhaoxin.com
Signed-off-by: LeoLiu-oc LeoLiu-oc@zhaoxin.com Signed-off-by: Cheng Jian cj.chengjian@huawei.com --- arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index cb6e076a6d39..c010f5bbbc51 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -63,6 +63,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, c->x86_stepping >= 0x0e)) flags->bm_check = 1; } + + if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { + /* + * All Zhaoxin CPUs that support C3 share cache. + * And caches should not be flushed by software while + * entering C3 type state. + */ + flags->bm_check = 1; + /* + * On all recent Zhaoxin platforms, ARB_DISABLE is a nop. + * So, set bm_control to zero to indicate that ARB_DISABLE + * is not required while entering C3 type state. + */ + flags->bm_control = 0; + } } EXPORT_SYMBOL(acpi_processor_power_init_bm_check);