From: Naveen Naidu naveennaidu479@gmail.com
stable inclusion from stable-v4.19.317 commit 4c003aef56d5642aefd4d11ee9d7e6755d4c1a6e category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IAMTH9 CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=...
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[ Upstream commit 57bdeef4716689d9b0e3571034d65cf420f6efcd ]
A config or MMIO read from a PCI device that doesn't exist or doesn't respond causes a PCI error. There's no real data to return to satisfy the CPU read, so most hardware fabricates ~0 data.
Add a PCI_ERROR_RESPONSE definition for that and use it where appropriate to make these checks consistent and easier to find.
Also add helper definitions PCI_SET_ERROR_RESPONSE() and PCI_POSSIBLE_ERROR() to make the code more readable.
Suggested-by: Bjorn Helgaas bhelgaas@google.com Link: https://lore.kernel.org/r/55563bf4dfc5d3fdc96695373c659d099bf175b1.163724371... Signed-off-by: Naveen Naidu naveennaidu479@gmail.com Signed-off-by: Bjorn Helgaas bhelgaas@google.com Reviewed-by: Pali Rohár pali@kernel.org Stable-dep-of: c625dabbf1c4 ("x86/amd_nb: Check for invalid SMN reads") Signed-off-by: Sasha Levin sashal@kernel.org Signed-off-by: Wei Li liwei391@huawei.com --- include/linux/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/include/linux/pci.h b/include/linux/pci.h index f4bc2a7122f4c..27903ebaa1f40 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -124,6 +124,15 @@ enum pci_interrupt_pin { /* The number of legacy PCI INTx interrupts */ #define PCI_NUM_INTX 4
+/* + * Reading from a device that doesn't respond typically returns ~0. A + * successful read from a device may also return ~0, so you need additional + * information to reliably identify errors. + */ +#define PCI_ERROR_RESPONSE (~0ULL) +#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) +#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) + /* * pci_power_t values must match the bits in the Capabilities PME_Support * and Control/Status PowerState fields in the Power Management capability.