driver inclusion category: bugfix bugzilla: https://gitee.com/src-openeuler/rdma-core/issues/U6KJ4Z
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The owner bit has been write in init_rc_wqe() or init_ud_wqe() with a write value. And it will be overwritten by some subsequent operations. When the SQ wraps around, the overwritten value will be an incorrect value.
For example, driver will assign the owner bit in the second step, and overwrite it in the third step.
```c ibv_wr_start(); ibv_wr_rdma_write(); if (inline) ibv_wr_set_inline_data_list(); else ibv_wr_set_sge_list(); ibv_wr_complete(); ```
This patch removes the redundant owner bit assignment operations in new IO.
Fixes: 36446a56eea5 ("libhns: Extended QP supports the new post send mechanism") Fixes: 163d62ca6196 ("libhns: Fix the owner bit error of sq in new io") Signed-off-by: Chengchang Tang tangchengchang@huawei.com --- providers/hns/hns_roce_u_hw_v2.c | 7 ------- 1 file changed, 7 deletions(-)
diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c index b2a8858..acbc854 100644 --- a/providers/hns/hns_roce_u_hw_v2.c +++ b/providers/hns/hns_roce_u_hw_v2.c @@ -2544,8 +2544,6 @@ static void wr_set_sge_list_rc(struct ibv_qp_ex *ibv_qp, size_t num_sge,
wqe->msg_len = htole32(qp->sge_info.total_len); hr_reg_write(wqe, RCWQE_SGE_NUM, qp->sge_info.valid_num); - - enable_wqe(qp, wqe, qp->sq.head); }
static void wr_send_rc(struct ibv_qp_ex *ibv_qp) @@ -2737,7 +2735,6 @@ static void wr_set_inline_data_rc(struct ibv_qp_ex *ibv_qp, void *addr,
qp->sge_info.total_len = length; set_inline_data_list_rc(qp, wqe, 1, &buff); - enable_wqe(qp, wqe, qp->sq.head); }
static void wr_set_inline_data_list_rc(struct ibv_qp_ex *ibv_qp, size_t num_buf, @@ -2755,7 +2752,6 @@ static void wr_set_inline_data_list_rc(struct ibv_qp_ex *ibv_qp, size_t num_buf, qp->sge_info.total_len += buf_list[i].length;
set_inline_data_list_rc(qp, wqe, num_buf, buf_list); - enable_wqe(qp, wqe, qp->sq.head); }
static struct hns_roce_ud_sq_wqe * @@ -2892,7 +2888,6 @@ static void wr_set_sge_list_ud(struct ibv_qp_ex *ibv_qp, size_t num_sge, hr_reg_write(wqe, UDWQE_SGE_NUM, cnt);
qp->sge_info.start_idx += cnt; - enable_wqe(qp, wqe, qp->sq.head); }
static void set_inline_data_list_ud(struct hns_roce_qp *qp, @@ -2958,7 +2953,6 @@ static void wr_set_inline_data_ud(struct ibv_qp_ex *ibv_qp, void *addr,
qp->sge_info.total_len = length; set_inline_data_list_ud(qp, wqe, 1, &buff); - enable_wqe(qp, wqe, qp->sq.head); }
static void wr_set_inline_data_list_ud(struct ibv_qp_ex *ibv_qp, size_t num_buf, @@ -2976,7 +2970,6 @@ static void wr_set_inline_data_list_ud(struct ibv_qp_ex *ibv_qp, size_t num_buf, qp->sge_info.total_len += buf_list[i].length;
set_inline_data_list_ud(qp, wqe, num_buf, buf_list); - enable_wqe(qp, wqe, qp->sq.head); }
static void wr_start(struct ibv_qp_ex *ibv_qp)