On 07/04/2021 14:31, Xie XiuQi wrote:
Hi LeoLiu,
On 2021/4/7 14:12, Cheng Jian wrote:
From: LeoLiu-oc LeoLiu-oc@zhaoxin.com
mainline inclusion from mainline-5.5 commit 5a3d56a034be9e8e87a6cb9ed3f2928184db1417 category: x86/mce bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=19 CVE: NA
Add support for more Zhaoxin CPUs.
All newer Zhaoxin CPUs support CMCI and are compatible with Intel's Machine-Check Architecture. Add that support for Zhaoxin CPUs.
[ bp: Massage comments and export intel_init_cmci(). ]
Signed-off-by: Tony W Wang-oc TonyWWang-oc@zhaoxin.com Signed-off-by: Borislav Petkov bp@suse.de Cc: CooperYan@zhaoxin.com Cc: DavidWang@zhaoxin.com Cc: HerryYang@zhaoxin.com Cc: "H. Peter Anvin" hpa@zytor.com Cc: Ingo Molnar mingo@redhat.com Cc: linux-edac linux-edac@vger.kernel.org Cc: QiyuanWang@zhaoxin.com Cc: Thomas Gleixner tglx@linutronix.de Cc: Tony Luck tony.luck@intel.com Cc: x86-ml x86@kernel.org Link: https://lkml.kernel.org/r/1568787573-1297-4-git-send-email-TonyWWang-oc@zhao... Signed-off-by: LeoLiu-oc LeoLiu-oc@zhaoxin.com Reviewed-by: Hanjun Guo guohanjun@huawei.com Signed-off-by: Cheng Jian cj.chengjian@huawei.com
arch/x86/kernel/cpu/mce/core.c | 30 +++++++++++++++++++----------- arch/x86/kernel/cpu/mce/intel.c | 7 +++++-- arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 9acfe70e8c00..2e26423c48c9 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1726,19 +1726,26 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) } }
-static void mce_centaur_feature_init(struct cpuinfo_x86 *c) +static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
In this patch we merge centaur and zhaoxin into one function. It's different with upstream patch, and removed this setting, is it right?
It's right. Will submit patch to mainline kernel to update this.
Sincerely TonyWWangoc
/** All newer Centaur CPUs support MCE broadcasting. Enable* synchronization with a one second timeout.*/- if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
c->x86 > 6) {if (cfg->monarch_timeout < 0)cfg->monarch_timeout = USEC_PER_SEC;{ struct mca_config *cfg = &mca_cfg;
/** All newer Centaur CPUs support MCE broadcasting. Enable* synchronization with a one second timeout.*/- if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
c->x86 > 6) {if (cfg->monarch_timeout < 0)cfg->monarch_timeout = USEC_PER_SEC;
- /*
* These CPUs have MCA bank 8 which reports only one error type called* SVAD (System View Address Decoder). The reporting of that error is* controlled by IA32_MC8.CTL.0.** If enabled, prefetching on these CPUs will cause SVAD MCE when* virtual machines start and result in a system panic. Always disable* bank 8 SVAD error by default.*/- if ((c->x86 == 7 && c->x86_model == 0x1b) ||
(c->x86_model == 0x19 || c->x86_model == 0x1f)) {if (cfg->banks > 8)mce_banks[8].ctl = 0;- intel_init_cmci();
- mce_adjust_timer = cmci_intel_adjust_timer;
}
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) @@ -1759,7 +1766,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) break;
case X86_VENDOR_CENTAUR:
mce_centaur_feature_init(c);
case X86_VENDOR_ZHAOXIN:
mce_zhaoxin_feature_init(c);break;
default:
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 693c8cfac75d..6a220c999a01 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -85,8 +85,11 @@ static int cmci_supported(int *banks) * initialization is vendor keyed and this * makes sure none of the backdoors are entered otherwise. */
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN &&boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)- if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0; rdmsrl(MSR_IA32_MCG_CAP, cap);
@@ -423,7 +426,7 @@ void cmci_disable_bank(int bank) raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); }
-static void intel_init_cmci(void) +void intel_init_cmci(void) { int banks;
diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index ceb67cd5918f..99d73d18f2c4 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -52,11 +52,13 @@ unsigned long cmci_intel_adjust_timer(unsigned long interval); bool mce_intel_cmci_poll(void); void mce_intel_hcpu_update(unsigned long cpu); void cmci_disable_bank(int bank); +void intel_init_cmci(void); #else # define cmci_intel_adjust_timer mce_adjust_timer_default static inline bool mce_intel_cmci_poll(void) { return false; } static inline void mce_intel_hcpu_update(unsigned long cpu) { } static inline void cmci_disable_bank(int bank) { } +static inline void intel_init_cmci(void) { } #endif
void mce_timer_kick(unsigned long interval);
.