From: Yufeng Mo moyufeng@huawei.com
driver inclusion category: bugfix bugzilla: NA CVE: NA
----------------------------
In hns3_process_hw_error(), the hardware error detection of the ROCEE AXI RESP error type is added. When the error occurs, the hns3 enet client needs to be notified of this error and take corresponding measures.
Signed-off-by: Yufeng Mo moyufeng@huawei.com Signed-off-by: Yonglong Liu liuyonglong@huawei.com Reviewed-by: Yongxin Li liyongxin1@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 1 + .../net/ethernet/hisilicon/hns3/hns3_enet.c | 2 + .../hisilicon/hns3/hns3pf/hclge_err.c | 2 + .../hisilicon/hns3/hns3pf/hclge_main.c | 43 +++++++++---------- 4 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index 8a6e9fefc130..154df30c8203 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -156,6 +156,7 @@ enum hnae3_hw_error_type { HNAE3_PPU_POISON_ERROR, HNAE3_CMDQ_ECC_ERROR, HNAE3_IMP_RD_POISON_ERROR, + HNAE3_ROCEE_AXI_RESP_ERROR, };
enum hnae3_reset_type { diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c index 49953ddc22d4..885ff9463097 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c @@ -4654,6 +4654,8 @@ static const struct hns3_hw_error_info hns3_hw_err[] = { .msg = "IMP CMDQ error" }, { .type = HNAE3_IMP_RD_POISON_ERROR, .msg = "IMP RD poison" }, + { .type = HNAE3_ROCEE_AXI_RESP_ERROR, + .msg = "ROCEE AXI RESP error" }, };
static void hns3_process_hw_error(struct hnae3_handle *handle, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c index 3c76eabb93a8..c9050fd19ed7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c @@ -1507,6 +1507,8 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
reset_type = HNAE3_FUNC_RESET;
+ hclge_report_hw_error(hdev, HNAE3_ROCEE_AXI_RESP_ERROR); + ret = hclge_log_rocee_axi_error(hdev); if (ret) return HNAE3_GLOBAL_RESET; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 6b98552a6e29..1e3610e20b28 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -3421,35 +3421,35 @@ static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) }
void hclge_report_hw_error(struct hclge_dev *hdev, - enum hnae3_hw_error_type type) + enum hnae3_hw_error_type type) { - struct hnae3_client *client = hdev->nic_client; - u16 i; + struct hnae3_client *client = hdev->nic_client; + u16 i;
- if (!client || !client->ops->process_hw_error || - !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) - return; + if (!client || !client->ops->process_hw_error || + !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) + return;
- for (i = 0; i < hdev->num_vmdq_vport + 1; i++) - client->ops->process_hw_error(&hdev->vport[i].nic, type); + for (i = 0; i < hdev->num_vmdq_vport + 1; i++) + client->ops->process_hw_error(&hdev->vport[i].nic, type); }
static void hclge_handle_imp_error(struct hclge_dev *hdev) { - u32 reg_val; + u32 reg_val;
- reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); - if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { - hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); - reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); - hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); - } + reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); + if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { + hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); + reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); + hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); + }
- if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { - hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); - reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); - hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); - } + if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { + hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); + reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); + hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); + } }
int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) @@ -3945,9 +3945,6 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) hdev->reset_level = HNAE3_FUNC_RESET; }
- if (hdev->ppu_poison_ras_err) - hdev->ppu_poison_ras_err = false; - dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", hdev->reset_level);