From: John Garry john.garry@huawei.com
mainline inclusion from mainline-v5.11-rc1 commit 644bf4b0f7ac category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I63VF5 CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=...
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Recently there was an undetected breakage for std arch event support.
Add support in "PMU events" testcase to detect such breakages.
For this, the "test" arch needs has support added to process std arch events. And a test event is added for the test, ifself.
Also add a few code comments to help understand the code a bit better.
Committer testing:
Before:
# perf test -vv pmu |& grep l3_cache_rd #
After:
# perf test -vv pmu |& grep l3_cache_rd testing event table l3_cache_rd: pass testing aliases PMU cpu: matched event l3_cache_rd #
Signed-off-by: John Garry john.garry@huawei.com Reviewed-By: Kajol Jainkjain@linux.ibm.com Tested-by: Arnaldo Carvalho de Melo acme@redhat.com Link: https://lore.kernel.org/r/1603364547-197086-3-git-send-email-john.garry@huaw... Signed-off-by: Arnaldo Carvalho de Melo acme@redhat.com Signed-off-by: Junhao He hejunhao3@huawei.com --- tools/perf/pmu-events/arch/test/arch-std-events.json | 8 ++++++++ tools/perf/pmu-events/arch/test/test_cpu/cache.json | 5 +++++ tools/perf/pmu-events/jevents.c | 4 ++++ tools/perf/tests/pmu-events.c | 12 ++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 tools/perf/pmu-events/arch/test/arch-std-events.json create mode 100644 tools/perf/pmu-events/arch/test/test_cpu/cache.json
diff --git a/tools/perf/pmu-events/arch/test/arch-std-events.json b/tools/perf/pmu-events/arch/test/arch-std-events.json new file mode 100644 index 000000000000..43f6f729d6ae --- /dev/null +++ b/tools/perf/pmu-events/arch/test/arch-std-events.json @@ -0,0 +1,8 @@ +[ + { + "PublicDescription": "Attributable Level 3 cache access, read", + "EventCode": "0x40", + "EventName": "L3_CACHE_RD", + "BriefDescription": "L3 cache access, read" + } +] diff --git a/tools/perf/pmu-events/arch/test/test_cpu/cache.json b/tools/perf/pmu-events/arch/test/test_cpu/cache.json new file mode 100644 index 000000000000..036d0efdb2bb --- /dev/null +++ b/tools/perf/pmu-events/arch/test/test_cpu/cache.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "L3_CACHE_RD" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 7dde6ad007ea..9c067a853013 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -1245,6 +1245,10 @@ int main(int argc, char *argv[])
sprintf(ldirname, "%s/test", start_dirname);
+ rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0); + if (rc) + goto err_processing_std_arch_event_dir; + rc = nftw(ldirname, process_one_file, maxfds, 0); if (rc) goto err_processing_dir; diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index d2908f41de57..aab154fe9485 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -79,6 +79,17 @@ static struct perf_pmu_test_event test_cpu_events[] = { .alias_str = "umask=0,(null)=0x30d40,event=0x3a", .alias_long_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions", }, + { + .event = { + .name = "l3_cache_rd", + .event = "event=0x40", + .desc = "L3 cache access, read", + .long_desc = "Attributable Level 3 cache access, read", + .topic = "cache", + }, + .alias_str = "event=0x40", + .alias_long_desc = "Attributable Level 3 cache access, read", + }, { /* sentinel */ .event = { .name = NULL, @@ -358,6 +369,7 @@ static int __test__pmu_event_aliases(char *pmu_name, int *count) }
+/* Test that aliases generated are as expected */ static int test_aliases(void) { struct perf_pmu *pmu = NULL;