From: Qi Liu liuqi115@huawei.com
driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I63VF5
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Add support for HiSilicon DDRC PMU aliasing on Hip09 platform.
Signed-off-by: Qi Liu liuqi115@huawei.com Signed-off-by: Junhao He hejunhao3@huawei.com --- .../hisilicon/hip09/sys/uncore-ddrc.json | 117 ++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json new file mode 100644 index 000000000000..4a68a2fdb854 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json @@ -0,0 +1,117 @@ +[ + { + "EventCode": "0x00", + "EventName": "ddrc_cycles", + "BriefDescription": "Count of DDRC cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventName": "cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x01", + "EventName": "act_cnt", + "BriefDescription": "count of DDRC active commands", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x07", + "EventName": "priority_cmd", + "BriefDescription": "count of DMC commands with the highest priority", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x0b", + "EventName": "pre_act", + "BriefDescription": "count of DDRC pre-active commands", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x41", + "EventName": "read_cmd", + "BriefDescription": "count of DDRC read commands", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x44", + "EventName": "write_cmd", + "BriefDescription": "count of DDRC write commands", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x80", + "EventName": "read_cmd_occupancy", + "BriefDescription": "count of cycles occupied by the read command in the queue", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x81", + "EventName": "write_cmd_occupancy", + "BriefDescription": "count of cycles occupied by the write command in the queue", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x83", + "EventName": "flux_wr", + "BriefDescription": "DDRC write commands", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x84", + "EventName": "flux_rd", + "BriefDescription": "DDRC read commands", + "Compat": "0x00000030", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricExpr": "flux_wr * 32 / duration_time", + "BriefDescription": "Average bandwidth of DDRC memory write(Byte/s)", + "Compat": "0x00000030", + "MetricGroup": "DDRC", + "MetricName": "ddrc_bw_write", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricExpr": "flux_rd * 32 / duration_time", + "BriefDescription": "Average bandwidth of DDRC memory read(Byte/s)", + "Compat": "0x00000030", + "MetricGroup": "DDRC", + "MetricName": "ddrc_bw_read", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricExpr": "(flux_wr + flux_rd) * 32 / duration_time", + "BriefDescription": "Average bandwidth of DDRC (including memory read and write)(Byte/s)", + "Compat": "0x00000030", + "MetricGroup": "DDRC", + "MetricName": "ddrc_bw", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricExpr": "read_cmd_occupancy / read_cmd", + "BriefDescription": "Average delay of DDRC read command scheduling", + "Compat": "0x00000030", + "MetricGroup": "DDRC", + "MetricName": "ddrc_read_lat", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricExpr": "write_cmd_occupancy / write_cmd", + "BriefDescription": "Average delay of DDRC write command scheduling", + "Compat": "0x00000030", + "MetricGroup": "DDRC", + "MetricName": "ddrc_write_lat", + "Unit": "hisi_sccl,ddrc" + } +] \ No newline at end of file