From: Cheng Jian cj.chengjian@huawei.com
hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4BLL0 CVE: NA
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This is an experimental feature to let everyone know this.
Signed-off-by: Cheng Jian cj.chengjian@huawei.com Reviewed-by: Xie XiuQi xiexiuqi@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- Documentation/admin-guide/kernel-parameters.txt | 6 ++++++ arch/arm64/Kconfig | 9 ++++++++- 2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6b1fc6dedc034..425015359b5ce 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -848,6 +848,12 @@ [ARM64] Disable using TLB instruction to flush all PE within the same inner shareable domain.
+ NOTE(Important) + This feature is used for learning and debugging + only. Please don't enable it on commercial products. + If you know exactly what the impact of the feature is, + you can configure it as you do. + range use tlb invalidation ipi for flush_tlb_range page use tlb invalidation ipi for flush_tlb_page switch don't local_flush_tlb_mm when switch_mm diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f984280b0d577..02c2f528cb608 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1610,7 +1610,7 @@ endmenu menu "TLB options"
config ARM64_TLBI_IPI - bool "IPI based ARM64 TLB invalidation" + bool "IPI based ARM64 TLB invalidation(EXPERIMENTAL)" depends on ARM64 default n help @@ -1625,7 +1625,14 @@ config ARM64_TLBI_IPI performance noise, especially at large-scale HPC environment, which has more than thousand nodes with low latency interconnect.
+ NOTE(Important) + This feature is used for learning and debugging only. Please don't + enable it on commercial products. + If you know exactly what the impact of the feature is, you can + configure it as you do. + If unsure, say N. + endmenu
menu "CPU Power Management"