From: Marc Zyngier maz@kernel.org
mainline inclusion from mainline-v6.2-rc1 commit e2c0b51f1c9dacc68292ce9ebffbfd4204d1ca58 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8DFTV CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=...
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The CCSIDR_EL1 register contains an UNKNOWN field (which replaces fields that were actually defined in previous revisions of the architecture).
Define an 'Unkn' field type modeled after the Res0/Res1 types to allow such description. This allows the generation of
#define CCSIDR_EL1_UNKN (UL(0) | GENMASK_ULL(31, 28))
which may have its use one day. Hopefully the architecture doesn't add too many of those in the future.
Signed-off-by: Marc Zyngier maz@kernel.org Signed-off-by: Akihiko Odaki akihiko.odaki@gmail.com Reviewed-by: Mark Brown broonie@kernel.org Link: https://lore.kernel.org/r/20230112023852.42012-2-akihiko.odaki@daynix.com Signed-off-by: Oliver Upton oliver.upton@linux.dev Signed-off-by: Junhao He hejunhao3@huawei.com --- arch/arm64/tools/gen-sysreg.awk | 20 +++++++++++++++++++- arch/arm64/tools/sysreg | 2 ++ 2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk index 7f27d66a17e1..6fa0468caa00 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -103,6 +103,7 @@ END {
res0 = "UL(0)" res1 = "UL(0)" + unkn = "UL(0)"
next_bit = 63
@@ -117,11 +118,13 @@ END {
define(reg "_RES0", "(" res0 ")") define(reg "_RES1", "(" res1 ")") + define(reg "_UNKN", "(" unkn ")") print ""
reg = null res0 = null res1 = null + unkn = null
next } @@ -139,6 +142,7 @@ END {
res0 = "UL(0)" res1 = "UL(0)" + unkn = "UL(0)"
define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") @@ -166,7 +170,9 @@ END { define(reg "_RES0", "(" res0 ")") if (res1 != null) define(reg "_RES1", "(" res1 ")") - if (res0 != null || res1 != null) + if (unkn != null) + define(reg "_UNKN", "(" unkn ")") + if (res0 != null || res1 != null || unkn != null) print ""
reg = null @@ -177,6 +183,7 @@ END { op2 = null res0 = null res1 = null + unkn = null
next } @@ -195,6 +202,7 @@ END { next_bit = 0 res0 = null res1 = null + unkn = null
next } @@ -220,6 +228,16 @@ END { next }
+/^Unkn/ && (block == "Sysreg" || block == "SysregFields") { + expect_fields(2) + parse_bitdef(reg, "UNKN", $2) + field = "UNKN_" msb "_" lsb + + unkn = unkn " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + /^Field/ && (block == "Sysreg" || block == "SysregFields") { expect_fields(3) field = $3 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8e39c718c1b8..936aca8504f9 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -15,6 +15,8 @@
# Res1 <msb>[:<lsb>]
+# Unkn <msb>[:<lsb>] + # Field <msb>[:<lsb>] <name>
# Enum <msb>[:<lsb>] <name>