From: Alexander Shishkin alexander.shishkin@linux.intel.com
mainline inclusion from mainline-v5.2-rc1 commit 7b7036d47c356a40818e516a69ac81a5dcc1613f category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I47H3V CVE: NA
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Since Intel TH is capable of MSI interrupt signalling, make use of it. The way it works is, each of the 7 interrupt triggering events has its own vector in this mode, as opposed to interrupt line delivery, where all events are signalled via the same line. Failing to enable MSI, the driver falls back to using an interrupt line.
Signed-off-by: Alexander Shishkin alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org Signed-off-by: Jackie Liu liuyun01@kylinos.cn Signed-off-by: Zheng Zengkai zhengzengkai@huawei.com Reviewed-by: Xie XiuQi xiexiuqi@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- drivers/hwtracing/intel_th/intel_th.h | 3 +++ drivers/hwtracing/intel_th/pci.c | 16 ++++++++++------ 2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/intel_th/intel_th.h b/drivers/hwtracing/intel_th/intel_th.h index 6c6eb87e48a0..db3ad8ca1c48 100644 --- a/drivers/hwtracing/intel_th/intel_th.h +++ b/drivers/hwtracing/intel_th/intel_th.h @@ -238,6 +238,9 @@ enum th_mmio_idx { #define TH_CONFIGURABLE_MASTERS 256 #define TH_MSC_MAX 2
+/* Maximum IRQ vectors */ +#define TH_NVEC_MAX 8 + /** * struct intel_th - Intel TH controller * @dev: driver core's device diff --git a/drivers/hwtracing/intel_th/pci.c b/drivers/hwtracing/intel_th/pci.c index a4a5efc8435d..fecba4190bbe 100644 --- a/drivers/hwtracing/intel_th/pci.c +++ b/drivers/hwtracing/intel_th/pci.c @@ -72,11 +72,11 @@ static int intel_th_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct intel_th_drvdata *drvdata = (void *)id->driver_data; - struct resource resource[TH_MMIO_END + 1] = { + struct resource resource[TH_MMIO_END + TH_NVEC_MAX] = { [TH_MMIO_CONFIG] = pdev->resource[TH_PCI_CONFIG_BAR], [TH_MMIO_SW] = pdev->resource[TH_PCI_STH_SW_BAR], }; - int err, r = TH_MMIO_SW + 1; + int err, r = TH_MMIO_SW + 1, i; struct intel_th *th;
err = pcim_enable_device(pdev); @@ -92,10 +92,12 @@ static int intel_th_pci_probe(struct pci_dev *pdev, r++; }
- if (pdev->irq > 0) { - resource[r].flags = IORESOURCE_IRQ; - resource[r++].start = pdev->irq; - } + err = pci_alloc_irq_vectors(pdev, 1, 8, PCI_IRQ_ALL_TYPES); + if (err > 0) + for (i = 0; i < err; i++, r++) { + resource[r].flags = IORESOURCE_IRQ; + resource[r].start = pci_irq_vector(pdev, i); + }
th = intel_th_alloc(&pdev->dev, drvdata, resource, r); if (IS_ERR(th)) @@ -114,6 +116,8 @@ static void intel_th_pci_remove(struct pci_dev *pdev) struct intel_th *th = pci_get_drvdata(pdev);
intel_th_free(th); + + pci_free_irq_vectors(pdev); }
static const struct intel_th_drvdata intel_th_2x = {