From: wanghaibin wanghaibin.wang@huawei.com
euleros inclusion category: bugfix bugzilla: 46842 CVE: NA
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We clear the ICH_LRn registers when save the ICH* registers. While the next vm entry, if the ICH_LRn registers is not enough (ICH_HCR,UIE bit will be set 1),if we set ICH_HCR register before the ICH_LRn restroe, here are lots of maintenance interrupts. This patch fix it
Signed-off-by: wanghaibin wanghaibin.wang@huawei.com Signed-off-by: Xiangyou Xie xiexiangyou@huawei.com Reviewed-by: Ying Fang fangying1@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- virt/kvm/arm/hyp/vgic-v3-sr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c index e20e797a1b69..f2f3665bc926 100644 --- a/virt/kvm/arm/hyp/vgic-v3-sr.c +++ b/virt/kvm/arm/hyp/vgic-v3-sr.c @@ -248,10 +248,10 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) int i;
if (used_lrs || cpu_if->its_vpe.its_vm) { - write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); - for (i = 0; i < used_lrs; i++) __gic_v3_set_lr(cpu_if->vgic_lr[i], i); + + write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); }
/*