From: Jinke Fan fanjinke@hygon.cn
mainline inclusion from mainline-v5.5-rc1 commit 7ad295d5196a58c22abecef62dd4f99e2f86e831 category: bugfix bugzilla: NA CVE: NA ---------------------------
When using following operations: date -s "21190910 19:20:00" hwclock -w to change date from 2019 to 2119 for test, it will fail on Hygon Dhyana and AMD Zen CPUs, while the same operations run ok on Intel i7 platform.
MC146818 driver use function mc146818_set_time() to set register RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage reset value on Intel platform to 0x7.
While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]: DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined as reserved.
DV0 is set to 1, it will select Bank 1, which will disable AltCentury register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32 (AltCentury), the CMOS write will be failed on code: CMOS_WRITE(century, acpi_gbl_FADT.century).
Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will enable AltCentury(0x32) register writing and finally setup century as expected.
Test results on Intel i7, AMD EPYC(17h) and Hygon machine show that it works as expected. Compiling for sparc64 and alpha architectures are passed.
Reference: https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf section: 3.13 Real Time Clock (RTC)
Reported-by: kbuild test robot lkp@intel.com Signed-off-by: Jinke Fan fanjinke@hygon.cn Link: https://lore.kernel.org/r/20191105083943.115320-1-fanjinke@hygon.cn Signed-off-by: Alexandre Belloni alexandre.belloni@bootlin.com Signed-off-by: Hanjun Guo guohanjun@huawei.com Reviewed-by: Xie XiuQi xiexiuqi@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- drivers/rtc/rtc-mc146818-lib.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c index 18a6f15e313d..24dad215540a 100644 --- a/drivers/rtc/rtc-mc146818-lib.c +++ b/drivers/rtc/rtc-mc146818-lib.c @@ -171,7 +171,20 @@ int mc146818_set_time(struct rtc_time *time) save_control = CMOS_READ(RTC_CONTROL); CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); save_freq_select = CMOS_READ(RTC_FREQ_SELECT); - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); + +#ifdef CONFIG_X86 + if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD && + boot_cpu_data.x86 == 0x17) || + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { + CMOS_WRITE((save_freq_select & (~RTC_DIV_RESET2)), + RTC_FREQ_SELECT); + save_freq_select &= ~RTC_DIV_RESET2; + } else + CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), + RTC_FREQ_SELECT); +#else + CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT); +#endif
#ifdef CONFIG_MACH_DECSTATION CMOS_WRITE(real_yrs, RTC_DEC_YEAR);