On 2021/3/26 11:50, Tony W Wang-oc wrote:
On 26/03/2021 10:49, Hanjun Guo wrote:
On 2021/3/25 18:08, LeoLiu-oc wrote:
Add the new PCI ID 0x1d17 0x9141/0x9142/0x9144 Zhaoxin NB HDAC support. And add some special initialization for Zhaoxin NB HDAC.
The patch is scheduled to be submitted to the kernel mainline in 2021.
Signed-off-by: LeoLiu-oc LeoLiu-oc@zhaoxin.com
sound/pci/hda/hda_controller.c | 17 +++++++++++- sound/pci/hda/hda_controller.h | 2 ++ sound/pci/hda/hda_intel.c | 51 +++++++++++++++++++++++++++++++++- 3 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index 0c5d41e5d146..0341637aa5d9 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -1116,6 +1116,16 @@ void azx_stop_chip(struct azx *chip) } EXPORT_SYMBOL_GPL(azx_stop_chip);
+static void azx_rirb_zxdelay(struct azx *chip, int enable) +{ + if (chip->remap_diu_addr) { + if (!enable) + writel(0x0, (char *)chip->remap_diu_addr + 0x490a8); + else + writel(0x1000000, (char *)chip->remap_diu_addr + 0x490a8); + } +}
/* * interrupt handler */ @@ -1175,9 +1185,14 @@ irqreturn_t azx_interrupt(int irq, void *dev_id) azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); active = true; if (status & RIRB_INT_RESPONSE) { - if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) + if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) || + (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)) { + azx_rirb_zxdelay(chip, 1);
Then chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND will run extra azx_rirb_zxdelay() as well, does it have side effect?
No. azx_rirb_azdelay() only apply to Zhaoxin NB HDAC controller actually.
OK, I can see remap_diu_addr is introduced for this purpose, not good enough, but we can keep this as it is.
Reviewed-by: Hanjun Guo guohanjun@huawei.com
Thanks Hanjun