From: Ke Chen chenke54@huawei.com
driver inclusion category:feature bugzilla: https://gitee.com/openeuler/kernel/issues/I9A3QT CVE: NA
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Add HCLGE_RAS_REG_ROH_ERR_MASK to support the error recovery of the ROH ras. Add HCLGE_RAS_REG_ERR_MASK to define the combination of the nfe_mask, the rocee_err_mask and the roh_err_mask.
Add new module error types for ROH, adjust the order of these types according to the design of firmware.
Signed-off-by: Jiaran Zhang zhangjiaran@huawei.com Signed-off-by: Ke Chen chenke54@huawei.com Reviewed-by: Gang Zhang gang.zhang@huawei.com Reviewed-by: Yefeng Yan yanyefeng@huawei.com Reviewed-by: Jingchao Dai daijingchao1@huawei.com Reviewed-by: Jian Shen shenjian15@huawei.com Signed-off-by: Jiantao Xiao xiaojiantao1@h-partners.com --- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 14 +++++++++++++- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 10 +++++++++- 2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c index db1811f7578c..e198f813e063 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c @@ -1699,6 +1699,15 @@ static const struct hclge_hw_module_id hclge_hw_module_id_st[] = { }, { .module_id = MODULE_ROCEE_LSAN, .msg = "MODULE_ROCEE_LSAN" + }, { + .module_id = MODULE_ROH_MAC_IF, + .msg = "MODULE_ROH_MAC_IF" + }, { + .module_id = MODULE_ROH_HDLC, + .msg = "MODULE_ROH_HDLC" + }, { + .module_id = MODULE_ROH_HPCS, + .msg = "MODULE_ROH_HPCS" } };
@@ -1759,7 +1768,10 @@ static const struct hclge_hw_type_id hclge_hw_type_id_st[] = { }, { .type_id = ROCEE_BUS_ERR, .msg = "rocee_bus_error" - }, + }, { + .type_id = ROH_ERR, + .msg = "roh_error" + } };
static void hclge_log_error(struct device *dev, char *reg, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h index 45a783a50643..1667a6466f37 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h @@ -16,8 +16,10 @@ #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00 #define HCLGE_RAS_REG_NFE_MASK 0xFF00 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000 +#define HCLGE_RAS_REG_ROH_ERR_MASK 0x18000000 #define HCLGE_RAS_REG_ERR_MASK \ - (HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK) + (HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK | \ + HCLGE_RAS_REG_ROH_ERR_MASK)
#define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
@@ -164,6 +166,10 @@ enum hclge_mod_name_list { MODULE_ROCEE_QMM = 48, MODULE_ROCEE_LSAN = 49, /* add new MODULE NAME for RoCEE here in order */ + MODULE_ROH_MAC_IF = 80, + MODULE_ROH_HDLC = 81, + MODULE_ROH_HPCS = 82, + /* add new MODULE NAME for ROH here in order */ };
enum hclge_err_type_list { @@ -187,6 +193,8 @@ enum hclge_err_type_list { ROCEE_OVF_ERR = 41, ROCEE_BUS_ERR = 42, /* add new ERROR TYPE for ROCEE here in order */ + ROH_ERR = 80, + /* add new ERROR TYPE for ROH here in order */ };
struct hclge_hw_blk {