hulk inclusion category: performance bugzilla: https://gitee.com/openeuler/kernel/issues/I9PMP7 CVE: NA
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On some Hisilicon platforms, like Kunpeng920, L3 cacheline size is 128 byte, enable CONFIG_ARCH_LLC_128_LINE_SIZE for these hisilicon platforms by default.
Signed-off-by: Zheng Zengkai zhengzengkai@huawei.com --- arch/arm64/Kconfig | 4 ++-- arch/arm64/configs/openeuler_defconfig | 1 + 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 5576ddf63622..2a875546bdc7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1608,8 +1608,8 @@ config HW_PERF_EVENTS
config ARCH_LLC_128_LINE_SIZE bool "Force 128 bytes alignment for fitting LLC cacheline" - depends on ARM64 - default y + depends on ARCH_HISI + default n help As specific machine's LLC cacheline size may be up to 128 bytes, gaining performance improvement from fitting diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 4932a6be9d6f..6a73a3fd2994 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -477,6 +477,7 @@ CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_LLC_128_LINE_SIZE=y CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_PARAVIRT=y CONFIG_PARAVIRT_SCHED=y