tree: https://gitee.com/openeuler/kernel.git openEuler-1.0-LTS head: 3a28772f4b29bdda924e9a5d2e3ff1ff1b23fd14 commit: 73d33f5c59dc3824444baca6a458427f4de3d8fa [13192/21616] qm: Move all the same logic functions of hisilicon crypto to qm config: arm64-randconfig-002-20240205 (https://download.01.org/0day-ci/archive/20240206/202402060939.zvTpc916-lkp@i...) compiler: aarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240206/202402060939.zvTpc916-lkp@i...)

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot lkp@intel.com | Closes: https://lore.kernel.org/oe-kbuild-all/202402060939.zvTpc916-lkp@intel.com/

All warnings (new ones prefixed by >>):

...

drivers/crypto/hisilicon/qm.c:2726: warning: Excess function parameter 'ce' description in 'qm_hw_error_init' drivers/crypto/hisilicon/qm.c:2726: warning: Excess function parameter 'nfe' description in 'qm_hw_error_init' drivers/crypto/hisilicon/qm.c:2726: warning: Excess function parameter 'fe' description in 'qm_hw_error_init' drivers/crypto/hisilicon/qm.c:2726: warning: Excess function parameter 'msi' description in 'qm_hw_error_init'

vim +2726 drivers/crypto/hisilicon/qm.c

ae67d23af736c7 xuzaibo 2019-04-21 2706 ae67d23af736c7 xuzaibo 2019-04-21 2707 /** 73d33f5c59dc38 Yu'an Wang 2020-04-16 2708 * qm_hw_error_init() - Configure qm hardware error report method. ae67d23af736c7 xuzaibo 2019-04-21 2709 * @qm: The qm which we want to configure. ae67d23af736c7 xuzaibo 2019-04-21 2710 * @ce: Correctable error configure. ae67d23af736c7 xuzaibo 2019-04-21 2711 * @nfe: Non-fatal error configure. ae67d23af736c7 xuzaibo 2019-04-21 2712 * @fe: Fatal error configure. ae67d23af736c7 xuzaibo 2019-04-21 2713 * @msi: Error reported by message signal interrupt. ae67d23af736c7 xuzaibo 2019-04-21 2714 * ae67d23af736c7 xuzaibo 2019-04-21 2715 * Hardware errors of qm can be reported either by RAS interrupts which will ae67d23af736c7 xuzaibo 2019-04-21 2716 * be handled by UEFI and then PCIe AER or by device MSI. User can configure ae67d23af736c7 xuzaibo 2019-04-21 2717 * each error to use either of above two methods. For RAS interrupts, we can ae67d23af736c7 xuzaibo 2019-04-21 2718 * configure an error as one of correctable error, non-fatal error or ae67d23af736c7 xuzaibo 2019-04-21 2719 * fatal error. ae67d23af736c7 xuzaibo 2019-04-21 2720 * ae67d23af736c7 xuzaibo 2019-04-21 2721 * Bits indicating errors can be configured to ce, nfe, fe and msi to enable ae67d23af736c7 xuzaibo 2019-04-21 2722 * related report methods. Error report will be masked if related error bit ae67d23af736c7 xuzaibo 2019-04-21 2723 * does not configure. ae67d23af736c7 xuzaibo 2019-04-21 2724 */ 73d33f5c59dc38 Yu'an Wang 2020-04-16 2725 static void qm_hw_error_init(struct hisi_qm *qm) ae67d23af736c7 xuzaibo 2019-04-21 @2726 { 73d33f5c59dc38 Yu'an Wang 2020-04-16 2727 u32 nfe = qm->err_ini.err_info.nfe; 73d33f5c59dc38 Yu'an Wang 2020-04-16 2728 u32 msi = qm->err_ini.err_info.msi; 73d33f5c59dc38 Yu'an Wang 2020-04-16 2729 u32 ce = qm->err_ini.err_info.ce; 73d33f5c59dc38 Yu'an Wang 2020-04-16 2730 u32 fe = qm->err_ini.err_info.fe; 73d33f5c59dc38 Yu'an Wang 2020-04-16 2731 ae67d23af736c7 xuzaibo 2019-04-21 2732 if (!qm->ops->hw_error_init) { ae67d23af736c7 xuzaibo 2019-04-21 2733 dev_err(&qm->pdev->dev, ae67d23af736c7 xuzaibo 2019-04-21 2734 "QM version %d doesn't support hw error handling!\n", ae67d23af736c7 xuzaibo 2019-04-21 2735 qm->ver); ae67d23af736c7 xuzaibo 2019-04-21 2736 return; ae67d23af736c7 xuzaibo 2019-04-21 2737 } ae67d23af736c7 xuzaibo 2019-04-21 2738 efe221f95003ac Zhou Wang 2019-07-11 2739 qm->ops->hw_error_init(qm, ce, nfe, fe, msi); ae67d23af736c7 xuzaibo 2019-04-21 2740 } ae67d23af736c7 xuzaibo 2019-04-21 2741

:::::: The code at line 2726 was first introduced by commit :::::: ae67d23af736c75f90795297fddb86dc97e7b3c7 arm64: Add hisilicon Crypto drivers qm/hpre/zip and code format

:::::: TO: xuzaibo xuzaibo@huawei.com :::::: CC: Xie XiuQi xiexiuqi@huawei.com