tree: https://gitee.com/openeuler/kernel.git openEuler-1.0-LTS head: 22c50245e8025b0c6beee13d0df238987b98e6f8 commit: 267bce716c1008522c3b8ddbeac8d3c65514e98f [21583/23866] crypto: hisilicon/qm - drop unnecessary IS_ENABLE(CONFIG_NUMA) check config: arm64-randconfig-002-20241026 (https://download.01.org/0day-ci/archive/20241027/202410270513.RTL2eHIu-lkp@i...) compiler: aarch64-linux-gcc (GCC) 14.1.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241027/202410270513.RTL2eHIu-lkp@i...)

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot lkp@intel.com | Closes: https://lore.kernel.org/oe-kbuild-all/202410270513.RTL2eHIu-lkp@intel.com/

All warnings (new ones prefixed by >>):

...

drivers/crypto/hisilicon/qm.c:3322: warning: Excess function parameter 'ce' description in 'qm_hw_error_init' drivers/crypto/hisilicon/qm.c:3322: warning: Excess function parameter 'nfe' description in 'qm_hw_error_init' drivers/crypto/hisilicon/qm.c:3322: warning: Excess function parameter 'fe' description in 'qm_hw_error_init' drivers/crypto/hisilicon/qm.c:3322: warning: Excess function parameter 'msi' description in 'qm_hw_error_init'

vim +3322 drivers/crypto/hisilicon/qm.c

ae67d23af736c7 xuzaibo 2019-04-21 3302 ae67d23af736c7 xuzaibo 2019-04-21 3303 /** 73d33f5c59dc38 Yu'an Wang 2020-04-16 3304 * qm_hw_error_init() - Configure qm hardware error report method. ae67d23af736c7 xuzaibo 2019-04-21 3305 * @qm: The qm which we want to configure. ae67d23af736c7 xuzaibo 2019-04-21 3306 * @ce: Correctable error configure. ae67d23af736c7 xuzaibo 2019-04-21 3307 * @nfe: Non-fatal error configure. ae67d23af736c7 xuzaibo 2019-04-21 3308 * @fe: Fatal error configure. ae67d23af736c7 xuzaibo 2019-04-21 3309 * @msi: Error reported by message signal interrupt. ae67d23af736c7 xuzaibo 2019-04-21 3310 * ae67d23af736c7 xuzaibo 2019-04-21 3311 * Hardware errors of qm can be reported either by RAS interrupts which will ae67d23af736c7 xuzaibo 2019-04-21 3312 * be handled by UEFI and then PCIe AER or by device MSI. User can configure ae67d23af736c7 xuzaibo 2019-04-21 3313 * each error to use either of above two methods. For RAS interrupts, we can ae67d23af736c7 xuzaibo 2019-04-21 3314 * configure an error as one of correctable error, non-fatal error or ae67d23af736c7 xuzaibo 2019-04-21 3315 * fatal error. ae67d23af736c7 xuzaibo 2019-04-21 3316 * ae67d23af736c7 xuzaibo 2019-04-21 3317 * Bits indicating errors can be configured to ce, nfe, fe and msi to enable ae67d23af736c7 xuzaibo 2019-04-21 3318 * related report methods. Error report will be masked if related error bit ae67d23af736c7 xuzaibo 2019-04-21 3319 * does not configure. ae67d23af736c7 xuzaibo 2019-04-21 3320 */ 73d33f5c59dc38 Yu'an Wang 2020-04-16 3321 static void qm_hw_error_init(struct hisi_qm *qm) ae67d23af736c7 xuzaibo 2019-04-21 @3322 { 73d33f5c59dc38 Yu'an Wang 2020-04-16 3323 u32 nfe = qm->err_ini.err_info.nfe; 73d33f5c59dc38 Yu'an Wang 2020-04-16 3324 u32 msi = qm->err_ini.err_info.msi; 73d33f5c59dc38 Yu'an Wang 2020-04-16 3325 u32 ce = qm->err_ini.err_info.ce; 73d33f5c59dc38 Yu'an Wang 2020-04-16 3326 u32 fe = qm->err_ini.err_info.fe; 73d33f5c59dc38 Yu'an Wang 2020-04-16 3327 ae67d23af736c7 xuzaibo 2019-04-21 3328 if (!qm->ops->hw_error_init) { ae67d23af736c7 xuzaibo 2019-04-21 3329 dev_err(&qm->pdev->dev, ae67d23af736c7 xuzaibo 2019-04-21 3330 "QM version %d doesn't support hw error handling!\n", ae67d23af736c7 xuzaibo 2019-04-21 3331 qm->ver); ae67d23af736c7 xuzaibo 2019-04-21 3332 return; ae67d23af736c7 xuzaibo 2019-04-21 3333 } ae67d23af736c7 xuzaibo 2019-04-21 3334 efe221f95003ac Zhou Wang 2019-07-11 3335 qm->ops->hw_error_init(qm, ce, nfe, fe, msi); ae67d23af736c7 xuzaibo 2019-04-21 3336 } ae67d23af736c7 xuzaibo 2019-04-21 3337

:::::: The code at line 3322 was first introduced by commit :::::: ae67d23af736c75f90795297fddb86dc97e7b3c7 arm64: Add hisilicon Crypto drivers qm/hpre/zip and code format

:::::: TO: xuzaibo xuzaibo@huawei.com :::::: CC: Xie XiuQi xiexiuqi@huawei.com