Juxin Gao (1): drivers/irqchip: Disable pci_irq_limit when using AVEC interrupt controller
Tianyang Zhang (1): irqchip/avec: Support AVEC for 3C6000 multi-node machine
arch/loongarch/include/asm/setup.h | 1 + drivers/irqchip/irq-loongarch-avec.c | 11 +++++++++-- drivers/pci/msi/msi.c | 18 ++++++++++++------ 3 files changed, 22 insertions(+), 8 deletions(-)
From: Tianyang Zhang zhangtianyang@loongson.cn
LoongArch inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/IB8166 CVE: NA
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This patch enables AVEC functionality for 3C6000 multi-node machine.
The topology of the advanced interrupt controller is consistent with NUMA node. We check the enable status of the node where each CPU is located once when it goes online, which may cause some additional operations, but it can ensure that the advanced interrupt controller can still be used in situations where some CPUs cannot start.
In addition, this patch alse fix a bug that use ipi method to clean expired affinity on multiple nodes.
Signed-off-by: Tianyang Zhang zhangtianyang@loongson.cn --- drivers/irqchip/irq-loongarch-avec.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongarch-avec.c b/drivers/irqchip/irq-loongarch-avec.c index e8c43b3fd826..2f7e64d22ad3 100644 --- a/drivers/irqchip/irq-loongarch-avec.c +++ b/drivers/irqchip/irq-loongarch-avec.c @@ -83,7 +83,7 @@ static void avecintc_sync(struct avecintc_data *adata) plist = per_cpu_ptr(&pending_list, adata->prev_cpu); list_add_tail(&adata->entry, &plist->head); adata->moving = 1; - smp_ops.send_ipi_single(adata->prev_cpu, SMP_CLEAR_VECTOR); + smp_ops.send_ipi_single(adata->prev_cpu, ACTION_CLEAR_VECTOR); } }
@@ -132,6 +132,7 @@ static int avecintc_set_affinity(struct irq_data *data, const struct cpumask *de
static int avecintc_cpu_online(unsigned int cpu) { + long value; if (!loongarch_avec.vector_matrix) return 0;
@@ -141,6 +142,10 @@ static int avecintc_cpu_online(unsigned int cpu)
pending_list_init(cpu);
+ value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC); + value |= IOCSR_MISC_FUNC_AVEC_EN; + iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC); + raw_spin_unlock(&loongarch_avec.lock);
return 0; @@ -193,7 +198,7 @@ void complete_irq_moving(void) }
if (isr & (1UL << (vector % VECTORS_PER_REG))) { - smp_ops.send_ipi_single(cpu, SMP_CLEAR_VECTOR); + smp_ops.send_ipi_single(cpu, ACTION_CLEAR_VECTOR); continue; } list_del(&adata->entry);
From: Juxin Gao gaojuxin@loongson.cn
LoongArch inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/IB8166 CVE: NA
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In the new interrupt model, the AVEC interrupt controller no longer has a limit on the number of interrupts like the extended interrupt controller, so when using the avec interrupt model, pci_irq_limit is disabled by default.
Signed-off-by: Juxin Gao gaojuxin@loongson.cn --- arch/loongarch/include/asm/setup.h | 1 + drivers/irqchip/irq-loongarch-avec.c | 2 ++ drivers/pci/msi/msi.c | 18 ++++++++++++------ 3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/loongarch/include/asm/setup.h b/arch/loongarch/include/asm/setup.h index ee52fb1e9963..eefb30c33ba3 100644 --- a/arch/loongarch/include/asm/setup.h +++ b/arch/loongarch/include/asm/setup.h @@ -12,6 +12,7 @@
#define VECSIZE 0x200
+extern bool disable_pci_irq_limit; extern unsigned long eentry; extern unsigned long tlbrentry; extern char init_command_line[COMMAND_LINE_SIZE]; diff --git a/drivers/irqchip/irq-loongarch-avec.c b/drivers/irqchip/irq-loongarch-avec.c index 2f7e64d22ad3..2f79a53e35a9 100644 --- a/drivers/irqchip/irq-loongarch-avec.c +++ b/drivers/irqchip/irq-loongarch-avec.c @@ -30,6 +30,7 @@ struct pending_list { struct list_head head; };
+bool disable_pci_irq_limit; static struct cpumask intersect_mask; static DEFINE_PER_CPU(struct pending_list, pending_list); #endif @@ -372,6 +373,7 @@ static int __init avecintc_init(struct irq_domain *parent) int ret, parent_irq; unsigned long value;
+ disable_pci_irq_limit = true; raw_spin_lock_init(&loongarch_avec.lock);
loongarch_avec.fwnode = irq_domain_alloc_named_fwnode("AVECINTC"); diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 785bbf637ab5..4eea161663b1 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -421,6 +421,8 @@ static int msi_capability_init(struct pci_dev *dev, int nvec, }
#ifdef CONFIG_LOONGARCH +#include <asm/setup.h> + static unsigned int pci_irq_numbers = 32;
static int __init pci_irq_limit(char *str) @@ -442,9 +444,11 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, int rc;
#ifdef CONFIG_LOONGARCH - if (maxvec > 32) { - maxvec = pci_irq_numbers; - minvec = min_t(int, pci_irq_numbers, minvec); + if (!disable_pci_irq_limit) { + if (maxvec > 32) { + maxvec = pci_irq_numbers; + minvec = min_t(int, pci_irq_numbers, minvec); + } } #endif
@@ -838,9 +842,11 @@ int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int int hwsize, rc, nvec = maxvec;
#ifdef CONFIG_LOONGARCH - if (maxvec > 32) { - nvec = pci_irq_numbers; - minvec = min_t(int, pci_irq_numbers, minvec); + if (!disable_pci_irq_limit) { + if (maxvec > 32) { + nvec = pci_irq_numbers; + minvec = min_t(int, pci_irq_numbers, minvec); + } } #endif
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