[PATCH openEuler-1.0-LTS 0/5] errata and bugfix for openEuler 20.03
errata and bugfix for openEuler 20.03 *** BLURB HERE *** Cheng Jian (1): config/x86: enable SHRINK_PAGECACHE Kai Shen (1): arm64: errata: add option to disable cache readunique prefetch on 1620 Xie XiuQi (2): arm64: errata: fix kabi changed for cpu_errata arm64: errata: enable HISILICON_ERRATUM_HIP08_RU_PREFETCH Zheng Zengkai (1): arm64: Add config switch and kernel parameter for CPU0 hotplug .../admin-guide/kernel-parameters.txt | 8 +++ arch/arm64/Kconfig | 46 +++++++++++++ arch/arm64/configs/openeuler_defconfig | 2 + arch/arm64/kernel/cpu_errata.c | 67 +++++++++++++++++++ arch/arm64/kernel/setup.c | 18 ++++- arch/x86/configs/hulk_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 2 +- 7 files changed, 142 insertions(+), 2 deletions(-) -- 2.25.1
From: Kai Shen <shenkai8@huawei.com> hulk inclusion category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=28 CVE: NA --------------------------- Random performance decreases appear on cases of Hackbench which test pipe or socket communication among multi-threads on Hisi HIP08 SoC. Cache sharing which caused by the change of the data layout and the cache readunique prefetch mechanism both lead to this problem. Readunique mechanism which may caused by store operation will invalid cachelines on other cores during data fetching stage which can cause cacheline invalidation happens frequently in a sharing data access situation. Disable cache readunique prefetch can trackle this problem. Test cases are like: for i in 20;do echo "--------pipe thread num=$i----------" for j in $(seq 1 10);do ./hackbench -pipe $i thread 1000 done done We disable readunique prefetch only in el2 for in el1 disabling readunique prefetch may cause panic due to lack of related priority which often be set in BIOS. Introduce CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH and disable RU prefetch using boot cmdline 'readunique_prefetch=off'. Signed-off-by: Kai Shen <shenkai8@huawei.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com> [XQ: adjusted context] Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com> Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> --- arch/arm64/Kconfig | 18 ++++++++++ arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/kernel/cpu_errata.c | 56 ++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index d8917873f549..058a73bf556d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -625,6 +625,24 @@ config QCOM_FALKOR_ERRATUM_E1041 If unsure, say Y. +config HISILICON_ERRATUM_HIP08_RU_PREFETCH + bool "HIP08 RU: HiSilicon HIP08 cache readunique might cause performance drop" + default y + help + The HiSilicon HIP08 cache readunique might compromise performance, + use cmdline "readunique_prefetch_disable" to disable RU prefetch. + + If unsure, say Y. + +config HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF + bool "HIP08 RU: disable HiSilicon HIP08 cache readunique by default" + depends on HISILICON_ERRATUM_HIP08_RU_PREFETCH + default n + help + Disable HiSilicon HIP08 cache readunique by default. + + If unsure, say N. + endmenu diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index a9090f204a08..85446098342d 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -56,7 +56,8 @@ #define ARM64_WORKAROUND_1463225 35 #define ARM64_HAS_CRC32 36 #define ARM64_SSBS 37 +#define ARM64_WORKAROUND_HISI_HIP08_RU_PREFETCH 38 -#define ARM64_NCAPS 38 +#define ARM64_NCAPS 39 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index c0b2ef5e7ea3..881187d5fed6 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -24,6 +24,11 @@ #include <asm/cputype.h> #include <asm/cpufeature.h> #include <asm/smp_plat.h> +#ifdef CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH +#include <asm/ptrace.h> +#include <asm/sysreg.h> +#include <linux/smp.h> +#endif static bool __maybe_unused is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) @@ -491,6 +496,48 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); } +#ifdef CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH +# ifdef CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF +static bool readunique_prefetch_enabled; +# else +static bool readunique_prefetch_enabled = true; +# endif +static int __init readunique_prefetch_switch(char *data) +{ + if (!data) + return -EINVAL; + + if (strcmp(data, "off") == 0) + readunique_prefetch_enabled = false; + else if (strcmp(data, "on") == 0) + readunique_prefetch_enabled = true; + else + return -EINVAL; + + return 0; +} +early_param("readunique_prefetch", readunique_prefetch_switch); + +static bool +should_disable_hisi_hip08_ru_prefetch(const struct arm64_cpu_capabilities *entry, int unused) +{ + u64 el; + + if (readunique_prefetch_enabled) + return false; + + el = read_sysreg(CurrentEL); + return el == CurrentEL_EL2; +} + +#define CTLR_HISI_HIP08_RU_PREFETCH (1L << 40) +static void __maybe_unused +hisi_hip08_ru_prefetch_disable(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(S3_1_c15_c6_4, 0, CTLR_HISI_HIP08_RU_PREFETCH); +} +#endif + /* known invulnerable cores */ static const struct midr_range arm64_ssb_cpus[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), @@ -870,6 +917,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), .matches = needs_tx2_tvm_workaround, }, +#endif +#ifdef CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH + { + .desc = "HiSilicon HIP08 Cache Readunique Prefetch Disable", + .capability = ARM64_WORKAROUND_HISI_HIP08_RU_PREFETCH, + ERRATA_MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + .matches = should_disable_hisi_hip08_ru_prefetch, + .cpu_enable = hisi_hip08_ru_prefetch_disable, + }, #endif { } -- 2.25.1
From: Xie XiuQi <xiexiuqi@huawei.com> hulk inclusion category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=28 CVE: NA Patch "arm64: errata: add option to disable cache readunique prefetch" breaks the kabi symbols: cpu_hwcaps cpu_hwcap_keys Fix it by using late_initcall instead arm64_errata mechanism. Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com> Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> --- arch/arm64/include/asm/cpucaps.h | 3 +-- arch/arm64/kernel/cpu_errata.c | 33 +++++++++++++++++++++----------- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 85446098342d..a9090f204a08 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -56,8 +56,7 @@ #define ARM64_WORKAROUND_1463225 35 #define ARM64_HAS_CRC32 36 #define ARM64_SSBS 37 -#define ARM64_WORKAROUND_HISI_HIP08_RU_PREFETCH 38 -#define ARM64_NCAPS 39 +#define ARM64_NCAPS 38 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 881187d5fed6..706a77a121f1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -518,24 +518,44 @@ static int __init readunique_prefetch_switch(char *data) } early_param("readunique_prefetch", readunique_prefetch_switch); +static const struct midr_range readunique_prefetch_cpus[] = { + MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + {}, +}; + static bool -should_disable_hisi_hip08_ru_prefetch(const struct arm64_cpu_capabilities *entry, int unused) +should_disable_hisi_hip08_ru_prefetch(void) { u64 el; if (readunique_prefetch_enabled) return false; + if (!is_midr_in_range_list(read_cpuid_id(), readunique_prefetch_cpus)) + return false; + el = read_sysreg(CurrentEL); return el == CurrentEL_EL2; } #define CTLR_HISI_HIP08_RU_PREFETCH (1L << 40) static void __maybe_unused -hisi_hip08_ru_prefetch_disable(const struct arm64_cpu_capabilities *__unused) +__hisi_hip08_ru_prefetch_disable(void* unused) { sysreg_clear_set(S3_1_c15_c6_4, 0, CTLR_HISI_HIP08_RU_PREFETCH); } + +static int hisi_hip08_ru_prefetch_disable(void) +{ + if (should_disable_hisi_hip08_ru_prefetch()) { + on_each_cpu(__hisi_hip08_ru_prefetch_disable, NULL, 1); + pr_info("CPU erratum: HiSilicon HIP08 Cache Readunique Prefetch Disable"); + } + + return 0; +} + +late_initcall(hisi_hip08_ru_prefetch_disable); #endif /* known invulnerable cores */ @@ -917,15 +937,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), .matches = needs_tx2_tvm_workaround, }, -#endif -#ifdef CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH - { - .desc = "HiSilicon HIP08 Cache Readunique Prefetch Disable", - .capability = ARM64_WORKAROUND_HISI_HIP08_RU_PREFETCH, - ERRATA_MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), - .matches = should_disable_hisi_hip08_ru_prefetch, - .cpu_enable = hisi_hip08_ru_prefetch_disable, - }, #endif { } -- 2.25.1
From: Xie XiuQi <xiexiuqi@huawei.com> hulk inclusion category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=28 CVE: NA enable CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH, to add a cmdline option to disable prefetch. Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com> Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> --- arch/arm64/configs/openeuler_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 19b1f9bc31a3..fc7065339051 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -401,6 +401,8 @@ CONFIG_QCOM_QDF2400_ERRATUM_0065=y CONFIG_SOCIONEXT_SYNQUACER_PREITS=y CONFIG_HISILICON_ERRATUM_161600802=y CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH=y +# CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF is not set # CONFIG_ARM64_4K_PAGES is not set # CONFIG_ARM64_16K_PAGES is not set CONFIG_ARM64_64K_PAGES=y -- 2.25.1
From: Zheng Zengkai <zhengzengkai@huawei.com> hulk inclusion category: feature bugzilla: 51775 CVE: NA ------------------------------------------------- New config switch CONFIG_ARM64_BOOTPARAM_HOTPLUG_CPU0 sets default state of whether the CPU0 hotplug is on or off. If the config switch is off, CPU0 is not hotpluggable by default. But the CPU0 hotplug feature can still be turned on by kernel parameter arm64_cpu0_hotplug at boot. If the config switch is on, CPU0 is always hotpluggable. The default value of the config switch is off. Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com> Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> --- .../admin-guide/kernel-parameters.txt | 8 ++++++ arch/arm64/Kconfig | 28 +++++++++++++++++++ arch/arm64/kernel/setup.c | 18 +++++++++++- 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 2fc1504e6c02..d24c8c9bb7d7 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3107,6 +3107,14 @@ If the dependencies are under your control, you can turn on cpu0_hotplug. + arm64_cpu0_hotplug [ARM64] Turn on CPU0 hotplug feature when + CONFIG_ARM64_BOOTPARAM_HOTPLUG_CPU0 is off. + Some features depend on CPU0. Known dependency is: + MegaRAID Tri-Mode SAS3508 may block the reboot process + after offline CPU0. + If the dependencies are under your control, you can + turn on arm64_cpu0_hotplug. + nps_mtm_hs_ctr= [KNL,ARC] This parameter sets the maximum duration, in cycles, each HW thread of the CTOP can run diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 058a73bf556d..37c5064a2e34 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -774,6 +774,34 @@ config HOTPLUG_CPU Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. +config ARM64_BOOTPARAM_HOTPLUG_CPU0 + bool "Set default setting of arm64_cpu0_hotpluggable" + default n + depends on HOTPLUG_CPU + help + Set whether default state of arm64_cpu0_hotpluggable is on or off. + + Say Y here to enable CPU0 hotplug by default. If this switch + is turned on, there is no need to give arm64_cpu0_hotplug kernel + parameter and the CPU0 hotplug feature is enabled by default. + + Please note: there may be some CPU0 dependencies if you want + to enable the CPU0 hotplug feature either by this switch or by + arm64_cpu0_hotplug kernel parameter. + + For example: + We found the following issue related to CPU0 dependency: + 1. echo 0 > /sys/devices/system/cpu/cpu0/online + 2. reboot + MegaRAID Tri-Mode SAS3508 may block the reboot process. + + Please make sure the dependencies are under your control before + you enable this feature. + + Say N if you don't want to enable CPU0 hotplug feature by default. + You still can enable the CPU0 hotplug feature at boot by kernel + parameter arm64_cpu0_hotplug. + config ARM64_ERR_RECOV bool "Support arm64 RAS error recovery" depends on ACPI_APEI_SEA && MEMORY_FAILURE diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 0bd2a5320736..0325fbdfc046 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -68,6 +68,19 @@ static int num_standard_resources; static struct resource *standard_resources; +#ifdef CONFIG_ARM64_BOOTPARAM_HOTPLUG_CPU0 +static int arm64_cpu0_hotpluggable = 1; +#else +static int arm64_cpu0_hotpluggable; +static int __init arm64_enable_cpu0_hotplug(char *str) +{ + arm64_cpu0_hotpluggable = 1; + return 1; +} + +__setup("arm64_cpu0_hotplug", arm64_enable_cpu0_hotplug); +#endif + phys_addr_t __fdt_pointer __initdata; /* @@ -392,7 +405,10 @@ static int __init topology_init(void) for_each_present_cpu(i) { struct cpu *cpu = &per_cpu(cpu_data.cpu, i); - cpu->hotpluggable = 1; + if (i == 0) + cpu->hotpluggable = arm64_cpu0_hotpluggable; + else + cpu->hotpluggable = 1; register_cpu(cpu, i); } -- 2.25.1
hulk inclusion category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=20 CVE: NA ------------------------------------------------- SHRINK_PAGECACHE means that we do not want to keep the large number of page cache in the system, Even though it will greatly improve the performance of the machine. It is asked by the user to keep the free memory as much as possible. Apparently, it will influence the informace. This prevents the pagecache from consuming too much memory. enable CONFIG_SHRINK_PAGECACHE this time. Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> --- arch/x86/configs/hulk_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/configs/hulk_defconfig b/arch/x86/configs/hulk_defconfig index 616f35475a15..60f198771a20 100644 --- a/arch/x86/configs/hulk_defconfig +++ b/arch/x86/configs/hulk_defconfig @@ -995,6 +995,7 @@ CONFIG_THP_SWAP=y CONFIG_TRANSPARENT_HUGE_PAGECACHE=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y +CONFIG_SHRINK_PAGECACHE=y # CONFIG_CMA is not set CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index ad86eb248cc4..f8f9fb59c300 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -992,7 +992,7 @@ CONFIG_THP_SWAP=y CONFIG_TRANSPARENT_HUGE_PAGECACHE=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y -# CONFIG_SHRINK_PAGECACHE is not set +CONFIG_SHRINK_PAGECACHE=y # CONFIG_CMA is not set CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y -- 2.25.1
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Cheng Jian