1. Added support for HiSilicon T6 ETM 2. Fix CPU hold issue caused by hip09 ETM overflow
Junhao He (3): coresight: etm4x: Add Support for HiSilicon T6 ETM coresight: etm4x: Workaround CPU hung bug on hip09 perf cs-etm: add error logging to cs_etm_is_etmv4()
.../hwtracing/coresight/coresight-etm4x-core.c | 15 ++++++++++++++- tools/perf/arch/arm/util/cs-etm.c | 11 ++++++----- 2 files changed, 20 insertions(+), 6 deletions(-)
driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I79882 CVE: NA
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Add ETMv4 periperhal ID for HiSilicon T6 platform.
Signed-off-by: Junhao He hejunhao3@huawei.com --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 95c92d2d3915..fa6f3604437f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2118,6 +2118,7 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ + CS_AMBA_UCI_ID(0x000b6d45, uci_id_etm4),/* HiSilicon-T6 */ {}, };
driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I79882 CVE: NA
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Workaround this issue on HiSilicon ETM by setting bit 13 of TRCAUXCTLR which is used to indicate that the ETM is in the idle state.
Signed-off-by: Junhao He hejunhao3@huawei.com --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index fa6f3604437f..46522839e684 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -262,6 +262,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
#define HISI_HIP08_AMBA_ID 0x000b6d01 +#define HISI_HIP09_AMBA_ID 0x000b6d02 #define ETM4_AMBA_MASK 0xfffff #define HISI_HIP08_CORE_COMMIT_MASK 0x3000 #define HISI_HIP08_CORE_COMMIT_SHIFT 12 @@ -280,6 +281,11 @@ static bool etm4_hisi_match_pid(unsigned int id) return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID; }
+static bool etm4_hisi_hip09_match_pid(unsigned int id) +{ + return (id & ETM4_AMBA_MASK) == HISI_HIP09_AMBA_ID; +} + static void etm4_hisi_config_core_commit(void *info) { bool enable = *(bool *)info; @@ -302,9 +308,12 @@ static void etm4_hisi_config_core_commit(void *info) static void etm4_hisi_config_set_auxctrlr(void *info) { struct csdev_access *csa = info; + u32 trcauxctlr;
/* Switch the ETM to idle state */ - etm4x_relaxed_write32(csa, HISI_HIP08_AUXCTRL_CHICKEN_BIT, TRCAUXCTLR); + trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); + trcauxctlr |= HISI_HIP08_AUXCTRL_CHICKEN_BIT; + etm4x_relaxed_write32(csa, trcauxctlr, TRCAUXCTLR); }
static struct etm4_arch_features etm4_features[] = { @@ -355,6 +364,9 @@ static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features); set_bit(ETM4_IMPDEF_HISI_SET_AUXCTRLR, drvdata->arch_features); } + + if (etm4_hisi_hip09_match_pid(id)) + set_bit(ETM4_IMPDEF_HISI_SET_AUXCTRLR, drvdata->arch_features); } #else static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I79882 CVE: NA
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When setting up SMT, not every process has an ETM, so the path ".../cs_etm/cpux/trcidr/trcidr0" does not exist, and the function perf_pmu__scan_file() will return an error. Log a error when read fails.
Signed-off-by: Junhao He hejunhao3@huawei.com --- tools/perf/arch/arm/util/cs-etm.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 7af0130b3040..b4a53afe6712 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -558,7 +558,7 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu) { - bool ret = false; + bool ret = true; char path[PATH_MAX]; int scan; unsigned int val; @@ -570,10 +570,11 @@ static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu) snprintf(path, PATH_MAX, "cpu%d/%s", cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]); scan = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val); - - /* The file was read successfully, we have a winner */ - if (scan == 1) - ret = true; + if (scan != 1) { + pr_err("%s: can't read file %s\n", + CORESIGHT_ETM_PMU_NAME, path); + ret = false; + }
return ret; }
-
Junhao He