tree: https://gitee.com/openeuler/kernel.git OLK-6.6 head: 46064348cc445799cf9e8fd030323a0426fbb5e4 commit: c74ae2c5da57becf3f41c596d79b3dd30fa1baa6 [1640/1640] hct: add mediated ccp driver support for hygon crypto technology. config: x86_64-randconfig-161-20241217 (https://download.01.org/0day-ci/archive/20241217/202412172322.TKo92WwH-lkp@i...) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot lkp@intel.com | Closes: https://lore.kernel.org/oe-kbuild-all/202412172322.TKo92WwH-lkp@intel.com/

smatch warnings: drivers/crypto/ccp/hygon/hct.c:362 hct_dev_cmd_queue_init() warn: always true condition '(dev_ctx->q_count >= 0) => (0-u32max >= 0)' drivers/crypto/ccp/hygon/hct.c:668 hct_write() warn: potential spectre issue 'dev_ctx->cmd_q' [r] drivers/crypto/ccp/hygon/hct.c:672 hct_write() warn: potential spectre issue 'mdev_state->trigger' [r] drivers/crypto/ccp/hygon/hct.c:1384 is_dma_share() warn: always true condition '(dma_iova >= 0) => (0-u64max >= 0)'

vim +362 drivers/crypto/ccp/hygon/hct.c

295 296 static int hct_dev_cmd_queue_init(struct pci_dev *pdev, struct hct_dev_ctx *dev_ctx, int idx) 297 { 298 struct hct_cmd_queue *cmd_q; 299 unsigned long addr, len; 300 unsigned int retval, qmr; 301 int i, ret; 302 303 if (!pdev || !dev_ctx) 304 return -EINVAL; 305 306 memset(dev_ctx, 0, sizeof(*dev_ctx)); 307 308 ret = pci_enable_device(pdev); 309 if (ret) 310 return -EINVAL; 311 312 addr = pci_resource_start(pdev, PCI_RESOURCE_BAR2); 313 len = pci_resource_len(pdev, PCI_RESOURCE_BAR2); 314 dev_ctx->io_regs = ioremap(addr, len); 315 if (!dev_ctx->io_regs) 316 return -ENOMEM; 317 318 pci_set_master(pdev); 319 retval = pci_alloc_irq_vectors(pdev, 1, MCCP_MSIX_ENTRY_SIZE, PCI_IRQ_MSIX); 320 if (retval != MCCP_NTB_VECTOR_NUM && retval != MCCP_PSP_VECTOR_NUM) 321 return -ENOMEM; 322 323 snprintf(dev_ctx->devname, MCCP_STRING_LEN, "hct-ccp-%d", idx); 324 dev_ctx->irq = pci_irq_vector(pdev, retval - 1); 325 /* To request_irq, the fourth parameter dev_name must be global 326 * variable or static variable. 327 */ 328 ret = request_irq(dev_ctx->irq, hct_cmd_queue_intr_handler, 0, dev_ctx->devname, dev_ctx); 329 if (ret) { 330 pci_free_irq_vectors(pdev); 331 dev_ctx->irq = 0; 332 return ret; 333 } 334 335 tasklet_init(&dev_ctx->irq_tasklet, hct_cmd_queue_intr_task, (unsigned long)dev_ctx); 336 337 qmr = ioread32(dev_ctx->io_regs + Q_MASK_REG); 338 if (qmr == 0) { 339 iowrite32(0x1f, dev_ctx->io_regs + Q_MASK_REG); 340 qmr = ioread32(dev_ctx->io_regs + Q_MASK_REG); 341 } 342 for (i = 0; i < MCCP_DEV_QUEUE_MAX; i++) { 343 if (!(qmr & (1 << i))) 344 continue; 345 346 cmd_q = &dev_ctx->cmd_q[dev_ctx->q_count++]; 347 348 mutex_init(&cmd_q->q_lock); 349 ret = kfifo_alloc(&cmd_q->ectx_fifo, MCCP_INSTANCE_MAX, GFP_KERNEL); 350 if (ret) 351 return -ENOMEM; 352 353 cmd_q->reg_control = dev_ctx->io_regs + MCMD_Q_STATUS_INCR * (i + 1); 354 cmd_q->reg_tail_lo = cmd_q->reg_control + MCMD_Q_TAIL_LO_BASE; 355 cmd_q->reg_head_lo = cmd_q->reg_control + MCMD_Q_HEAD_LO_BASE; 356 cmd_q->reg_int_enable = cmd_q->reg_control + MCMD_Q_INT_ENABLE_BASE; 357 cmd_q->reg_interrupt_status = cmd_q->reg_control + MCMD_Q_INTERRUPT_STATUS_BASE; 358 cmd_q->reg_status = cmd_q->reg_control + MCMD_Q_STATUS_BASE; 359 cmd_q->reg_int_status = cmd_q->reg_control + MCMD_Q_INT_STATUS_BASE; 360 } 361

362 return (dev_ctx->q_count >= 0) ? 0 : -1;

363 } 364