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[PATCH] ACPI: AC: fix some errors and warnings reported by checkpatch.pl
by Xiaofei Tan 25 Mar '21

25 Mar '21

Fix some errors and warnings reported by checkpatch.pl, including following five types: ERROR: "foo * bar" should be "foo *bar" ERROR: code indent should use tabs where possible WARNING: Block comments use a trailing */ on a separate line WARNING: braces {} are not necessary for single statement blocks WARNING: void function return statements are not generally useful Signed-off-by: Xiaofei Tan <tanxiaofei(a)huawei.com> --- drivers/acpi/ac.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c index b86ee6e..07987854 100644 --- a/drivers/acpi/ac.c +++ b/drivers/acpi/ac.c @@ -78,17 +78,16 @@ static struct acpi_driver acpi_ac_driver = { struct acpi_ac { struct power_supply *charger; struct power_supply_desc charger_desc; - struct acpi_device * device; + struct acpi_device *device; unsigned long long state; struct notifier_block battery_nb; }; #define to_acpi_ac(x) power_supply_get_drvdata(x) -/* -------------------------------------------------------------------------- - AC Adapter Management - -------------------------------------------------------------------------- */ - +/* + * AC Adapter Management + */ static int acpi_ac_get_state(struct acpi_ac *ac) { acpi_status status = AE_OK; @@ -109,9 +108,9 @@ static int acpi_ac_get_state(struct acpi_ac *ac) return 0; } -/* -------------------------------------------------------------------------- - sysfs I/F - -------------------------------------------------------------------------- */ +/* + * sysfs I/F + */ static int get_ac_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) @@ -138,10 +137,9 @@ static enum power_supply_property ac_props[] = { POWER_SUPPLY_PROP_ONLINE, }; -/* -------------------------------------------------------------------------- - Driver Model - -------------------------------------------------------------------------- */ - +/* + * Driver Model + */ static void acpi_ac_notify(struct acpi_device *device, u32 event) { struct acpi_ac *ac = acpi_driver_data(device); @@ -174,8 +172,6 @@ static void acpi_ac_notify(struct acpi_device *device, u32 event) acpi_notifier_call_chain(device, event, (u32) ac->state); kobject_uevent(&ac->charger->dev.kobj, KOBJ_CHANGE); } - - return; } static int acpi_ac_battery_notify(struct notifier_block *nb, @@ -282,9 +278,8 @@ static int acpi_ac_add(struct acpi_device *device) ac->battery_nb.notifier_call = acpi_ac_battery_notify; register_acpi_notifier(&ac->battery_nb); end: - if (result) { + if (result) kfree(ac); - } return result; } @@ -293,7 +288,7 @@ static int acpi_ac_add(struct acpi_device *device) static int acpi_ac_resume(struct device *dev) { struct acpi_ac *ac; - unsigned old_state; + unsigned int old_state; if (!dev) return -EINVAL; @@ -352,9 +347,8 @@ static int __init acpi_ac_init(void) } result = acpi_bus_register_driver(&acpi_ac_driver); - if (result < 0) { + if (result < 0) return -ENODEV; - } return 0; } -- 2.8.1

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[PATCH for-next 0/2] RDMA/hns: Support to select congestion control algorithm
by Weihang Li 24 Mar '21

24 Mar '21

The configuration of congestion control algorithm is recorded in the firmware, the driver queries it and then sets it to the hardware. Wei Xu (1): RDMA/hns: Support query information of functions from FW Yangyang Li (1): RDMA/hns: Support congestion control type selection according to the FW drivers/infiniband/hw/hns/hns_roce_device.h | 11 ++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 192 ++++++++++++++++++++++++++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 34 ++++- drivers/infiniband/hw/hns/hns_roce_main.c | 2 + 4 files changed, 236 insertions(+), 3 deletions(-) -- 2.8.1

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Re: [bug report] net: hns3: vf indexing in hclge_add_fd_entry()
by shenjian (K) 24 Mar '21

24 Mar '21

Hello Dan, Thanks for your report! 在 2021/3/24 15:01, Dan Carpenter 写道: > Hello Jian Shen, > > The patch 5f2b1238b33c: "net: hns3: refactor out > hclge_add_fd_entry()" from Mar 22, 2021, leads to the following > static checker warning: > > drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c:6512 hclge_fd_parse_ring_cookie() > warn: array off by one? 'hdev->vport[vf]' > > drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c > 6493 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, > 6494 u16 *vport_id, u8 *action, u16 *queue_id) > 6495 { > 6496 struct hclge_vport *vport = hdev->vport; > 6497 > 6498 if (ring_cookie == RX_CLS_FLOW_DISC) { > 6499 *action = HCLGE_FD_ACTION_DROP_PACKET; > 6500 } else { > 6501 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); > 6502 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); > 6503 u16 tqps; > 6504 > 6505 if (vf > hdev->num_req_vfs) { > ^^^^^^^^^^^^^^^^^^^^^^ > > The is off by one but checking hdev->num_req_vfs in this context doesn't > make sense. Should it instead be check hdev->num_alloc_vport? Also > should we add HCLGE_VF_VPORT_START_NUM? > > vf = ethtool_get_flow_spec_ring_vf(ring_cookie); > vf += HCLGE_VF_VPORT_START_NUM; > if (vf >= hdev->num_alloc_vport) > return -EINVAL; > > 6506 dev_err(&hdev->pdev->dev, > 6507 "Error: vf id (%u) > max vf num (%u)\n", > ^^ > Use >= > > 6508 vf, hdev->num_req_vfs); > 6509 return -EINVAL; > 6510 } > 6511 > 6512 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; > ^^^^^^^^^ > 6513 tqps = hdev->vport[vf].nic.kinfo.num_tqps; > ^^^ > The vport array has hdev->num_vmdq_vport + hdev->num_req_vfs + 1; > elements. ->vport[0] is tqp_main_vport. The next elements are > hdev->num_vmdq_vport and the last part of the array is hdev->num_req_vfs. > > Another possibility is that perhaps this is what was intended? > > idx = vf + 1 + hdev->num_vmdq_vport; > > *vport_id = vf ? vport[idx].vport_id : vport[0].vport_id; > tqps = vport[idx].nic.kinfo.num_tqps; > > There is related code that offers clues but I'm not sure what to do. > > 6514 > 6515 if (ring >= tqps) { > 6516 dev_err(&hdev->pdev->dev, > 6517 "Error: queue id (%u) > max tqp num (%u)\n", > 6518 ring, tqps - 1); > 6519 return -EINVAL; > 6520 } > 6521 > 6522 *action = HCLGE_FD_ACTION_SELECT_QUEUE; > 6523 *queue_id = ring; > 6524 } > 6525 > 6526 return 0; > 6527 } > > [ snip ] > > 9111 static bool hclge_check_vf_mac_exist(struct hclge_vport *vport, int vf_idx, > 9112 u8 *mac_addr) > 9113 { > 9114 struct hclge_mac_vlan_tbl_entry_cmd req; > 9115 struct hclge_dev *hdev = vport->back; > 9116 struct hclge_desc desc; > 9117 u16 egress_port = 0; > 9118 int i; > 9119 > 9120 if (is_zero_ether_addr(mac_addr)) > 9121 return false; > 9122 > 9123 memset(&req, 0, sizeof(req)); > 9124 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, > 9125 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); > 9126 req.egress_port = cpu_to_le16(egress_port); > 9127 hclge_prepare_mac_addr(&req, mac_addr, false); > 9128 > 9129 if (hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false) != -ENOENT) > 9130 return true; > 9131 > 9132 vf_idx += HCLGE_VF_VPORT_START_NUM; > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > We're are skipping the first element. Should it instead be?: > > vf_idx += hdev->num_vmdq_vport + 1; > > 9133 for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) > ^^^^^^^^^^^^^^^^^^^^^^^^ > We're only checking the last part of the array. > > 9134 if (i != vf_idx && > 9135 ether_addr_equal(mac_addr, hdev->vport[i].vf_info.mac)) > 9136 return true; > 9137 > 9138 return false; > 9139 } > > Another thing that's not clear to me is how pci_num_vf() relates to > this. I suspect that it is the same as hdev->num_vmdq_vport, but I > can't be sure. > > regards, > dan carpenter > . The use for num_vmdq_vport is confusing. At the beginning, the HNS3 driver is planed to support VMDQ . Whereafter the hardware supports SR-IOV with better performance. So VMDQ feature is discarded, but the codes of vmdq is remained. For the value of num_vmdq_vport is always 0, so the vport id of VF is actually start from 1. That's why the driver still work. As the num_vmdq_vport is actually useless and confusing, I will send a patch to remove it soon. regards, Jian Shen

1 0

[PATCH RFC] net: sched: implement TCQ_F_CAN_BYPASS for lockless qdisc
by Yunsheng Lin 24 Mar '21

24 Mar '21

Currently pfifo_fast has both TCQ_F_CAN_BYPASS and TCQ_F_NOLOCK flag set, but queue discipline by-pass does not work for lockless qdisc because skb is always enqueued to qdisc even when the qdisc is empty, see __dev_xmit_skb(). This patch calles sch_direct_xmit() to transmit the skb directly to the driver for empty lockless qdisc too, which aviod enqueuing and dequeuing operation. qdisc->empty is set to false whenever a skb is enqueued, and is set to true when skb dequeuing return NULL, see pfifo_fast_dequeue(). Also, qdisc is scheduled at the end of qdisc_run_end() when q->empty is false to avoid packet stuck problem. The performance for ip_forward test increases about 10% with this patch. Signed-off-by: Yunsheng Lin <linyunsheng(a)huawei.com> --- include/net/sch_generic.h | 7 +++++-- net/core/dev.c | 11 +++++++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 2d6eb60..6591356 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -161,7 +161,6 @@ static inline bool qdisc_run_begin(struct Qdisc *qdisc) if (qdisc->flags & TCQ_F_NOLOCK) { if (!spin_trylock(&qdisc->seqlock)) return false; - WRITE_ONCE(qdisc->empty, false); } else if (qdisc_is_running(qdisc)) { return false; } @@ -176,8 +175,12 @@ static inline bool qdisc_run_begin(struct Qdisc *qdisc) static inline void qdisc_run_end(struct Qdisc *qdisc) { write_seqcount_end(&qdisc->running); - if (qdisc->flags & TCQ_F_NOLOCK) + if (qdisc->flags & TCQ_F_NOLOCK) { spin_unlock(&qdisc->seqlock); + + if (unlikely(!READ_ONCE(qdisc->empty))) + __netif_schedule(qdisc); + } } static inline bool qdisc_may_bulk(const struct Qdisc *qdisc) diff --git a/net/core/dev.c b/net/core/dev.c index 2bfdd52..fa8504d 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -3791,7 +3791,18 @@ static inline int __dev_xmit_skb(struct sk_buff *skb, struct Qdisc *q, qdisc_calculate_pkt_len(skb, q); if (q->flags & TCQ_F_NOLOCK) { + if (q->flags & TCQ_F_CAN_BYPASS && READ_ONCE(q->empty) && qdisc_run_begin(q)) { + qdisc_bstats_cpu_update(q, skb); + + if (sch_direct_xmit(skb, q, dev, txq, NULL, true) && !READ_ONCE(q->empty)) + __qdisc_run(q); + + qdisc_run_end(q); + return NET_XMIT_SUCCESS; + } + rc = q->enqueue(skb, q, &to_free) & NET_XMIT_MASK; + WRITE_ONCE(q->empty, false); qdisc_run(q); if (unlikely(to_free)) -- 2.7.4

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[PATCH] dma-mapping: make map_benchmark compile into module
by Tian Tao 24 Mar '21

24 Mar '21

under some scenarios, it is necessary to compile map_benchmark into module to test iommu, so this patch changed Kconfig and export_symbol to implement map_benchmark compiled into module. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- kernel/dma/Kconfig | 2 +- kernel/kthread.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 77b4055..0468293 100644 --- a/kernel/dma/Kconfig +++ b/kernel/dma/Kconfig @@ -223,7 +223,7 @@ config DMA_API_DEBUG_SG If unsure, say N. config DMA_MAP_BENCHMARK - bool "Enable benchmarking of streaming DMA mapping" + tristate "Enable benchmarking of streaming DMA mapping" depends on DEBUG_FS help Provides /sys/kernel/debug/dma_map_benchmark that helps with testing diff --git a/kernel/kthread.c b/kernel/kthread.c index 1578973..fa4736f 100644 --- a/kernel/kthread.c +++ b/kernel/kthread.c @@ -455,6 +455,7 @@ void kthread_bind_mask(struct task_struct *p, const struct cpumask *mask) { __kthread_bind_mask(p, mask, TASK_UNINTERRUPTIBLE); } +EXPORT_SYMBOL(kthread_bind_mask); /** * kthread_bind - bind a just-created kthread to a cpu. -- 2.7.4

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[PATCH net] net: sched: fix packet stuck problem for lockless qdisc
by Yunsheng Lin 23 Mar '21

23 Mar '21

Lockless qdisc has below concurrent problem: cpu0 cpu1 . . q->enqueue . . . qdisc_run_begin() . . . dequeue_skb() . . . sch_direct_xmit() . . . . q->enqueue . qdisc_run_begin() . return and do nothing . . qdisc_run_end() . cpu1 enqueue a skb without calling __qdisc_run() because cpu0 has not released the lock yet and spin_trylock() return false for cpu1 in qdisc_run_begin(), and cpu0 do not see the skb enqueued by cpu1 when calling dequeue_skb() because cpu1 may enqueue the skb after cpu0 calling dequeue_skb() and before cpu0 calling qdisc_run_end(). Lockless qdisc has another concurrent problem when tx_action is involved: cpu0(serving tx_action) cpu1 cpu2 . . . . q->enqueue . . qdisc_run_begin() . . dequeue_skb() . . . q->enqueue . . . . sch_direct_xmit() . . . qdisc_run_begin() . . return and do nothing . . . clear __QDISC_STATE_SCHED . . qdisc_run_begin() . . return and do nothing . . . . . . qdisc_run_begin() . This patch fixes the above data race by: 1. Set a flag after spin_trylock() return false. 2. Retry a spin_trylock() in case other CPU may not see the new flag after it releases the lock. 3. reschedule if the flag is set after the lock is released at the end of qdisc_run_end(). For tx_action case, the flags is also set when cpu1 is at the end if qdisc_run_begin(), so tx_action will be rescheduled again to dequeue the skb enqueued by cpu2. Also clear the flag before dequeuing in order to reduce the overhead of the above process, and aviod doing the heavy test_and_clear_bit() at the end of qdisc_run_end(). Fixes: 6b3ba9146fe6 ("net: sched: allow qdiscs to handle locking") Signed-off-by: Yunsheng Lin <linyunsheng(a)huawei.com> --- For those who has not been following the qdsic scheduling discussion, there is packet stuck problem for lockless qdisc, see [1], and I has done some cleanup and added some enhanced features too, see [2] [3]. While I was doing the optimization for lockless qdisc, it accurred to me that these optimization is useless if there is still basic bug in lockless qdisc, even the bug is not easily reproducible. So look through [1] again, I found that the data race for tx action mentioned by Michael, and thought deep about it and came up with this patch trying to fix it. So I am really appreciated some who still has the reproducer can try this patch and report back. 1. https://lore.kernel.org/netdev/d102074f-7489-e35a-98cf-e2cad7efd8a2@netroun… 2. https://patchwork.kernel.org/project/netdevbpf/patch/1615777818-13969-1-git… 3. https://patchwork.kernel.org/project/netdevbpf/patch/1615800610-34700-1-git… --- include/net/sch_generic.h | 23 ++++++++++++++++++++--- net/sched/sch_generic.c | 1 + 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index f7a6e14..4220eab 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -36,6 +36,7 @@ struct qdisc_rate_table { enum qdisc_state_t { __QDISC_STATE_SCHED, __QDISC_STATE_DEACTIVATED, + __QDISC_STATE_NEED_RESCHEDULE, }; struct qdisc_size_table { @@ -159,8 +160,17 @@ static inline bool qdisc_is_empty(const struct Qdisc *qdisc) static inline bool qdisc_run_begin(struct Qdisc *qdisc) { if (qdisc->flags & TCQ_F_NOLOCK) { - if (!spin_trylock(&qdisc->seqlock)) - return false; + if (!spin_trylock(&qdisc->seqlock)) { + set_bit(__QDISC_STATE_NEED_RESCHEDULE, + &qdisc->state); + + /* Retry again in case other CPU may not see the + * new flags after it releases the lock at the + * end of qdisc_run_end(). + */ + if (!spin_trylock(&qdisc->seqlock)) + return false; + } WRITE_ONCE(qdisc->empty, false); } else if (qdisc_is_running(qdisc)) { return false; @@ -176,8 +186,15 @@ static inline bool qdisc_run_begin(struct Qdisc *qdisc) static inline void qdisc_run_end(struct Qdisc *qdisc) { write_seqcount_end(&qdisc->running); - if (qdisc->flags & TCQ_F_NOLOCK) + if (qdisc->flags & TCQ_F_NOLOCK) { spin_unlock(&qdisc->seqlock); + + if (unlikely(test_bit(__QDISC_STATE_NEED_RESCHEDULE, + &qdisc->state) && + !test_bit(__QDISC_STATE_DEACTIVATED, + &qdisc->state))) + __netif_schedule(qdisc); + } } static inline bool qdisc_may_bulk(const struct Qdisc *qdisc) diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c index 44991ea..25d75d8 100644 --- a/net/sched/sch_generic.c +++ b/net/sched/sch_generic.c @@ -205,6 +205,7 @@ static struct sk_buff *dequeue_skb(struct Qdisc *q, bool *validate, const struct netdev_queue *txq = q->dev_queue; struct sk_buff *skb = NULL; + clear_bit(__QDISC_STATE_NEED_RESCHEDULE, &q->state); *packets = 1; if (unlikely(!skb_queue_empty(&q->gso_skb))) { spinlock_t *lock = NULL; -- 2.7.4

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[PATCH net-next 0/8] net: hns: add some cleanups
by Huazhong Tan 23 Mar '21

23 Mar '21

This series includes some cleanups for the HNS ethernet driver. Huazhong Tan (6): net: hns: remove unused get_autoneg() net: hns: remove unused set_autoneg() net: hns: remove unused set_rx_ignore_pause_frames() net: hns: remove unused config_half_duplex() net: hns: remove unused NIC_LB_TEST_RX_PKG_ERR net: hns: remove unused HNS_LED_PC_REG Yonglong Liu (2): net: hns: remove unnecessary !! operation in hns_mac_config_sds_loopback_acpi() net: hns: remove redundant variable initialization drivers/net/ethernet/hisilicon/hns/hnae.h | 6 ------ drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c | 22 +--------------------- drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c | 18 ------------------ drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c | 2 +- drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h | 4 ---- drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 16 ++++++++-------- drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 2 +- drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c | 4 ++-- .../net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c | 18 +----------------- drivers/net/ethernet/hisilicon/hns/hns_enet.c | 4 ++-- drivers/net/ethernet/hisilicon/hns/hns_ethtool.c | 3 +-- drivers/net/ethernet/hisilicon/hns_mdio.c | 4 ++-- 12 files changed, 19 insertions(+), 84 deletions(-) -- 2.7.4

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[PATCH] coresight: core: Fix typo in coresight-core.c
by Qi Liu 23 Mar '21

23 Mar '21

Fix up one typo: compoment->component. Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built as a module") Signed-off-by: Qi Liu <liuqi115(a)huawei.com> --- drivers/hwtracing/coresight/coresight-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 0062c89..bc397a7 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -86,7 +86,7 @@ static int coresight_id_match(struct device *dev, void *data) i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE) return 0; - /* Get the source ID for both compoment */ + /* Get the source ID for both component */ trace_id = source_ops(csdev)->trace_id(csdev); i_trace_id = source_ops(i_csdev)->trace_id(i_csdev); -- 2.8.1

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Re: [PATCH v14 07/13] iommu/smmuv3: Implement cache_invalidate
by chenxiang (M) 23 Mar '21

23 Mar '21

Hi Eric, 在 2021/2/24 4:56, Eric Auger 写道: > Implement domain-selective, pasid selective and page-selective > IOTLB invalidations. > > Signed-off-by: Eric Auger <eric.auger(a)redhat.com> > > --- > > v13 -> v14: > - Add domain invalidation > - do global inval when asid is not provided with addr > granularity > > v7 -> v8: > - ASID based invalidation using iommu_inv_pasid_info > - check ARCHID/PASID flags in addr based invalidation > - use __arm_smmu_tlb_inv_context and __arm_smmu_tlb_inv_range_nosync > > v6 -> v7 > - check the uapi version > > v3 -> v4: > - adapt to changes in the uapi > - add support for leaf parameter > - do not use arm_smmu_tlb_inv_range_nosync or arm_smmu_tlb_inv_context > anymore > > v2 -> v3: > - replace __arm_smmu_tlb_sync by arm_smmu_cmdq_issue_sync > > v1 -> v2: > - properly pass the asid > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 4c19a1114de4..df3adc49111c 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2949,6 +2949,79 @@ static void arm_smmu_detach_pasid_table(struct iommu_domain *domain) > mutex_unlock(&smmu_domain->init_mutex); > } > > +static int > +arm_smmu_cache_invalidate(struct iommu_domain *domain, struct device *dev, > + struct iommu_cache_invalidate_info *inv_info) > +{ > + struct arm_smmu_cmdq_ent cmd = {.opcode = CMDQ_OP_TLBI_NSNH_ALL}; > + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + if (smmu_domain->stage != ARM_SMMU_DOMAIN_NESTED) > + return -EINVAL; > + > + if (!smmu) > + return -EINVAL; > + > + if (inv_info->version != IOMMU_CACHE_INVALIDATE_INFO_VERSION_1) > + return -EINVAL; > + > + if (inv_info->cache & IOMMU_CACHE_INV_TYPE_PASID || > + inv_info->cache & IOMMU_CACHE_INV_TYPE_DEV_IOTLB) { > + return -ENOENT; > + } > + > + if (!(inv_info->cache & IOMMU_CACHE_INV_TYPE_IOTLB)) > + return -EINVAL; > + > + /* IOTLB invalidation */ > + > + switch (inv_info->granularity) { > + case IOMMU_INV_GRANU_PASID: > + { > + struct iommu_inv_pasid_info *info = > + &inv_info->granu.pasid_info; > + > + if (info->flags & IOMMU_INV_ADDR_FLAGS_PASID) > + return -ENOENT; > + if (!(info->flags & IOMMU_INV_PASID_FLAGS_ARCHID)) > + return -EINVAL; > + > + __arm_smmu_tlb_inv_context(smmu_domain, info->archid); > + return 0; > + } > + case IOMMU_INV_GRANU_ADDR: > + { > + struct iommu_inv_addr_info *info = &inv_info->granu.addr_info; > + size_t size = info->nb_granules * info->granule_size; > + bool leaf = info->flags & IOMMU_INV_ADDR_FLAGS_LEAF; > + > + if (info->flags & IOMMU_INV_ADDR_FLAGS_PASID) > + return -ENOENT; > + > + if (!(info->flags & IOMMU_INV_ADDR_FLAGS_ARCHID)) > + break; > + > + arm_smmu_tlb_inv_range_domain(info->addr, size, > + info->granule_size, leaf, > + info->archid, smmu_domain); Is it possible to add a check before the function to make sure that info->granule_size can be recognized by SMMU? There is a scenario which will cause TLBI issue: RIL feature is enabled on guest but is disabled on host, and then on host it just invalidate 4K/2M/1G once a time, but from QEMU, info->nb_granules is always 1 and info->granule_size = size, if size is not equal to 4K or 2M or 1G (for example size = granule_size is 5M), it will only part of the size it wants to invalidate. I think maybe we can add a check here: if RIL is not enabled and also size is not the granule_size (4K/2M/1G) supported by SMMU hardware, can we just simply use the smallest granule_size supported by hardware all the time? > + > + arm_smmu_cmdq_issue_sync(smmu); > + return 0; > + } > + case IOMMU_INV_GRANU_DOMAIN: > + break; I check the qemu code (https://github.com/eauger/qemu/tree/v5.2.0-2stage-rfcv8), for opcode CMD_TLBI_NH_ALL or CMD_TLBI_NSNH_ALL from guest OS it calls smmu_inv_notifiers_all() to unamp all notifiers of all mr's, but it seems not set event.entry.granularity which i think it should set IOMMU_INV_GRAN_ADDR. BTW, for opcode CMD_TLBI_NH_ALL or CMD_TLBI_NSNH_ALL, it needs to unmap size = 0x1000000000000 on 48bit system (it may spend much time), maybe it is better to set it as IOMMU_INV_GRANU_DOMAIN, then in host OS, send TLBI_NH_ALL directly when IOMMU_INV_GRANU_DOMAIN. > + default: > + return -EINVAL; > + } > + > + /* Global S1 invalidation */ > + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; > + arm_smmu_cmdq_issue_cmd(smmu, &cmd); > + arm_smmu_cmdq_issue_sync(smmu); > + return 0; > +} > + > static bool arm_smmu_dev_has_feature(struct device *dev, > enum iommu_dev_features feat) > { > @@ -3048,6 +3121,7 @@ static struct iommu_ops arm_smmu_ops = { > .put_resv_regions = generic_iommu_put_resv_regions, > .attach_pasid_table = arm_smmu_attach_pasid_table, > .detach_pasid_table = arm_smmu_detach_pasid_table, > + .cache_invalidate = arm_smmu_cache_invalidate, > .dev_has_feat = arm_smmu_dev_has_feature, > .dev_feat_enabled = arm_smmu_dev_feature_enabled, > .dev_enable_feat = arm_smmu_dev_enable_feature,

2 4

[PATCH V2 net-next 0/7] net: hns3: refactor and new features for flow director
by Huazhong Tan 23 Mar '21

23 Mar '21

This patchset refactor some functions and add some new features for flow director. patch 1~3: refactor large functions patch 4, 7: add traffic class and user-def field support for ethtool patch 5: refactor flow director configuration patch 6: clean up for hns3_del_all_fd_entries() change log: V1->V2: modifies patch 5 as Jakub suggested, keep configuring ethtool/tc flower rules synchronously while aRFS asynchronously. changes the usecnt of user-def rule checking in patch 7. removes previous patches 8 and 9 from this series, since there are issues that need further discussion. previous version: V1: https://patchwork.kernel.org/project/netdevbpf/cover/1615811031-55209-1-git… Jian Shen (7): net: hns3: refactor out hclge_add_fd_entry() net: hns3: refactor out hclge_fd_get_tuple() net: hns3: refactor for function hclge_fd_convert_tuple net: hns3: add support for traffic class tuple support for flow director by ethtool net: hns3: refactor flow director configuration net: hns3: refine for hns3_del_all_fd_entries() net: hns3: add support for user-def data of flow director drivers/net/ethernet/hisilicon/hns3/hnae3.h | 2 - drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 10 - .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 14 + .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 1316 +++++++++++++------- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 58 + 5 files changed, 936 insertions(+), 464 deletions(-) -- 2.7.4

2 8

[PATCH] sched/fair: remove redundant test_idle_cores for non-smt
by Barry Song 22 Mar '21

22 Mar '21

update_idle_core() is only done for the case of sched_smt_present. but test_idle_cores() is done for all machines even those without smt. this could contribute to up 8%+ hackbench performance loss on a machine like kunpeng 920 which has no smt. this patch removes the redundant test_idle_cores() for non-smt machines. we run the below hackbench with different -g parameter from 2 to 14, for each different g, we run the command 10 times and get the average time: $ numactl -N 0 hackbench -p -T -l 20000 -g $1 hackbench will report the time which is needed to complete a certain number of messages transmissions between a certain number of tasks, for example: $ numactl -N 0 hackbench -p -T -l 20000 -g 10 Running in threaded mode with 10 groups using 40 file descriptors each (== 400 tasks) Each sender will pass 20000 messages of 100 bytes The below is the result of hackbench w/ and w/o this patch: g= 2 4 6 8 10 12 14 w/o: 1.8151 3.8499 5.5142 7.2491 9.0340 10.7345 12.0929 w/ : 1.8428 3.7436 5.4501 6.9522 8.2882 9.9535 11.3367 +4.1% +8.3% +7.3% +6.3% Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/sched/fair.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 2e2ab1e..de42a32 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -6038,9 +6038,11 @@ static inline bool test_idle_cores(int cpu, bool def) { struct sched_domain_shared *sds; - sds = rcu_dereference(per_cpu(sd_llc_shared, cpu)); - if (sds) - return READ_ONCE(sds->has_idle_cores); + if (static_branch_likely(&sched_smt_present)) { + sds = rcu_dereference(per_cpu(sd_llc_shared, cpu)); + if (sds) + return READ_ONCE(sds->has_idle_cores); + } return def; } -- 1.8.3.1

6 5

[PATCH v2 for-rc] RDMA/hns: Fix bug during CMDQ initialization
by Weihang Li 22 Mar '21

22 Mar '21

From: Lang Cheng <chenglang(a)huawei.com> When reloading driver, the head/tail pointer of CMDQ may be not at position 0. Then during initialization of CMDQ, if head is reset first, the firmware will start to handle CMDQ because the head is not equal to the tail. The driver can reset tail first since the firmware will be triggerred only by head. This bug is introduced by changing macros of head/tail register without changing the order of initialization. Fixes: 292b3352bd5b ("RDMA/hns: Adjust fields and variables about CMDQ tail/head") Signed-off-by: Lang Cheng <chenglang(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- Changes since v1: - Only retain the bugfix part for -rc branch. - Link: https://patchwork.kernel.org/project/linux-rdma/patch/1615541933-35798-1-gi… drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index c3934ab..ce26f97 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1194,8 +1194,10 @@ static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) upper_32_bits(dma)); roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, (u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); - roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); + + /* Make sure to write tail first and then head */ roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); + roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); } else { roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, -- 2.8.1

2 1

[PATCH] spi: imx: Use of_device_get_match_data() helper
by Tian Tao 22 Mar '21

22 Mar '21

Use the of_device_get_match_data() helper instead of open coding. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/spi/spi-imx.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index cf55192..4fe767a 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1548,13 +1548,12 @@ static int spi_imx_slave_abort(struct spi_master *master) static int spi_imx_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - const struct of_device_id *of_id = - of_match_device(spi_imx_dt_ids, &pdev->dev); struct spi_master *master; struct spi_imx_data *spi_imx; struct resource *res; int ret, irq, spi_drctl; - const struct spi_imx_devtype_data *devtype_data = of_id->data; + const struct spi_imx_devtype_data *devtype_data = + of_device_get_match_data(&pdev->dev); bool slave_mode; u32 val; -- 2.7.4

1 0

[PATCH] i2c: imx: Use devm_request_irq()
by Tian Tao 19 Mar '21

19 Mar '21

Use devm_request_irq() to get rid of manual unregistration. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/i2c/busses/i2c-imx.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index b80fdc1..e377d4a 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -1435,8 +1435,8 @@ static int i2c_imx_probe(struct platform_device *pdev) goto rpm_disable; /* Request IRQ */ - ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, - pdev->name, i2c_imx); + ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, + IRQF_SHARED, pdev->name, i2c_imx); if (ret) { dev_err(&pdev->dev, "can't claim irq %d\n", irq); goto rpm_disable; @@ -1481,7 +1481,6 @@ static int i2c_imx_probe(struct platform_device *pdev) clk_notifier_unregister: clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); - free_irq(irq, i2c_imx); rpm_disable: pm_runtime_put_noidle(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -1494,7 +1493,7 @@ static int i2c_imx_probe(struct platform_device *pdev) static int i2c_imx_remove(struct platform_device *pdev) { struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); - int irq, ret; + int ret; ret = pm_runtime_get_sync(&pdev->dev); if (ret < 0) @@ -1514,9 +1513,6 @@ static int i2c_imx_remove(struct platform_device *pdev) imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); - irq = platform_get_irq(pdev, 0); - if (irq >= 0) - free_irq(irq, i2c_imx); clk_disable_unprepare(i2c_imx->clk); pm_runtime_put_noidle(&pdev->dev); -- 2.7.4

2 1

[PATCH] i2c: mlxbf: Remove the unneeded devm_free_irq
by Tian Tao 19 Mar '21

19 Mar '21

Use devm_request_irq to request interrupts,devm_free_irq is not needed to release interrupts. so just remove it. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/i2c/busses/i2c-mlxbf.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c index 2fb0532..ea839de 100644 --- a/drivers/i2c/busses/i2c-mlxbf.c +++ b/drivers/i2c/busses/i2c-mlxbf.c @@ -2426,8 +2426,6 @@ static int mlxbf_i2c_remove(struct platform_device *pdev) } mutex_unlock(&mlxbf_i2c_bus_lock); - devm_free_irq(dev, priv->irq, priv); - i2c_del_adapter(&priv->adap); return 0; -- 2.7.4

2 1

[PATCH 0/3] drivers/perf: convert sysfs sprintf/snprintf/scnprintf to sysfs_emit
by Qi Liu 18 Mar '21

18 Mar '21

Use the generic sysfs_emit() and sysfs_emit_at() function to take place of sprintf/snprintf/scnprintf, to avoid buffer overrun. Zihao Tang (1) drivers/perf: convert sysfs snprintf family to sysfs_emit Qi Liu (2): drivers/perf: convert sysfs scnprintf family to sysfs_emit_at drivers/perf: convert sysfs sprintf family to sysfs_emit drivers/perf/arm-cci.c | 12 ++++++------ drivers/perf/arm-ccn.c | 28 ++++++++++++---------------- drivers/perf/arm-cmn.c | 22 +++++++++++----------- drivers/perf/arm_dmc620_pmu.c | 2 +- drivers/perf/arm_dsu_pmu.c | 5 ++--- drivers/perf/arm_smmuv3_pmu.c | 4 ++-- drivers/perf/arm_spe_pmu.c | 3 +-- drivers/perf/fsl_imx8_ddr_perf.c | 7 +++---- drivers/perf/hisilicon/hisi_uncore_pmu.c | 8 ++++---- drivers/perf/qcom_l2_pmu.c | 2 +- drivers/perf/qcom_l3_pmu.c | 4 ++-- drivers/perf/thunderx2_pmu.c | 4 ++-- drivers/perf/xgene_pmu.c | 4 ++-- 13 files changed, 49 insertions(+), 56 deletions(-) -- 2.8.1

4 9

[PATCH v2 0/3] Add support for HiSilicon I2C controller
by Yicong Yang 18 Mar '21

18 Mar '21

Add driver and MAINTAINERS for HiSilicon I2C controller on Kunpeng SoC. Also provide the devm_*() variants for adding the I2C adapters. Change since v1: - fix compile test error on 32bit arch, reported by intel lkp robot: 64 bit division without using kernel wrapper in probe function. Link:https://lore.kernel.org/linux-i2c/1615016946-55670-1-git-send-email-ya… Yicong Yang (3): i2c: core: add managed function for adding i2c adapters i2c: add support for HiSilicon I2C controller MAINTAINERS: Add maintainer for HiSilicon I2C driver MAINTAINERS | 7 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-hisi.c | 525 ++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/i2c-core-base.c | 39 ++++ include/linux/i2c.h | 1 + 6 files changed, 583 insertions(+) create mode 100644 drivers/i2c/busses/i2c-hisi.c -- 2.8.1

2 6

[PATCH v3] iommu: Check dev->iommu in iommu_dev_xxx functions
by Shameer Kolothum 18 Mar '21

18 Mar '21

The device iommu probe/attach might have failed leaving dev->iommu to NULL and device drivers may still invoke these functions resulting in a crash in iommu vendor driver code. Hence make sure we check that. Fixes: a3a195929d40 ("iommu: Add APIs for multiple domains per device") Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi(a)huawei.com> --- v2 --> v3 -Removed iommu_ops from struct dev_iommu. v1 --> v2: -Added iommu_ops to struct dev_iommu based on the discussion with Robin. -Rebased against iommu-tree core branch. --- drivers/iommu/iommu.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index d0b0a15dba84..e10cfa99057c 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2878,10 +2878,12 @@ EXPORT_SYMBOL_GPL(iommu_fwspec_add_ids); */ int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat) { - const struct iommu_ops *ops = dev->bus->iommu_ops; + if (dev->iommu && dev->iommu->iommu_dev) { + const struct iommu_ops *ops = dev->iommu->iommu_dev->ops; - if (ops && ops->dev_enable_feat) - return ops->dev_enable_feat(dev, feat); + if (ops->dev_enable_feat) + return ops->dev_enable_feat(dev, feat); + } return -ENODEV; } @@ -2894,10 +2896,12 @@ EXPORT_SYMBOL_GPL(iommu_dev_enable_feature); */ int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat) { - const struct iommu_ops *ops = dev->bus->iommu_ops; + if (dev->iommu && dev->iommu->iommu_dev) { + const struct iommu_ops *ops = dev->iommu->iommu_dev->ops; - if (ops && ops->dev_disable_feat) - return ops->dev_disable_feat(dev, feat); + if (ops->dev_disable_feat) + return ops->dev_disable_feat(dev, feat); + } return -EBUSY; } @@ -2905,10 +2909,12 @@ EXPORT_SYMBOL_GPL(iommu_dev_disable_feature); bool iommu_dev_feature_enabled(struct device *dev, enum iommu_dev_features feat) { - const struct iommu_ops *ops = dev->bus->iommu_ops; + if (dev->iommu && dev->iommu->iommu_dev) { + const struct iommu_ops *ops = dev->iommu->iommu_dev->ops; - if (ops && ops->dev_feat_enabled) - return ops->dev_feat_enabled(dev, feat); + if (ops->dev_feat_enabled) + return ops->dev_feat_enabled(dev, feat); + } return false; } -- 2.17.1

3 2

[PATCH v2 0/2] EDAC/ghes: Add EDAC device for reporting the CPU cache error count
by Shiju Jose 17 Mar '21

17 Mar '21

CPU cache corrected errors are detected occasionally on few of our ARM64 hardware boards. Though it is rare, the probability of the CPU cache errors frequently occurring can't be avoided. The earlier failure detection by monitoring the cache corrected errors for the frequent occurrences and taking preventive action could prevent more serious hardware faults. On Intel architectures, cache corrected errors are reported and the affected cores are offlined in the architecture specific method. http://www.mcelog.org/cache.html However for the firmware-first error reporting, specifically on ARM64 architecture, there is no provision present for reporting the cache corrected error count to the user-space and taking preventive action such as offline the affected cores. For this purpose, it was suggested to create the CPU EDAC device for the CPU caches for reporting the cache error count for the firmware-first error reporting. User-space application could monitor the recorded corrected error count for the earlier hardware failure detection and could take preventive action, such as offline the corresponding CPU core/s. Changes: RFC V1 -> RFC V2: 1. Fixed feedback by Boris. 1.1. Added reason of this patch. 1.2. Changed CPU errors to CPU cache errors in the drivers/edac/Kconfig 1.3 Changed EDAC cache list to percpu variables. 1.4 Changed configuration depends on ARM64. 1.5. Moved discovery of cacheinfo to ghes_scan_system(). 2. Changes in the descriptions. Shiju Jose (2): EDAC/ghes: Add EDAC device for reporting the CPU cache errors ACPI / APEI: Add reporting ARM64 CPU cache corrected error count Documentation/ABI/testing/sysfs-devices-edac | 15 ++ drivers/acpi/apei/ghes.c | 76 +++++++- drivers/edac/Kconfig | 12 ++ drivers/edac/ghes_edac.c | 186 +++++++++++++++++++ include/acpi/ghes.h | 27 +++ include/linux/cper.h | 4 + 6 files changed, 316 insertions(+), 4 deletions(-) -- 2.17.1

3 5

[PATCH net-next] net: sched: remove unnecessay lock protection for skb_bad_txq/gso_skb
by Yunsheng Lin 17 Mar '21

17 Mar '21

Currently qdisc_lock(q) is taken before enqueuing and dequeuing for lockless qdisc's skb_bad_txq/gso_skb queue, qdisc->seqlock is also taken, which can provide the same protection as qdisc_lock(q). This patch removes the unnecessay qdisc_lock(q) protection for lockless qdisc' skb_bad_txq/gso_skb queue. And dev_reset_queue() takes the qdisc->seqlock for lockless qdisc besides taking the qdisc_lock(q) when doing the qdisc reset, some_qdisc_is_busy() takes both qdisc->seqlock and qdisc_lock(q) when checking qdisc status. It is unnecessary to take both lock while the fast path only take one lock, so this patch also changes it to only take qdisc_lock(q) for locked qdisc, and only take qdisc->seqlock for lockless qdisc. Since qdisc->seqlock is taken for lockless qdisc when calling qdisc_is_running() in some_qdisc_is_busy(), use qdisc->running to decide if the lockless qdisc is running. Signed-off-by: Yunsheng Lin <linyunsheng(a)huawei.com> --- include/net/sch_generic.h | 2 -- net/sched/sch_generic.c | 72 +++++++++++++---------------------------------- 2 files changed, 19 insertions(+), 55 deletions(-) diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 2d6eb60..0e497ed 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -139,8 +139,6 @@ static inline struct Qdisc *qdisc_refcount_inc_nz(struct Qdisc *qdisc) static inline bool qdisc_is_running(struct Qdisc *qdisc) { - if (qdisc->flags & TCQ_F_NOLOCK) - return spin_is_locked(&qdisc->seqlock); return (raw_read_seqcount(&qdisc->running) & 1) ? true : false; } diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c index 49eae93..a5f1e3c 100644 --- a/net/sched/sch_generic.c +++ b/net/sched/sch_generic.c @@ -38,7 +38,7 @@ EXPORT_SYMBOL(default_qdisc_ops); /* Main transmission queue. */ /* Modifications to data participating in scheduling must be protected with - * qdisc_lock(qdisc) spinlock. + * qdisc_lock(qdisc) or qdisc->seqlock spinlock. * * The idea is the following: * - enqueue, dequeue are serialized via qdisc root lock @@ -51,14 +51,8 @@ EXPORT_SYMBOL(default_qdisc_ops); static inline struct sk_buff *__skb_dequeue_bad_txq(struct Qdisc *q) { const struct netdev_queue *txq = q->dev_queue; - spinlock_t *lock = NULL; struct sk_buff *skb; - if (q->flags & TCQ_F_NOLOCK) { - lock = qdisc_lock(q); - spin_lock(lock); - } - skb = skb_peek(&q->skb_bad_txq); if (skb) { /* check the reason of requeuing without tx lock first */ @@ -77,9 +71,6 @@ static inline struct sk_buff *__skb_dequeue_bad_txq(struct Qdisc *q) } } - if (lock) - spin_unlock(lock); - return skb; } @@ -96,13 +87,6 @@ static inline struct sk_buff *qdisc_dequeue_skb_bad_txq(struct Qdisc *q) static inline void qdisc_enqueue_skb_bad_txq(struct Qdisc *q, struct sk_buff *skb) { - spinlock_t *lock = NULL; - - if (q->flags & TCQ_F_NOLOCK) { - lock = qdisc_lock(q); - spin_lock(lock); - } - __skb_queue_tail(&q->skb_bad_txq, skb); if (qdisc_is_percpu_stats(q)) { @@ -112,20 +96,10 @@ static inline void qdisc_enqueue_skb_bad_txq(struct Qdisc *q, qdisc_qstats_backlog_inc(q, skb); q->q.qlen++; } - - if (lock) - spin_unlock(lock); } static inline void dev_requeue_skb(struct sk_buff *skb, struct Qdisc *q) { - spinlock_t *lock = NULL; - - if (q->flags & TCQ_F_NOLOCK) { - lock = qdisc_lock(q); - spin_lock(lock); - } - while (skb) { struct sk_buff *next = skb->next; @@ -144,8 +118,7 @@ static inline void dev_requeue_skb(struct sk_buff *skb, struct Qdisc *q) skb = next; } - if (lock) - spin_unlock(lock); + __netif_schedule(q); } @@ -207,24 +180,9 @@ static struct sk_buff *dequeue_skb(struct Qdisc *q, bool *validate, *packets = 1; if (unlikely(!skb_queue_empty(&q->gso_skb))) { - spinlock_t *lock = NULL; - - if (q->flags & TCQ_F_NOLOCK) { - lock = qdisc_lock(q); - spin_lock(lock); - } skb = skb_peek(&q->gso_skb); - /* skb may be null if another cpu pulls gso_skb off in between - * empty check and lock. - */ - if (!skb) { - if (lock) - spin_unlock(lock); - goto validate; - } - /* skb in gso_skb were already validated */ *validate = false; if (xfrm_offload(skb)) @@ -243,11 +201,10 @@ static struct sk_buff *dequeue_skb(struct Qdisc *q, bool *validate, } else { skb = NULL; } - if (lock) - spin_unlock(lock); + goto trace; } -validate: + *validate = true; if ((q->flags & TCQ_F_ONETXQUEUE) && @@ -1153,13 +1110,15 @@ static void dev_reset_queue(struct net_device *dev, if (nolock) spin_lock_bh(&qdisc->seqlock); - spin_lock_bh(qdisc_lock(qdisc)); + else + spin_lock_bh(qdisc_lock(qdisc)); qdisc_reset(qdisc); - spin_unlock_bh(qdisc_lock(qdisc)); if (nolock) spin_unlock_bh(&qdisc->seqlock); + else + spin_unlock_bh(qdisc_lock(qdisc)); } static bool some_qdisc_is_busy(struct net_device *dev) @@ -1168,20 +1127,27 @@ static bool some_qdisc_is_busy(struct net_device *dev) for (i = 0; i < dev->num_tx_queues; i++) { struct netdev_queue *dev_queue; - spinlock_t *root_lock; struct Qdisc *q; + bool nolock; int val; dev_queue = netdev_get_tx_queue(dev, i); q = dev_queue->qdisc_sleeping; - root_lock = qdisc_lock(q); - spin_lock_bh(root_lock); + nolock = q->flags & TCQ_F_NOLOCK; + + if (nolock) + spin_lock_bh(&q->seqlock); + else + spin_lock_bh(qdisc_lock(q)); val = (qdisc_is_running(q) || test_bit(__QDISC_STATE_SCHED, &q->state)); - spin_unlock_bh(root_lock); + if (nolock) + spin_unlock_bh(&q->seqlock); + else + spin_unlock_bh(qdisc_lock(q)); if (val) return true; -- 2.7.4

4 8

[RFC PATCH v4 0/3] scheduler: expose the topology of clusters and add cluster scheduler
by Barry Song 16 Mar '21

16 Mar '21

ARM64 server chip Kunpeng 920 has 6 or 8 clusters in each NUMA node, and each cluster has 4 cpus. All clusters share L3 cache data while each cluster has local L3 tag. On the other hand, each cluster will share some internal system bus. This means cache is much more affine inside one cluster than across clusters. +-----------------------------------+ +---------+ | +------+ +------+ +---------------------------+ | | | CPU0 | | cpu1 | | +-----------+ | | | +------+ +------+ | | | | | | +----+ L3 | | | | +------+ +------+ cluster | | tag | | | | | CPU2 | | CPU3 | | | | | | | +------+ +------+ | +-----------+ | | | | | | +-----------------------------------+ | | +-----------------------------------+ | | | +------+ +------+ +--------------------------+ | | | | | | | +-----------+ | | | +------+ +------+ | | | | | | | | L3 | | | | +------+ +------+ +----+ tag | | | | | | | | | | | | | | +------+ +------+ | +-----------+ | | | | | | +-----------------------------------+ | L3 | | data | +-----------------------------------+ | | | +------+ +------+ | +-----------+ | | | | | | | | | | | | | +------+ +------+ +----+ L3 | | | | | | tag | | | | +------+ +------+ | | | | | | | | | | ++ +-----------+ | | | +------+ +------+ |---------------------------+ | +-----------------------------------| | | +-----------------------------------| | | | +------+ +------+ +---------------------------+ | | | | | | | +-----------+ | | | +------+ +------+ | | | | | | +----+ L3 | | | | +------+ +------+ | | tag | | | | | | | | | | | | | | +------+ +------+ | +-----------+ | | | | | | +-----------------------------------+ | | +-----------------------------------+ | | | +------+ +------+ +--------------------------+ | | | | | | | +-----------+ | | | +------+ +------+ | | | | | There is a similar need for clustering in x86. Some x86 cores could share L2 caches that is similar to the cluster in Kupeng 920 (e.g. on Jacobsville there are 6 clusters of 4 Atom cores, each cluster sharing a separate L2, and 24 cores sharing L3). Having a sched_domain for clusters will bring two aspects of improvement: 1. spreading unrelated tasks among clusters, which decreases the contention of resources and improve the throughput. unrelated tasks might be put randomly without cluster sched_domain: +-------------------+ +-----------------+ | +----+ +----+ | | | | |task| |task| | | | | |1 | |2 | | | | | +----+ +----+ | | | | | | | | cluster1 | | cluster2 | +-------------------+ +-----------------+ but with cluster sched_domain, they are likely to spread due to LB: +-------------------+ +-----------------+ | +----+ | | +----+ | | |task| | | |task| | | |1 | | | |2 | | | +----+ | | +----+ | | | | | | cluster1 | | cluster2 | +-------------------+ +-----------------+ 2. gathering related tasks within a cluster, which improves the cache affinity of tasks talking with each other. Without cluster sched_domain, related tasks might be put randomly. In case task1-8 have relationship as below: Task1 wakes up task4 Task2 wakes up task5 Task3 wakes up task6 Task4 wakes up task7 With the tuning of select_idle_cpu() to scan local cluster first, those tasks might get a chance to be gathered like: +---------------------------+ +----------------------+ | +----+ +-----+ | | +----+ +-----+ | | |task| |task | | | |task| |task | | | |1 | | 4 | | | |2 | |5 | | | +----+ +-----+ | | +----+ +-----+ | | | | | | cluster1 | | cluster2 | | | | | | | | | | +-----+ +------+ | | +-----+ +------+ | | |task | | task | | | |task | |task | | | |3 | | 6 | | | |4 | |8 | | | +-----+ +------+ | | +-----+ +------+ | +---------------------------+ +----------------------+ Otherwise, the result might be: +---------------------------+ +----------------------+ | +----+ +-----+ | | +----+ +-----+ | | |task| |task | | | |task| |task | | | |1 | | 2 | | | |5 | |6 | | | +----+ +-----+ | | +----+ +-----+ | | | | | | cluster1 | | cluster2 | | | | | | | | | | +-----+ +------+ | | +-----+ +------+ | | |task | | task | | | |task | |task | | | |3 | | 4 | | | |7 | |8 | | | +-----+ +------+ | | +-----+ +------+ | +---------------------------+ +----------------------+ -v4: * rebased to tip/sched/core with the latest unified code of select_idle_cpu * added Tim's patch for x86 Jacobsville * also added benchmark data of spreading unrelated tasks * avoided the iteration of sched_domain by moving to static_key(addressing Vincent's comment * used acpi_cpu_id for acpi_find_processor_node(addressing Masa's comment) Barry Song (1): scheduler: add scheduler level for clusters Jonathan Cameron (1): topology: Represent clusters of CPUs within a die. Tim Chen (1): scheduler: Add cluster scheduler level for x86 Documentation/admin-guide/cputopology.rst | 26 ++++++++++-- arch/arm64/Kconfig | 7 ++++ arch/arm64/kernel/topology.c | 2 + arch/x86/Kconfig | 8 ++++ arch/x86/include/asm/smp.h | 7 ++++ arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/cacheinfo.c | 1 + arch/x86/kernel/cpu/common.c | 3 ++ arch/x86/kernel/smpboot.c | 43 +++++++++++++++++++- drivers/acpi/pptt.c | 63 +++++++++++++++++++++++++++++ drivers/base/arch_topology.c | 14 +++++++ drivers/base/topology.c | 10 +++++ include/linux/acpi.h | 5 +++ include/linux/arch_topology.h | 5 +++ include/linux/sched/cluster.h | 19 +++++++++ include/linux/sched/sd_flags.h | 9 +++++ include/linux/sched/topology.h | 7 ++++ include/linux/topology.h | 13 ++++++ kernel/sched/core.c | 18 +++++++++ kernel/sched/fair.c | 66 ++++++++++++++++++++++++------- kernel/sched/sched.h | 1 + kernel/sched/topology.c | 6 +++ 22 files changed, 315 insertions(+), 19 deletions(-) create mode 100644 include/linux/sched/cluster.h -- 1.8.3.1

6 15

[PATCH] Documentation/features: mark BATCHED_UNMAP_TLB_FLUSH doesn't apply to ARM64
by Barry Song 16 Mar '21

16 Mar '21

BATCHED_UNMAP_TLB_FLUSH is used on x86 to do batched tlb shootdown by sending one IPI to TLB flush all entries after unmapping pages rather than sending an IPI to flush each individual entry. On arm64, tlb shootdown is done by hardware. Flush instructions are innershareable. The local flushes are limited to the boot (1 per CPU) and when a task is getting a new ASID. So marking this feature as "TODO" is not proper. ".." isn't good as well. So this patch adds a "N/A" for this kind of features which are not needed on some architectures. Cc: Mel Gorman <mgorman(a)suse.de> Cc: Andy Lutomirski <luto(a)kernel.org> Cc: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- Documentation/features/arch-support.txt | 1 + Documentation/features/vm/TLB/arch-support.txt | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/features/arch-support.txt b/Documentation/features/arch-support.txt index d22a1095e661..118ae031840b 100644 --- a/Documentation/features/arch-support.txt +++ b/Documentation/features/arch-support.txt @@ -8,4 +8,5 @@ The meaning of entries in the tables is: | ok | # feature supported by the architecture |TODO| # feature not yet supported by the architecture | .. | # feature cannot be supported by the hardware + | N/A| # feature doesn't apply to the architecture diff --git a/Documentation/features/vm/TLB/arch-support.txt b/Documentation/features/vm/TLB/arch-support.txt index 30f75a79ce01..0d070f9f98d8 100644 --- a/Documentation/features/vm/TLB/arch-support.txt +++ b/Documentation/features/vm/TLB/arch-support.txt @@ -9,7 +9,7 @@ | alpha: | TODO | | arc: | TODO | | arm: | TODO | - | arm64: | TODO | + | arm64: | N/A | | c6x: | .. | | csky: | TODO | | h8300: | .. | -- 2.25.1

5 4

Re: [PATCH] lib/logic_pio: Fix overlap check for pio registery
by John Garry 15 Mar '21

15 Mar '21

On 21/12/2020 13:04, Jiahui Cen wrote: >> On 21/12/2020 03:24, Jiahui Cen wrote: >>> Hi John, >>> >>> On 2020/12/18 18:40, John Garry wrote: >>>> On 18/12/2020 06:23, Jiahui Cen wrote: >>>>> Since the [start, end) is a half-open interval, a range with the end equal >>>>> to the start of another range should not be considered as overlapped. >>>>> >>>>> Signed-off-by: Jiahui Cen<cenjiahui(a)huawei.com> >>>>> --- >>>>> lib/logic_pio.c | 2 +- >>>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>>> >>>>> diff --git a/lib/logic_pio.c b/lib/logic_pio.c >>>>> index f32fe481b492..445d611f1dc1 100644 >>>>> --- a/lib/logic_pio.c >>>>> +++ b/lib/logic_pio.c >>>>> @@ -57,7 +57,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range) >>>>> new_range->flags == LOGIC_PIO_CPU_MMIO) { >>>>> /* for MMIO ranges we need to check for overlap */ >>>>> if (start >= range->hw_start + range->size || >>>>> - end < range->hw_start) { >>>>> + end <= range->hw_start) { >>>> It looks like your change is correct, but should not really have an impact in practice since: >>>> a: BIOSes generally list ascending IO port CPU addresses >>>> b. there is space between IO port CPU address regions >>>> >>>> Have you seen a problem here? >>>> >>> No serious problem. I found it just when I was working on adding support of >>> pci expander bridge for Arm in QEMU. I found the IO window of some extended >>> root bus could not be registered when I inserted the extended buses' _CRS >>> info into DSDT table in the x86 way, which does not sort the buses. >>> >>> Though root buses should be sorted in QEMU, would it be better to accept >>> those non-ascending IO windows? >>> >> ok, so it seems that you have seen a real problem, and this issue is not just detected by code analysis. >> >>> BTW, for b, it seems to be no space between IO windows of different root buses >>> generated by EDK2. Or maybe I missed something obvious. >> I don't know about that. Anyway, your change looks ok. >> >> Reviewed-by: John Garry<john.garry(a)huawei.com> >> >> BTW, for your virt env, will there be requirement to unregister PCI MMIO ranges? Currently we don't see that in non-virt world. >> > Thanks for your review. > > And currently there is no such a requirement in my virt env. > I am not sure what happened to this patch, but I plan on sending some patches in this area soon - do you want me to include this one? Thanks, John

2 2

[PATCH RFC v2 rdma-core 0/6] libhns: Add support for Dynamic Context Attachment
by Weihang Li 15 Mar '21

15 Mar '21

The HIP09 introduces the DCA(Dynamic Context Attachment) feature which supports many RC QPs to share the WQE buffer in a memory pool. If a QP enables DCA feature, the WQE's buffer will not be allocated when creating but when the users start to post WRs. This will reduce the memory consumption when there are too many QPs are inactive. For more detailed information, please refer to the man pages provided by the last patch of this series. This series is associated with the kernel one "RDMA/hns: Add support for Dynamic Context Attachment", you can review it at: https://patchwork.kernel.org/project/linux-rdma/cover/1611394994-50363-1-gi… Changes since v1: - Add direct verbs to set the parameters about size that used to configuring DCA. - Add man pages to explain what is DCA, how does it works and how to use it. - Link: https://patchwork.kernel.org/project/linux-rdma/cover/1612667574-56673-1-gi… Weihang Li (1): Update kernel headers Xi Wang (5): libhns: Introduce DCA for RC QP libhns: Add support for shrinking DCA memory pool libhns: Add support for attaching QP's WQE buffer libhns: Add direct verb to support config DCA memory pool libhns: Add man pages to introduce DCA feature CMakeLists.txt | 1 + debian/ibverbs-providers.install | 1 + debian/ibverbs-providers.lintian-overrides | 4 +- debian/ibverbs-providers.symbols | 5 + debian/libibverbs-dev.install | 6 + kernel-headers/rdma/hns-abi.h | 64 +++++ libibverbs/cmd_qp.c | 3 +- libibverbs/man/ibv_create_qp_ex.3 | 1 + libibverbs/verbs.h | 1 + providers/hns/CMakeLists.txt | 9 +- providers/hns/hns_roce_u.c | 96 +++++++ providers/hns/hns_roce_u.h | 44 ++++ providers/hns/hns_roce_u_abi.h | 1 + providers/hns/hns_roce_u_buf.c | 387 +++++++++++++++++++++++++++++ providers/hns/hns_roce_u_hw_v2.c | 138 +++++++++- providers/hns/hns_roce_u_hw_v2.h | 7 + providers/hns/hns_roce_u_verbs.c | 44 +++- providers/hns/hnsdv.h | 44 ++++ providers/hns/libhns.map | 8 + providers/hns/man/CMakeLists.txt | 6 + providers/hns/man/hns_dca.7.md | 35 +++ providers/hns/man/hnsdv.7.md | 34 +++ providers/hns/man/hnsdv_is_supported.3.md | 39 +++ providers/hns/man/hnsdv_open_device.3.md | 70 ++++++ redhat/rdma-core.spec | 5 + suse/rdma-core.spec | 19 ++ 26 files changed, 1051 insertions(+), 21 deletions(-) create mode 100644 providers/hns/hnsdv.h create mode 100644 providers/hns/libhns.map create mode 100644 providers/hns/man/CMakeLists.txt create mode 100644 providers/hns/man/hns_dca.7.md create mode 100644 providers/hns/man/hnsdv.7.md create mode 100644 providers/hns/man/hnsdv_is_supported.3.md create mode 100644 providers/hns/man/hnsdv_open_device.3.md -- 2.8.1

3 8

[RESEND PATCH v2 0/2] scripts/gdb: clarify the platforms supporting lx_current and add arm64 support
by Barry Song 15 Mar '21

15 Mar '21

lx_current depends on per_cpu current_task variable which exists on x86 only. so it actually works on x86 only. the 1st patch documents this clearly; the 2nd patch adds support for arm64. -resend resending to Andrew as Kieran Bingham explained patches of scripts/gdb usually go through the tree of Andrew Morton; Barry Song (2): scripts/gdb: document lx_current is only supported by x86 scripts/gdb: add lx_current support for arm64 .../dev-tools/gdb-kernel-debugging.rst | 2 +- scripts/gdb/linux/cpus.py | 23 +++++++++++++++++-- 2 files changed, 22 insertions(+), 3 deletions(-) -- 2.25.1

1 2

[PATCH net-next 0/4] net: hns3: support imp-controlled PHYs
by Huazhong Tan 14 Mar '21

14 Mar '21

This series adds support for imp-controlled PHYs in the HNS3 ethernet driver. Guangbin Huang (4): net: hns3: add support for imp-controlled PHYs net: hns3: add get/set pause parameters support for imp-controlled PHYs net: hns3: add ioctl support for imp-controlled PHYs net: hns3: add phy loopback support for imp-controlled PHYs drivers/net/ethernet/hisilicon/hns3/hnae3.h | 4 + drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 + drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 9 +- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 4 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 44 +++- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 20 +- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 241 ++++++++++++++++++--- .../ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c | 39 ++++ .../ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h | 2 + 9 files changed, 321 insertions(+), 44 deletions(-) -- 2.7.4

2 5

[PATCH for-rc] RDMA/hns: Fix bug during CMDQ initialization
by Weihang Li 13 Mar '21

13 Mar '21

From: Lang Cheng <chenglang(a)huawei.com> When reloading driver, the head/tail pointer of CMDQ may be not at position 0. Then during initialization of CMDQ, if head is reset first, the firmware will start to handle CMDQ because the head is not equal to the tail. The driver can reset tail first since the firmware will be triggerred only by head. This bug is introduced by changing macros of head/tail register without changing the order of initialization. Besides, the same name represents opposite meanings in new/old driver, it is hard to maintain, so rename them to PI/CI. Fixes: 292b3352bd5b ("RDMA/hns: Adjust fields and variables about CMDQ tail/head") Signed-off-by: Lang Cheng <chenglang(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_common.h | 4 ++-- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 12 +++++++----- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h index 23c438c..8a18aa1 100644 --- a/drivers/infiniband/hw/hns/hns_roce_common.h +++ b/drivers/infiniband/hw/hns/hns_roce_common.h @@ -364,8 +364,8 @@ #define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000 #define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004 #define ROCEE_TX_CMQ_DEPTH_REG 0x07008 -#define ROCEE_TX_CMQ_HEAD_REG 0x07010 -#define ROCEE_TX_CMQ_TAIL_REG 0x07014 +#define ROCEE_TX_CMQ_PI_REG 0x07010 +#define ROCEE_TX_CMQ_CI_REG 0x07014 #define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018 #define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index c3934ab..c359f09 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1194,8 +1194,10 @@ static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) upper_32_bits(dma)); roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, (u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); - roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); - roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); + + /* Make sure to write CI first and then PI */ + roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); + roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); } else { roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, @@ -1275,7 +1277,7 @@ static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) { - u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_TAIL_REG); + u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); struct hns_roce_v2_priv *priv = hr_dev->priv; return tail == priv->cmq.csq.head; @@ -1303,7 +1305,7 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, } /* Write to hardware */ - roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, csq->head); + roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); /* If the command is sync, wait for the firmware to write back, * if multi descriptors to be sent, use the first one to check @@ -1334,7 +1336,7 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, } } else { /* FW/HW reset or incorrect number of desc */ - tail = roce_read(hr_dev, ROCEE_TX_CMQ_TAIL_REG); + tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n", csq->head, tail); csq->head = tail; -- 2.8.1

3 2

SEARCHING FOR A PARTNER
by dreyusmargariat＠gmail.com 13 Mar '21

13 Mar '21

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[PATCH net-next 0/2] net: hns3: two updates for -next
by Huazhong Tan 12 Mar '21

12 Mar '21

This series includes two updates for the HNS3 ethernet driver. Yufeng Mo (2): net: hns3: use FEC capability queried from firmware net: hns3: use pause capability queried from firmware drivers/net/ethernet/hisilicon/hns3/hnae3.h | 4 ++++ drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 3 +++ drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 8 +++++++ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 9 +++++++- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 2 ++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 26 +++++++++++++++------- 6 files changed, 43 insertions(+), 9 deletions(-) -- 2.7.4

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[PATCH v2 for-next] RDMA/hns: Add support for XRC on HIP09
by Weihang Li 12 Mar '21

12 Mar '21

From: Wenpeng Liang <liangwenpeng(a)huawei.com> The HIP09 supports XRC transport service, it greatly saves the number of QPs required to connect all processes in a large cluster. Signed-off-by: Wenpeng Liang <liangwenpeng(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- Changes since v1: - Change all type of xrcdn-related variables/fields to u32. - Link: https://patchwork.kernel.org/project/linux-rdma/patch/1614689298-13601-1-gi… drivers/infiniband/hw/hns/hns_roce_alloc.c | 3 + drivers/infiniband/hw/hns/hns_roce_device.h | 25 +++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 147 +++++++++++++++++++--------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 2 + drivers/infiniband/hw/hns/hns_roce_main.c | 32 +++++- drivers/infiniband/hw/hns/hns_roce_pd.c | 51 ++++++++++ drivers/infiniband/hw/hns/hns_roce_qp.c | 63 ++++++++---- drivers/infiniband/hw/hns/hns_roce_srq.c | 3 + include/uapi/rdma/hns-abi.h | 2 + 9 files changed, 258 insertions(+), 70 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_alloc.c b/drivers/infiniband/hw/hns/hns_roce_alloc.c index 4bcaaa05..5d389ed 100644 --- a/drivers/infiniband/hw/hns/hns_roce_alloc.c +++ b/drivers/infiniband/hw/hns/hns_roce_alloc.c @@ -304,6 +304,9 @@ int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev) { + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + hns_roce_cleanup_xrcd_table(hr_dev); + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) hns_roce_cleanup_srq_table(hr_dev); hns_roce_cleanup_qp_table(hr_dev); diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 3d6b7a2d..1a95fb7 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -137,6 +137,7 @@ enum { SERV_TYPE_UC, SERV_TYPE_RD, SERV_TYPE_UD, + SERV_TYPE_XRC = 5, }; enum hns_roce_qp_state { @@ -168,6 +169,8 @@ enum hns_roce_event { HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, HNS_ROCE_EVENT_TYPE_MB = 0x13, HNS_ROCE_EVENT_TYPE_FLR = 0x15, + HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, + HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, }; #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 @@ -179,6 +182,7 @@ enum { HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), HNS_ROCE_CAP_FLAG_SRQ = BIT(5), + HNS_ROCE_CAP_FLAG_XRC = BIT(6), HNS_ROCE_CAP_FLAG_MW = BIT(7), HNS_ROCE_CAP_FLAG_FRMR = BIT(8), HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), @@ -244,6 +248,11 @@ struct hns_roce_pd { unsigned long pdn; }; +struct hns_roce_xrcd { + struct ib_xrcd ibxrcd; + u32 xrcdn; +}; + struct hns_roce_bitmap { /* Bitmap Traversal last a bit which is 1 */ unsigned long last; @@ -467,6 +476,7 @@ struct hns_roce_srq { u32 rsv_sge; int wqe_shift; u32 cqn; + u32 xrcdn; void __iomem *db_reg_l; atomic_t refcount; @@ -640,6 +650,8 @@ struct hns_roce_qp { enum hns_roce_event event_type); unsigned long qpn; + u32 xrcdn; + atomic_t refcount; struct completion free; @@ -766,6 +778,8 @@ struct hns_roce_caps { int reserved_uars; int num_pds; int reserved_pds; + u32 num_xrcds; + u32 reserved_xrcds; u32 mtt_entry_sz; u32 cqe_sz; u32 page_size_cap; @@ -963,6 +977,7 @@ struct hns_roce_dev { struct hns_roce_cmdq cmd; struct hns_roce_bitmap pd_bitmap; + struct hns_roce_bitmap xrcd_bitmap; struct hns_roce_uar_table uar_table; struct hns_roce_mr_table mr_table; struct hns_roce_cq_table cq_table; @@ -1004,6 +1019,11 @@ static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) return container_of(ibpd, struct hns_roce_pd, ibpd); } +static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) +{ + return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); +} + static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) { return container_of(ibah, struct hns_roce_ah, ibah); @@ -1136,6 +1156,7 @@ int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); +int hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); @@ -1143,6 +1164,7 @@ void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); +void hns_roce_cleanup_xrcd_table(struct hns_roce_dev *hr_dev); int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, @@ -1207,6 +1229,9 @@ int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, struct ib_udata *udata); int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); +int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); +int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); + struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata); diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index c3934ab..593acf1 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1829,6 +1829,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; + caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; @@ -1846,6 +1847,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; caps->reserved_lkey = 0; caps->reserved_pds = 0; + caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; caps->reserved_mrws = 1; caps->reserved_uars = 0; caps->reserved_cqs = 0; @@ -1900,7 +1902,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | - HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; + HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC; caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; @@ -2131,6 +2133,8 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; caps->ceqe_size = HNS_ROCE_CEQE_SIZE; caps->aeqe_size = HNS_ROCE_AEQE_SIZE; + caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; + caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; caps->mtt_ba_pg_sz = 0; caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; @@ -3909,6 +3913,16 @@ static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, ilog2(hr_qp->rq.wqe_cnt)); } +static inline int get_cqn(struct ib_cq *ib_cq) +{ + return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; +} + +static inline int get_pdn(struct ib_pd *ib_pd) +{ + return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; +} + static void modify_qp_reset_to_init(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, @@ -3925,13 +3939,13 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, * 0 at the same time, else set them to 0x1. */ roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, - V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); + V2_QPC_BYTE_4_TST_S, to_hr_qp_type(ibqp->qp_type)); roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, - V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); + V2_QPC_BYTE_16_PD_S, get_pdn(ibqp->pd)); roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); @@ -3942,6 +3956,9 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); + if (ibqp->qp_type == IB_QPT_XRC_TGT) + context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); + if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) roce_set_bit(context->byte_68_rq_db, V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); @@ -3956,19 +3973,20 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, - V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); + V2_QPC_BYTE_80_RX_CQN_S, get_cqn(ibqp->recv_cq)); + if (ibqp->srq) { + roce_set_bit(context->byte_76_srqn_op_en, + V2_QPC_BYTE_76_SRQ_EN_S, 1); roce_set_field(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, to_hr_srq(ibqp->srq)->srqn); - roce_set_bit(context->byte_76_srqn_op_en, - V2_QPC_BYTE_76_SRQ_EN_S, 1); } roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1); roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, - V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); + V2_QPC_BYTE_252_TX_CQN_S, get_cqn(ibqp->send_cq)); if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) return; @@ -3991,22 +4009,28 @@ static void modify_qp_init_to_init(struct ib_qp *ibqp, * 0 at the same time, else set them to 0x1. */ roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, - V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); + V2_QPC_BYTE_4_TST_S, to_hr_qp_type(ibqp->qp_type)); roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, V2_QPC_BYTE_4_TST_S, 0); + if (ibqp->qp_type == IB_QPT_XRC_TGT) { + context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); + qpc_mask->qkey_xrcd = 0; + } + roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, - V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); + V2_QPC_BYTE_16_PD_S, get_pdn(ibqp->pd)); + roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, V2_QPC_BYTE_16_PD_S, 0); roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, - V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); + V2_QPC_BYTE_80_RX_CQN_S, get_cqn(ibqp->recv_cq)); roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, V2_QPC_BYTE_80_RX_CQN_S, 0); roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, - V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); + V2_QPC_BYTE_252_TX_CQN_S, get_cqn(ibqp->send_cq)); roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, V2_QPC_BYTE_252_TX_CQN_S, 0); @@ -4685,7 +4709,6 @@ static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, V2_QPC_BYTE_244_RNR_CNT_S, 0); } - /* RC&UC&UD required attr */ if (attr_mask & IB_QP_SQ_PSN) { roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, @@ -4763,7 +4786,6 @@ static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); } - /* RC&UC required attr */ if (attr_mask & IB_QP_RQ_PSN) { roce_set_field(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_RX_REQ_EPSN_M, @@ -4806,6 +4828,29 @@ static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, } } +static void clear_qp(struct hns_roce_qp *hr_qp) +{ + struct ib_qp *ibqp = &hr_qp->ibqp; + + if (ibqp->send_cq) + hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), + hr_qp->qpn, NULL); + + if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) + hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), + hr_qp->qpn, ibqp->srq ? + to_hr_srq(ibqp->srq) : NULL); + + if (hr_qp->rq.wqe_cnt) + *hr_qp->rdb.db_record = 0; + + hr_qp->rq.head = 0; + hr_qp->rq.tail = 0; + hr_qp->sq.head = 0; + hr_qp->sq.tail = 0; + hr_qp->next_sge = 0; +} + static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, enum ib_qp_state cur_state, @@ -4840,19 +4885,23 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, /* When QP state is err, SQ and RQ WQE should be flushed */ if (new_state == IB_QPS_ERR) { - spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); - hr_qp->state = IB_QPS_ERR; - roce_set_field(context->byte_160_sq_ci_pi, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, - hr_qp->sq.head); - roce_set_field(qpc_mask->byte_160_sq_ci_pi, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); - spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); - - if (!ibqp->srq) { + if (ibqp->qp_type != IB_QPT_XRC_TGT) { + spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); + hr_qp->state = IB_QPS_ERR; + roce_set_field(context->byte_160_sq_ci_pi, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, + hr_qp->sq.head); + roce_set_field(qpc_mask->byte_160_sq_ci_pi, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); + spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); + } + + if (!ibqp->srq && ibqp->qp_type != IB_QPT_XRC_INI && + ibqp->qp_type != IB_QPT_XRC_TGT) { spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); + hr_qp->state = IB_QPS_ERR; roce_set_field(context->byte_84_rq_ci_pi, V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, @@ -4871,7 +4920,8 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, goto out; roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, - ibqp->srq ? 1 : 0); + ((to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC) || + ibqp->srq) ? 1 : 0); roce_set_bit(qpc_mask->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, 0); @@ -4892,21 +4942,8 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); - if (new_state == IB_QPS_RESET && !ibqp->uobject) { - hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, - ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); - if (ibqp->send_cq != ibqp->recv_cq) - hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), - hr_qp->qpn, NULL); - - hr_qp->rq.head = 0; - hr_qp->rq.tail = 0; - hr_qp->sq.head = 0; - hr_qp->sq.tail = 0; - hr_qp->next_sge = 0; - if (hr_qp->rq.wqe_cnt) - *hr_qp->rdb.db_record = 0; - } + if (new_state == IB_QPS_RESET && !ibqp->uobject) + clear_qp(hr_qp); out: return ret; @@ -5017,7 +5054,9 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S); if (hr_qp->ibqp.qp_type == IB_QPT_RC || - hr_qp->ibqp.qp_type == IB_QPT_UC) { + hr_qp->ibqp.qp_type == IB_QPT_UC || + hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || + hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { struct ib_global_route *grh = rdma_ah_retrieve_grh(&qp_attr->ah_attr); @@ -5049,6 +5088,7 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, V2_QPC_BYTE_140_RR_MAX_S); + qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_MIN_RNR_TIME_M, V2_QPC_BYTE_80_MIN_RNR_TIME_S); @@ -5083,6 +5123,15 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, return ret; } +static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) +{ + return ((hr_qp->ibqp.qp_type == IB_QPT_RC || + hr_qp->ibqp.qp_type == IB_QPT_UD || + hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || + hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && + hr_qp->state != IB_QPS_RESET); +} + static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, struct ib_udata *udata) @@ -5092,9 +5141,7 @@ static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, unsigned long flags; int ret = 0; - if ((hr_qp->ibqp.qp_type == IB_QPT_RC || - hr_qp->ibqp.qp_type == IB_QPT_UD) && - hr_qp->state != IB_QPS_RESET) { + if (modify_qp_is_ok(hr_qp)) { /* Modify qp to reset before destroying qp */ ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET); @@ -5275,7 +5322,7 @@ static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) hr_reg_write(ctx, SRQC_SRQ_ST, 1); hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); hr_reg_write(ctx, SRQC_SRQN, srq->srqn); - hr_reg_write(ctx, SRQC_XRCD, 0); + hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); hr_reg_write(ctx, SRQC_RQWS, @@ -5479,6 +5526,12 @@ static void hns_roce_irq_work_handle(struct work_struct *work) case HNS_ROCE_EVENT_TYPE_FLR: ibdev_warn(ibdev, "Function level reset.\n"); break; + case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: + ibdev_err(ibdev, "xrc domain violation error.\n"); + break; + case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: + ibdev_err(ibdev, "invalid xrceth error.\n"); + break; default: break; } @@ -5579,6 +5632,8 @@ static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: + case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: + case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: hns_roce_qp_event(hr_dev, queue_num, event_type); break; case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 39621fb..ffdae15 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -74,6 +74,8 @@ #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 +#define HNS_ROCE_V2_MAX_XRCD_NUM 0x1000000 +#define HNS_ROCE_V2_RSV_XRCD_NUM 0 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c index c9c0836..1a747f7 100644 --- a/drivers/infiniband/hw/hns/hns_roce_main.c +++ b/drivers/infiniband/hw/hns/hns_roce_main.c @@ -207,6 +207,9 @@ static int hns_roce_query_device(struct ib_device *ib_dev, props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; } + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + props->device_cap_flags |= IB_DEVICE_XRC; + return 0; } @@ -300,6 +303,7 @@ static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, return -EAGAIN; resp.qp_tab_size = hr_dev->caps.num_qps; + resp.srq_tab_size = hr_dev->caps.num_srqs; ret = hns_roce_uar_alloc(hr_dev, &context->uar); if (ret) @@ -461,6 +465,13 @@ static const struct ib_device_ops hns_roce_dev_srq_ops = { INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), }; +static const struct ib_device_ops hns_roce_dev_xrcd_ops = { + .alloc_xrcd = hns_roce_alloc_xrcd, + .dealloc_xrcd = hns_roce_dealloc_xrcd, + + INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd), +}; + static int hns_roce_register_device(struct hns_roce_dev *hr_dev) { int ret; @@ -484,20 +495,20 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev) if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); - /* MW */ if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); - /* FRMR */ if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); - /* SRQ */ if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); } + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops); + ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); ib_set_device_ops(ib_dev, &hns_roce_dev_ops); for (i = 0; i < hr_dev->caps.num_ports; i++) { @@ -727,10 +738,19 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) goto err_uar_alloc_free; } + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) { + ret = hns_roce_init_xrcd_table(hr_dev); + if (ret) { + dev_err(dev, "failed to init xrcd table, ret = %d.\n", + ret); + goto err_pd_table_free; + } + } + ret = hns_roce_init_mr_table(hr_dev); if (ret) { dev_err(dev, "Failed to init memory region table.\n"); - goto err_pd_table_free; + goto err_xrcd_table_free; } hns_roce_init_cq_table(hr_dev); @@ -759,6 +779,10 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) hns_roce_cleanup_cq_table(hr_dev); hns_roce_cleanup_mr_table(hr_dev); +err_xrcd_table_free: + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + hns_roce_cleanup_xrcd_table(hr_dev); + err_pd_table_free: hns_roce_cleanup_pd_table(hr_dev); diff --git a/drivers/infiniband/hw/hns/hns_roce_pd.c b/drivers/infiniband/hw/hns/hns_roce_pd.c index cca818d..3ca51ce 100644 --- a/drivers/infiniband/hw/hns/hns_roce_pd.c +++ b/drivers/infiniband/hw/hns/hns_roce_pd.c @@ -137,3 +137,54 @@ void hns_roce_cleanup_uar_table(struct hns_roce_dev *hr_dev) { hns_roce_bitmap_cleanup(&hr_dev->uar_table.bitmap); } + +static int hns_roce_xrcd_alloc(struct hns_roce_dev *hr_dev, u32 *xrcdn) +{ + return hns_roce_bitmap_alloc(&hr_dev->xrcd_bitmap, + (unsigned long *)xrcdn); +} + +static void hns_roce_xrcd_free(struct hns_roce_dev *hr_dev, + u32 xrcdn) +{ + hns_roce_bitmap_free(&hr_dev->xrcd_bitmap, xrcdn, BITMAP_NO_RR); +} + +int hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev) +{ + return hns_roce_bitmap_init(&hr_dev->xrcd_bitmap, + hr_dev->caps.num_xrcds, + hr_dev->caps.num_xrcds - 1, + hr_dev->caps.reserved_xrcds, 0); +} + +void hns_roce_cleanup_xrcd_table(struct hns_roce_dev *hr_dev) +{ + hns_roce_bitmap_cleanup(&hr_dev->xrcd_bitmap); +} + +int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata) +{ + struct hns_roce_dev *hr_dev = to_hr_dev(ib_xrcd->device); + struct hns_roce_xrcd *xrcd = to_hr_xrcd(ib_xrcd); + int ret; + + if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)) + return -EINVAL; + + ret = hns_roce_xrcd_alloc(hr_dev, &xrcd->xrcdn); + if (ret) { + dev_err(hr_dev->dev, "failed to alloc xrcdn, ret = %d.\n", ret); + return ret; + } + + return 0; +} + +int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata) +{ + hns_roce_xrcd_free(to_hr_dev(ib_xrcd->device), + to_hr_xrcd(ib_xrcd)->xrcdn); + + return 0; +} diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index 004aca9..9169225 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -98,7 +98,9 @@ void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 && (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR || event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR || - event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR)) { + event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR || + event_type == HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION || + event_type == HNS_ROCE_EVENT_TYPE_INVALID_XRCETH)) { qp->state = IB_QPS_ERR; if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) init_flush_work(hr_dev, qp); @@ -142,6 +144,8 @@ static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, event.event = IB_EVENT_QP_REQ_ERR; break; case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: + case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: + case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: event.event = IB_EVENT_QP_ACCESS_ERR; break; default: @@ -366,8 +370,13 @@ void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) unsigned long flags; list_del(&hr_qp->node); - list_del(&hr_qp->sq_node); - list_del(&hr_qp->rq_node); + + if (hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) + list_del(&hr_qp->sq_node); + + if (hr_qp->ibqp.qp_type != IB_QPT_XRC_INI && + hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) + list_del(&hr_qp->rq_node); xa_lock_irqsave(xa, flags); __xa_erase(xa, hr_qp->qpn & (hr_dev->caps.num_qps - 1)); @@ -1100,11 +1109,16 @@ static int check_qp_type(struct hns_roce_dev *hr_dev, enum ib_qp_type type, bool is_user) { switch (type) { + case IB_QPT_XRC_INI: + case IB_QPT_XRC_TGT: + if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)) + goto out; + break; case IB_QPT_UD: if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08 && is_user) goto out; - fallthrough; + break; case IB_QPT_RC: case IB_QPT_GSI: break; @@ -1124,8 +1138,8 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata) { - struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); - struct ib_device *ibdev = &hr_dev->ib_dev; + struct ib_device *ibdev = pd ? pd->device : init_attr->xrcd->device; + struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); struct hns_roce_qp *hr_qp; int ret; @@ -1137,6 +1151,15 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, if (!hr_qp) return ERR_PTR(-ENOMEM); + if (init_attr->qp_type == IB_QPT_XRC_INI) + init_attr->recv_cq = NULL; + + if (init_attr->qp_type == IB_QPT_XRC_TGT) { + hr_qp->xrcdn = to_hr_xrcd(init_attr->xrcd)->xrcdn; + init_attr->recv_cq = NULL; + init_attr->send_cq = NULL; + } + if (init_attr->qp_type == IB_QPT_GSI) { hr_qp->port = init_attr->port_num - 1; hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; @@ -1156,20 +1179,20 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, int to_hr_qp_type(int qp_type) { - int transport_type; - - if (qp_type == IB_QPT_RC) - transport_type = SERV_TYPE_RC; - else if (qp_type == IB_QPT_UC) - transport_type = SERV_TYPE_UC; - else if (qp_type == IB_QPT_UD) - transport_type = SERV_TYPE_UD; - else if (qp_type == IB_QPT_GSI) - transport_type = SERV_TYPE_UD; - else - transport_type = -1; - - return transport_type; + switch (qp_type) { + case IB_QPT_RC: + return SERV_TYPE_RC; + case IB_QPT_UC: + return SERV_TYPE_UC; + case IB_QPT_UD: + case IB_QPT_GSI: + return SERV_TYPE_UD; + case IB_QPT_XRC_INI: + case IB_QPT_XRC_TGT: + return SERV_TYPE_XRC; + default: + return -1; + } } static int check_mtu_validate(struct hns_roce_dev *hr_dev, diff --git a/drivers/infiniband/hw/hns/hns_roce_srq.c b/drivers/infiniband/hw/hns/hns_roce_srq.c index d5a6de0..f71459a 100644 --- a/drivers/infiniband/hw/hns/hns_roce_srq.c +++ b/drivers/infiniband/hw/hns/hns_roce_srq.c @@ -314,6 +314,9 @@ static void set_srq_ext_param(struct hns_roce_srq *srq, { srq->cqn = ib_srq_has_cq(init_attr->srq_type) ? to_hr_cq(init_attr->ext.cq)->cqn : 0; + + srq->xrcdn = (init_attr->srq_type == IB_SRQT_XRC) ? + to_hr_xrcd(init_attr->ext.xrc.xrcd)->xrcdn : 0; } static int set_srq_param(struct hns_roce_srq *srq, diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h index 90b739d..42b1776 100644 --- a/include/uapi/rdma/hns-abi.h +++ b/include/uapi/rdma/hns-abi.h @@ -86,6 +86,8 @@ struct hns_roce_ib_create_qp_resp { struct hns_roce_ib_alloc_ucontext_resp { __u32 qp_tab_size; __u32 cqe_size; + __u32 srq_tab_size; + __u32 reserved; }; struct hns_roce_ib_alloc_pd_resp { -- 2.8.1

2 1

[PATCH net-next] skbuff: remove some unnecessary operation in skb_segment_list()
by l00371289 11 Mar '21

11 Mar '21

From: Yunsheng Lin <linyunsheng(a)huawei.com> gro list uses skb_shinfo(skb)->frag_list to link two skb together, and NAPI_GRO_CB(p)->last->next is used when there are more skb, see skb_gro_receive_list(). gso expects that each segmented skb is linked together using skb->next, so only the first skb->next need to set to skb_shinfo(skb)-> frag_list when doing gso list segment. It is the same reason that nskb->next does not need to be set to list_skb before goto the error handling, because nskb->next already pointers to list_skb. And nskb is also the last skb at the end of loop, so remove tail variable and use nskb instead. Signed-off-by: Yunsheng Lin <linyunsheng(a)huawei.com> --- net/core/skbuff.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/net/core/skbuff.c b/net/core/skbuff.c index c421c8f..e8320b5 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -3732,13 +3732,13 @@ struct sk_buff *skb_segment_list(struct sk_buff *skb, unsigned int tnl_hlen = skb_tnl_header_len(skb); unsigned int delta_truesize = 0; unsigned int delta_len = 0; - struct sk_buff *tail = NULL; struct sk_buff *nskb, *tmp; int err; skb_push(skb, -skb_network_offset(skb) + offset); skb_shinfo(skb)->frag_list = NULL; + skb->next = list_skb; do { nskb = list_skb; @@ -3756,17 +3756,8 @@ struct sk_buff *skb_segment_list(struct sk_buff *skb, } } - if (!tail) - skb->next = nskb; - else - tail->next = nskb; - - if (unlikely(err)) { - nskb->next = list_skb; + if (unlikely(err)) goto err_linearize; - } - - tail = nskb; delta_len += nskb->len; delta_truesize += nskb->truesize; @@ -3793,7 +3784,7 @@ struct sk_buff *skb_segment_list(struct sk_buff *skb, skb_gso_reset(skb); - skb->prev = tail; + skb->prev = nskb; if (skb_needs_linearize(skb, features) && __skb_linearize(skb)) -- 2.7.4

2 1

[PATCH for-next] RDMA/hns: Use new SQ doorbell register for HIP09
by Weihang Li 11 Mar '21

11 Mar '21

From: Lang Cheng <chenglang(a)huawei.com> HIP09 uses new address space to map SQ doorbell registers, the doorbell of each QP is isolated based on the size of 64KB, which can improve the performance in concurrency scenarios. Signed-off-by: Lang Cheng <chenglang(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 3 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 49 ++++++++++++++++-------------- 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index c3934ab..18394e5 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -681,8 +681,7 @@ static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); - hns_roce_write512(hr_dev, wqe, hr_dev->mem_base + - HNS_ROCE_DWQE_SIZE * qp->ibqp.qp_num); + hns_roce_write512(hr_dev, wqe, qp->sq.db_reg_l); } static int hns_roce_v2_post_send(struct ib_qp *ibqp, diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index 8af411f..2318e3e 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -840,9 +840,14 @@ static int alloc_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, resp->cap_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; } } else { - /* QP doorbell register address */ - hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset + - DB_REG_OFFSET * hr_dev->priv_uar.index; + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) + hr_qp->sq.db_reg_l = hr_dev->mem_base + + HNS_ROCE_DWQE_SIZE * hr_qp->qpn; + else + hr_qp->sq.db_reg_l = + hr_dev->reg_base + hr_dev->sdb_offset + + DB_REG_OFFSET * hr_dev->priv_uar.index; + hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset + DB_REG_OFFSET * hr_dev->priv_uar.index; @@ -1011,36 +1016,36 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, } } - ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp); - if (ret) { - ibdev_err(ibdev, "failed to alloc QP doorbell, ret = %d.\n", - ret); - goto err_wrid; - } - ret = alloc_qp_buf(hr_dev, hr_qp, init_attr, udata, ucmd.buf_addr); if (ret) { ibdev_err(ibdev, "failed to alloc QP buffer, ret = %d.\n", ret); - goto err_db; + goto err_buf; } ret = alloc_qpn(hr_dev, hr_qp); if (ret) { ibdev_err(ibdev, "failed to alloc QPN, ret = %d.\n", ret); - goto err_buf; + goto err_qpn; + } + + ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp); + if (ret) { + ibdev_err(ibdev, "failed to alloc QP doorbell, ret = %d.\n", + ret); + goto err_db; } ret = alloc_qpc(hr_dev, hr_qp); if (ret) { ibdev_err(ibdev, "failed to alloc QP context, ret = %d.\n", ret); - goto err_qpn; + goto err_qpc; } ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr); if (ret) { ibdev_err(ibdev, "failed to store QP, ret = %d.\n", ret); - goto err_qpc; + goto err_store; } if (udata) { @@ -1055,7 +1060,7 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp); if (ret) - goto err_store; + goto err_flow_ctrl; } hr_qp->ibqp.qp_num = hr_qp->qpn; @@ -1065,17 +1070,17 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, return 0; -err_store: +err_flow_ctrl: hns_roce_qp_remove(hr_dev, hr_qp); -err_qpc: +err_store: free_qpc(hr_dev, hr_qp); -err_qpn: +err_qpc: + free_qp_db(hr_dev, hr_qp, udata); +err_db: free_qpn(hr_dev, hr_qp); -err_buf: +err_qpn: free_qp_buf(hr_dev, hr_qp); -err_db: - free_qp_db(hr_dev, hr_qp, udata); -err_wrid: +err_buf: free_kernel_wrid(hr_qp); return ret; } -- 2.8.1

2 1

Re: [RESEND PATCH] PCI: Factor functions of PCI function reset
by Yicong Yang 10 Mar '21

10 Mar '21

On 2021/3/9 23:50, Bjorn Helgaas wrote: > [+cc Alex, Krzysztof] > > On Wed, Nov 11, 2020 at 06:22:03PM +0800, Yicong Yang wrote: >> Previosly we use pci_probe_reset_function() to probe whehter a function >> can be reset and use __pci_reset_function_locked() to perform a function >> reset. These two functions have lots of common lines. > > s/Previosly/Previously/ > s/we use/we used/ > s/whehter/whether/ will fix. > > I'm not a big fan of dual-purpose functions that decide whether to > probe or to reset based on a parameter. Those two things just don't > seem semantically compatible. But I do see your point about common > lines, and the underlying functions (pci_dev_specific_reset(), > pci_af_flr(), etc) already have that structure. > i noticed this when i tried to fix another issue with FLR[1]. as you said, the underlying functions use the probe flag to indicate whether it is a probe operation or not and i think it make sense to reduce the redundency in the same way. > Let me think about this some more. > sure, of course. It's also very kind to have any comments on the previous issue we met: [1] https://lore.kernel.org/linux-pci/1605090088-13960-1-git-send-email-yangyic… Thanks, Yicong >> Factor the two functions and reduce the redundancy. >> >> Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> >> --- >> drivers/pci/pci.c | 61 ++++++++++++++++------------------------------------- >> drivers/pci/pci.h | 2 +- >> drivers/pci/probe.c | 2 +- >> 3 files changed, 20 insertions(+), 45 deletions(-) >> >> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c >> index e39c549..e3e5f0f 100644 >> --- a/drivers/pci/pci.c >> +++ b/drivers/pci/pci.c >> @@ -5006,9 +5006,11 @@ static void pci_dev_restore(struct pci_dev *dev) >> } >> >> /** >> - * __pci_reset_function_locked - reset a PCI device function while holding >> - * the @dev mutex lock. >> + * pci_probe_reset_function - check whether the device can be safely reset >> + * or reset a PCI device function while holding >> + * the @dev mutex lock. >> * @dev: PCI device to reset >> + * @probe: Probe or not whether the device can be reset. >> * >> * Some devices allow an individual function to be reset without affecting >> * other functions in the same device. The PCI device must be responsive >> @@ -5022,10 +5024,10 @@ static void pci_dev_restore(struct pci_dev *dev) >> * device including MSI, bus mastering, BARs, decoding IO and memory spaces, >> * etc. >> * >> - * Returns 0 if the device function was successfully reset or negative if the >> - * device doesn't support resetting a single function. >> + * Returns 0 if the device function can be reset or was successfully reset. >> + * negative if the device doesn't support resetting a single function. >> */ >> -int __pci_reset_function_locked(struct pci_dev *dev) >> +int pci_probe_reset_function(struct pci_dev *dev, int probe) >> { >> int rc; >> >> @@ -5039,61 +5041,34 @@ int __pci_reset_function_locked(struct pci_dev *dev) >> * other error, we're also finished: this indicates that further >> * reset mechanisms might be broken on the device. >> */ >> - rc = pci_dev_specific_reset(dev, 0); >> + rc = pci_dev_specific_reset(dev, probe); >> if (rc != -ENOTTY) >> return rc; >> if (pcie_has_flr(dev)) { >> + if (probe) >> + return 0; >> rc = pcie_flr(dev); >> if (rc != -ENOTTY) >> return rc; >> } >> - rc = pci_af_flr(dev, 0); >> + rc = pci_af_flr(dev, probe); >> if (rc != -ENOTTY) >> return rc; >> - rc = pci_pm_reset(dev, 0); >> + rc = pci_pm_reset(dev, probe); >> if (rc != -ENOTTY) >> return rc; >> - rc = pci_dev_reset_slot_function(dev, 0); >> + rc = pci_dev_reset_slot_function(dev, probe); >> if (rc != -ENOTTY) >> return rc; >> - return pci_parent_bus_reset(dev, 0); >> + >> + return pci_parent_bus_reset(dev, probe); >> } >> -EXPORT_SYMBOL_GPL(__pci_reset_function_locked); >> >> -/** >> - * pci_probe_reset_function - check whether the device can be safely reset >> - * @dev: PCI device to reset >> - * >> - * Some devices allow an individual function to be reset without affecting >> - * other functions in the same device. The PCI device must be responsive >> - * to PCI config space in order to use this function. >> - * >> - * Returns 0 if the device function can be reset or negative if the >> - * device doesn't support resetting a single function. >> - */ >> -int pci_probe_reset_function(struct pci_dev *dev) >> +int __pci_reset_function_locked(struct pci_dev *dev) >> { >> - int rc; >> - >> - might_sleep(); >> - >> - rc = pci_dev_specific_reset(dev, 1); >> - if (rc != -ENOTTY) >> - return rc; >> - if (pcie_has_flr(dev)) >> - return 0; >> - rc = pci_af_flr(dev, 1); >> - if (rc != -ENOTTY) >> - return rc; >> - rc = pci_pm_reset(dev, 1); >> - if (rc != -ENOTTY) >> - return rc; >> - rc = pci_dev_reset_slot_function(dev, 1); >> - if (rc != -ENOTTY) >> - return rc; >> - >> - return pci_parent_bus_reset(dev, 1); >> + return pci_probe_reset_function(dev, 0); >> } >> +EXPORT_SYMBOL_GPL(__pci_reset_function_locked); >> >> /** >> * pci_reset_function - quiesce and reset a PCI device function >> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h >> index fa12f7c..73740dd 100644 >> --- a/drivers/pci/pci.h >> +++ b/drivers/pci/pci.h >> @@ -39,7 +39,7 @@ enum pci_mmap_api { >> int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, >> enum pci_mmap_api mmap_api); >> >> -int pci_probe_reset_function(struct pci_dev *dev); >> +int pci_probe_reset_function(struct pci_dev *dev, int probe); >> int pci_bridge_secondary_bus_reset(struct pci_dev *dev); >> int pci_bus_error_reset(struct pci_dev *dev); >> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index 03d3712..793cc8a 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -2403,7 +2403,7 @@ static void pci_init_capabilities(struct pci_dev *dev) >> >> pcie_report_downtraining(dev); >> >> - if (pci_probe_reset_function(dev) == 0) >> + if (pci_probe_reset_function(dev, 1) == 0) >> dev->reset_fn = 1; >> } >> >> -- >> 2.8.1 >> > > . >

1 0

hi there
by J. Kirinec 09 Mar '21

09 Mar '21

Hello there, How are you today? fine i hope. It's nice to meet you, and I hope you do not mind me being connected with you in such a way. in actual fact i was looking for my old friend who reside in your country and that was when I came across your profile and I decided to write you. My name is J. Kirinec, USA marine officer. I am in charge of medic. I will like to hear from you if it so please with you, i believe it's curiosity that brings me to you in a time like this. It will be my wish to establish a very strong relationship with you because I felt the both of us want the same thing. Once again I must say that I am sorry if the connection with you contradicts your moral ethics. I look forward to hearing from you. Regards, J. Kirinec

1 0

[PATCH] sched/topology: Fix a typo in pr_err()
by Yicong Yang 08 Mar '21

08 Mar '21

Fix a typo 'borken' to 'broken' in pr_err(). Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> --- kernel/sched/topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 09d3504..c42e388 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -1906,7 +1906,7 @@ static struct sched_domain *build_sched_domain(struct sched_domain_topology_leve if (!cpumask_subset(sched_domain_span(child), sched_domain_span(sd))) { - pr_err("BUG: arch topology borken\n"); + pr_err("BUG: arch topology broken\n"); #ifdef CONFIG_SCHED_DEBUG pr_err(" the %s domain not a subset of the %s domain\n", child->name, sd->name); -- 2.8.1

2 2

【Some Questions About Multi-Process Resource Cleaning】
by oulijun 08 Mar '21

08 Mar '21

Hi, Thomas Monjalon&Ferruh Yigit and others I'm analyzing multiprocess with eal. I have some questions I'd like to ask you. Firstly, After the rte_eal_init() command is executed, the master and slave processes are started successfully. and traffic is continuously sent using the tester.If you run the kill -9 command to stop the slave process, restart the re-process, and start packet receiving and sending, how to ensure that the eal resource of the slave process is cleaned up? Second, how to invoke the remove function to clear probe resources of the slave process after the slave process exits? Finally, I found out why the rte_eal_cleanup call was not unregistered mp action after the process exited. I look forward to your response. Thanks Lijun Ou

4 6

[PATCH v1] drm/nouveau/device: use snprintf() to replace strncpy() to avoid NUL-terminated string loss
by Luo Jiaxing 08 Mar '21

08 Mar '21

Following warning is found when using W=1 to build kernel: In function ‘nvkm_udevice_info’, inlined from ‘nvkm_udevice_mthd’ at drivers/gpu/drm/nouveau/nvkm/engine/device/user.c:195:10: drivers/gpu/drm/nouveau/nvkm/engine/device/user.c:164:2: warning: ‘strncpy’ specified bound 16 equals destination size [-Wstringop-truncation] 164 | strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip)); drivers/gpu/drm/nouveau/nvkm/engine/device/user.c:165:2: warning: ‘strncpy’ specified bound 64 equals destination size [-Wstringop-truncation] 165 | strncpy(args->v0.name, device->name, sizeof(args->v0.name)); The reason of this warning is strncpy() does not guarantee that the destination buffer will be NUL terminated. If the length of source string is bigger than number we set by third input parameter, only a part of characters is copied to the destination, and no NUL-terminated string is automatically added. There are some potential risks. So use snprintf() to replace strncpy(). Signed-off-by: Luo Jiaxing <luojiaxing(a)huawei.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index fea9d8f..4bf65bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -161,8 +161,8 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size) if (imem && args->v0.ram_size > 0) args->v0.ram_user = args->v0.ram_user - imem->reserved; - strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip)); - strncpy(args->v0.name, device->name, sizeof(args->v0.name)); + snprintf(args->v0.chip, sizeof(args->v0.chip), "%s", device->chip->name); + snprintf(args->v0.name, sizeof(args->v0.name), "%s", device->name); return 0; } -- 2.7.4

1 0

[PATCH] sched/topology: remove redundant cpumask_and in init_overlap_sched_group
by Barry Song 08 Mar '21

08 Mar '21

mask is built in build_balance_mask() by for_each_cpu(i, sg_span), so it must be a subset of sched_group_span(sg). Though cpumask_first_and doesn't lead to a wrong result of balance cpu, it is pointless to do cpumask_and again. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/sched/topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 12f8058..45f3db2 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -934,7 +934,7 @@ static void init_overlap_sched_group(struct sched_domain *sd, int cpu; build_balance_mask(sd, sg, mask); - cpu = cpumask_first_and(sched_group_span(sg), mask); + cpu = cpumask_first(mask); sg->sgc = *per_cpu_ptr(sdd->sgc, cpu); if (atomic_inc_return(&sg->sgc->ref) == 1) -- 1.8.3.1

3 3

[PATCH 0/3] Add support for HiSilicon I2C controller
by Yicong Yang 08 Mar '21

08 Mar '21

Add driver and MAINTAINERS for HiSilicon I2C controller on Kunpeng SoC. Also provide the devm_*() variants for adding the I2C adapters. Yicong Yang (3): i2c: core: add managed function for adding i2c adapters i2c: add support for HiSilicon I2C controller MAINTAINERS: Add maintainer for HiSilicon I2C driver MAINTAINERS | 7 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-hisi.c | 525 ++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/i2c-core-base.c | 39 ++++ include/linux/i2c.h | 1 + 6 files changed, 583 insertions(+) create mode 100644 drivers/i2c/busses/i2c-hisi.c -- 2.8.1

2 4

[bug report] irqbalance change the affinity of irq
by tiantao (H) 06 Mar '21

06 Mar '21

Hi All： I found a strange phenomenon about smmu interrupting affinity. The background is as follows. First. I have a kunpeng920 with two cpu's, four numa nodes, each numa has 32core, and each cpu has two smmu devices, which are located in numa 0 and numa 2 separately. Secondly. I know the irq number of smmu evtq by the following patch, here if this irq number is 26 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8594b4a..ce894bc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2945,6 +2945,7 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) switch (desc->platform.msi_index) { case EVTQ_MSI_INDEX: smmu->evtq.q.irq = desc->irq; + dev_err(smmu->dev, "evtq irq number %d\n", desc->irq); The strange phenomenon is as follows. After the system boots normally, the system load is very low at this time and I can know that the irq number is on numa 1 with the following command localhost:~ # cat /proc/irq/26/smp_affinity_list 32-63 But this is wrong, the irq should be set to numa 0 for the correct affinity. When I disable irqbalance.service via command "systemctl disable irqbalance.service" and then reboot the system. After checking in the log again that the irq number of smmu evtq is still 26, then I can get the correct result by querying with the following command. localhost:~ # cat /proc/irq/26/smp_affinity_list 0-31 Why does irqbalance cause the affinity of smmu's evtq interrupt to be set to a numa node that the smmu device is not on?

3 2

[PATCH 0/3] testpmd updates
by Lijun Ou 05 Mar '21

05 Mar '21

This series add a API implementation for testpmd as well as fix two bugs. Chengwen Feng (1): app/testpmd: support Tx mbuf free on demand cmd Hongbo Zheng (1): app/testpmd: fix mixed use of RX/Rx/TX/Tx in testpmd Huisong Li (1): app/testpmd: remove forwarding config from parsing Rx and Tx app/test-pmd/cmdline.c | 93 ++++++++++++++++++++++++++++- app/test-pmd/config.c | 18 +++--- doc/guides/rel_notes/release_21_05.rst | 2 + doc/guides/testpmd_app_ug/testpmd_funcs.rst | 7 +++ 4 files changed, 109 insertions(+), 11 deletions(-) -- 2.7.4

3 9

[RFC V2] app/testpmd: support multi-process
by Lijun Ou 05 Mar '21

05 Mar '21

This patch adds multi-process support for testpmd. The test cmd example as follows: the primary cmd: ./testpmd -w xxx --file-prefix=xx -l 0-1 -n 2 -- -i\ --rxq=16 --txq=16 --num-procs=2 --proc-id=0 the secondary cmd: ./testpmd -w xxx --file-prefix=xx -l 2-3 -n 2 -- -i\ --rxq=16 --txq=16 --num-procs=2 --proc-id=1 Signed-off-by: Min Hu (Connor) <humin29(a)huawei.com> Signed-off-by: Lijun Ou <oulijun(a)huawei.com> --- app/test-pmd/cmdline.c | 6 ++- app/test-pmd/config.c | 9 +++- app/test-pmd/parameters.c | 9 ++++ app/test-pmd/testpmd.c | 135 +++++++++++++++++++++++++++++----------------- app/test-pmd/testpmd.h | 7 +++ 5 files changed, 114 insertions(+), 52 deletions(-) diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c index 89034c8..48af5cd 100644 --- a/app/test-pmd/cmdline.c +++ b/app/test-pmd/cmdline.c @@ -71,8 +71,6 @@ #include "cmdline_tm.h" #include "bpf_cmd.h" -static struct cmdline *testpmd_cl; - static void cmd_reconfig_device_queue(portid_t id, uint8_t dev, uint8_t queue); /* *** Help command with introduction. *** */ @@ -17124,6 +17122,10 @@ prompt(void) if (testpmd_cl == NULL) return; cmdline_interact(testpmd_cl); + if (unlikely(f_quit == 1)) { + dup2(testpmd_fd_copy, testpmd_cl->s_in); + close(testpmd_fd_copy); + } cmdline_stdin_exit(testpmd_cl); } diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c index 0e2b9f7..f065008 100644 --- a/app/test-pmd/config.c +++ b/app/test-pmd/config.c @@ -3100,6 +3100,8 @@ rss_fwd_config_setup(void) queueid_t rxq; queueid_t nb_q; streamid_t sm_id; + int start; + int end; nb_q = nb_rxq; if (nb_q > nb_txq) @@ -3117,7 +3119,10 @@ rss_fwd_config_setup(void) init_fwd_streams(); setup_fwd_config_of_each_lcore(&cur_fwd_config); - rxp = 0; rxq = 0; + start = proc_id * nb_q / num_procs; + end = start + nb_q / num_procs; + rxp = 0; + rxq = start; for (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) { struct fwd_stream *fs; @@ -3134,6 +3139,8 @@ rss_fwd_config_setup(void) continue; rxp = 0; rxq++; + if (rxq >= end) + rxq = start; } } diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c index df5eb10..ac63854 100644 --- a/app/test-pmd/parameters.c +++ b/app/test-pmd/parameters.c @@ -45,6 +45,8 @@ #include <rte_flow.h> #include "testpmd.h" +#define PARAM_PROC_ID "proc-id" +#define PARAM_NUM_PROCS "num-procs" static void usage(char* progname) @@ -603,6 +605,8 @@ launch_args_parse(int argc, char** argv) { "rx-mq-mode", 1, 0, 0 }, { "record-core-cycles", 0, 0, 0 }, { "record-burst-stats", 0, 0, 0 }, + { PARAM_NUM_PROCS, 1, 0, 0 }, + { PARAM_PROC_ID, 1, 0, 0 }, { 0, 0, 0, 0 }, }; @@ -1356,6 +1360,11 @@ launch_args_parse(int argc, char** argv) record_core_cycles = 1; if (!strcmp(lgopts[opt_idx].name, "record-burst-stats")) record_burst_stats = 1; + + if (strncmp(lgopts[opt_idx].name, PARAM_NUM_PROCS, 8) == 0) + num_procs = atoi(optarg); + if (strncmp(lgopts[opt_idx].name, PARAM_PROC_ID, 7) == 0) + proc_id = atoi(optarg); break; case 'h': usage(argv[0]); diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index c256e71..3abd080 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -63,6 +63,8 @@ #include "testpmd.h" +int testpmd_fd_copy = 500; /* the copy of STDIN_FILENO */ + #ifndef MAP_HUGETLB /* FreeBSD may not have MAP_HUGETLB (in fact, it probably doesn't) */ #define HUGE_FLAG (0x40000) @@ -125,6 +127,9 @@ uint8_t port_numa[RTE_MAX_ETHPORTS]; */ uint8_t rxring_numa[RTE_MAX_ETHPORTS]; +int proc_id = 0; +unsigned num_procs = 1; + /* * Store specified sockets on which TX ring to be used by ports * is allocated. @@ -978,16 +983,26 @@ mbuf_pool_create(uint16_t mbuf_seg_size, unsigned nb_mbuf, /* wrapper to rte_mempool_create() */ TESTPMD_LOG(INFO, "preferred mempool ops selected: %s\n", rte_mbuf_best_mempool_ops()); - rte_mp = rte_pktmbuf_pool_create(pool_name, nb_mbuf, - mb_mempool_cache, 0, mbuf_seg_size, socket_id); + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + rte_mp = rte_pktmbuf_pool_create(pool_name, + nb_mbuf, mb_mempool_cache, 0, + mbuf_seg_size, socket_id); + else + rte_mp = rte_mempool_lookup(pool_name); + break; } case MP_ALLOC_ANON: { - rte_mp = rte_mempool_create_empty(pool_name, nb_mbuf, - mb_size, (unsigned int) mb_mempool_cache, - sizeof(struct rte_pktmbuf_pool_private), - socket_id, mempool_flags); + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + rte_mp = rte_mempool_create_empty(pool_name, + nb_mbuf, mb_size, + (unsigned int)mb_mempool_cache, + sizeof(struct rte_pktmbuf_pool_private), + socket_id, mempool_flags); + else + rte_mp = rte_mempool_lookup(pool_name); + if (rte_mp == NULL) goto err; @@ -1017,9 +1032,13 @@ mbuf_pool_create(uint16_t mbuf_seg_size, unsigned nb_mbuf, TESTPMD_LOG(INFO, "preferred mempool ops selected: %s\n", rte_mbuf_best_mempool_ops()); - rte_mp = rte_pktmbuf_pool_create(pool_name, nb_mbuf, - mb_mempool_cache, 0, mbuf_seg_size, - heap_socket); + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + rte_mp = rte_pktmbuf_pool_create(pool_name, + nb_mbuf, mb_mempool_cache, 0, + mbuf_seg_size, heap_socket); + else + rte_mp = rte_mempool_lookup(pool_name); + break; } case MP_ALLOC_XBUF: @@ -2503,21 +2522,28 @@ start_port(portid_t pid) return -1; } /* configure port */ - diag = rte_eth_dev_configure(pi, nb_rxq + nb_hairpinq, + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + diag = rte_eth_dev_configure(pi, + nb_rxq + nb_hairpinq, nb_txq + nb_hairpinq, &(port->dev_conf)); - if (diag != 0) { - if (rte_atomic16_cmpset(&(port->port_status), - RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) - printf("Port %d can not be set back " - "to stopped\n", pi); - printf("Fail to configure port %d\n", pi); - /* try to reconfigure port next time */ - port->need_reconfig = 1; - return -1; + if (diag != 0) { + if (rte_atomic16_cmpset( + &(port->port_status), + RTE_PORT_HANDLING, + RTE_PORT_STOPPED) == 0) + printf("Port %d can not be set " + "back to stopped\n", pi); + printf("Fail to configure port %d\n", + pi); + /* try to reconfigure port next time */ + port->need_reconfig = 1; + return -1; + } } } - if (port->need_reconfig_queues > 0) { + if (port->need_reconfig_queues > 0 && + rte_eal_process_type() == RTE_PROC_PRIMARY) { port->need_reconfig_queues = 0; /* setup tx queues */ for (qi = 0; qi < nb_txq; qi++) { @@ -2618,15 +2644,18 @@ start_port(portid_t pid) cnt_pi++; /* start port */ - if (rte_eth_dev_start(pi) < 0) { - printf("Fail to start port %d\n", pi); - - /* Fail to setup rx queue, return */ - if (rte_atomic16_cmpset(&(port->port_status), - RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) - printf("Port %d can not be set back to " - "stopped\n", pi); - continue; + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + diag = rte_eth_dev_start(pi); + if (diag < 0) { + printf("Fail to start port %d\n", pi); + + /* Fail to setup rx queue, return */ + if (rte_atomic16_cmpset(&(port->port_status), + RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) + printf("Port %d can not be set back to " + "stopped\n", pi); + continue; + } } if (rte_atomic16_cmpset(&(port->port_status), @@ -2755,7 +2784,7 @@ stop_port(portid_t pid) if (port->flow_list) port_flow_flush(pi); - if (rte_eth_dev_stop(pi) != 0) + if (rte_eal_process_type() == RTE_PROC_PRIMARY && rte_eth_dev_stop(pi) != 0) RTE_LOG(ERR, EAL, "rte_eth_dev_stop failed for port %u\n", pi); @@ -2824,8 +2853,10 @@ close_port(portid_t pid) continue; } - port_flow_flush(pi); - rte_eth_dev_close(pi); + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + port_flow_flush(pi); + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + rte_eth_dev_close(pi); } remove_invalid_ports(); @@ -3089,7 +3120,7 @@ pmd_test_exit(void) } } for (i = 0 ; i < RTE_DIM(mempools) ; i++) { - if (mempools[i]) + if (rte_eal_process_type() == RTE_PROC_PRIMARY && mempools[i]) rte_mempool_free(mempools[i]); } @@ -3537,6 +3568,10 @@ init_port_dcb_config(portid_t pid, int retval; uint16_t i; + if (num_procs > 1) { + printf("The multi-process feature doesn't support dcb.\n"); + return -ENOTSUP; + } rte_port = &ports[pid]; memset(&port_conf, 0, sizeof(struct rte_eth_conf)); @@ -3635,13 +3670,6 @@ init_port(void) } static void -force_quit(void) -{ - pmd_test_exit(); - prompt_exit(); -} - -static void print_stats(void) { uint8_t i; @@ -3672,12 +3700,16 @@ signal_handler(int signum) if (latencystats_enabled != 0) rte_latencystats_uninit(); #endif - force_quit(); /* Set flag to indicate the force termination. */ f_quit = 1; - /* exit with the expected status */ - signal(signum, SIG_DFL); - kill(getpid(), signum); + if (interactive == 1) { + dup2(testpmd_cl->s_in, testpmd_fd_copy); + close(testpmd_cl->s_in); + } else { + dup2(0, testpmd_fd_copy); + close(0); + } + } } @@ -3702,10 +3734,6 @@ main(int argc, char** argv) rte_exit(EXIT_FAILURE, "Cannot init EAL: %s\n", rte_strerror(rte_errno)); - if (rte_eal_process_type() == RTE_PROC_SECONDARY) - rte_exit(EXIT_FAILURE, - "Secondary process type not supported.\n"); - ret = register_eth_event_callback(); if (ret != 0) rte_exit(EXIT_FAILURE, "Cannot register for ethdev events"); @@ -3801,8 +3829,10 @@ main(int argc, char** argv) } } - if (!no_device_start && start_port(RTE_PORT_ALL) != 0) + if (!no_device_start && start_port(RTE_PORT_ALL) != 0) { + pmd_test_exit(); rte_exit(EXIT_FAILURE, "Start ports failed\n"); + } /* set all ports to promiscuous mode by default */ RTE_ETH_FOREACH_DEV(port_id) { @@ -3848,6 +3878,8 @@ main(int argc, char** argv) } prompt(); pmd_test_exit(); + if (unlikely(f_quit == 1)) + prompt_exit(); } else #endif { @@ -3883,6 +3915,11 @@ main(int argc, char** argv) printf("Press enter to exit\n"); rc = read(0, &c, 1); pmd_test_exit(); + if (unlikely(f_quit == 1)) { + dup2(testpmd_fd_copy, 0); + close(testpmd_fd_copy); + prompt_exit(); + } if (rc < 0) return 1; } diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index 5f23162..8629c57 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -13,6 +13,7 @@ #include <rte_gso.h> #include <cmdline.h> #include <sys/queue.h> +#include "cmdline.h" #define RTE_PORT_ALL (~(portid_t)0x0) @@ -24,6 +25,10 @@ #define RTE_PORT_CLOSED (uint16_t)2 #define RTE_PORT_HANDLING (uint16_t)3 +uint8_t f_quit; +int testpmd_fd_copy; +struct cmdline *testpmd_cl; + /* * It is used to allocate the memory for hash key. * The hash key size is NIC dependent. @@ -421,6 +426,8 @@ extern uint64_t noisy_lkup_mem_sz; extern uint64_t noisy_lkup_num_writes; extern uint64_t noisy_lkup_num_reads; extern uint64_t noisy_lkup_num_reads_writes; +extern int proc_id; +extern unsigned num_procs; extern uint8_t dcb_config; extern uint8_t dcb_test; -- 2.7.4

2 2

[PATCH 00/13] Features and bugfixes for hns3
by Lijun Ou 04 Mar '21

04 Mar '21

This series add three features according to the 21.05 roadmap as well as fix some bugs. Chengchang Tang (4): net/hns3: support module EEPROM dump net/hns3: add more registers to dump net/hns3: fix maximum frame size update after buffer alloc net/hns3: fix imprecise statistics Chengwen Feng (2): net/hns3: implement cleanup for Tx done net/hns3: support RXD advanced layout Hongbo Zheng (1): net/hns3: add process for MAC interrupt Huisong Li (4): net/hns3: encapsulate a port shaping interface net/hns3: support PF on electrical net device net/hns3: remove unused parameter from func declaration net/hns3: fix memory leakage for mbuf Min Hu (Connor) (2): net/hns3: add Rx and Tx bytes stats net/hns3: add imissed packet stats doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 5 + drivers/net/hns3/hns3_cmd.c | 8 +- drivers/net/hns3/hns3_cmd.h | 81 +++++++ drivers/net/hns3/hns3_dcb.c | 22 +- drivers/net/hns3/hns3_dcb.h | 2 +- drivers/net/hns3/hns3_ethdev.c | 420 +++++++++++++++++++++++++++++---- drivers/net/hns3/hns3_ethdev.h | 22 ++ drivers/net/hns3/hns3_ethdev_vf.c | 46 ++-- drivers/net/hns3/hns3_intr.c | 20 ++ drivers/net/hns3/hns3_intr.h | 4 + drivers/net/hns3/hns3_regs.c | 171 +++++++++++++- drivers/net/hns3/hns3_regs.h | 1 + drivers/net/hns3/hns3_rxtx.c | 283 ++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 12 + drivers/net/hns3/hns3_rxtx_vec_neon.h | 15 ++ drivers/net/hns3/hns3_rxtx_vec_sve.c | 11 + drivers/net/hns3/hns3_stats.c | 293 +++++++++++++---------- drivers/net/hns3/hns3_stats.h | 12 +- 20 files changed, 1232 insertions(+), 198 deletions(-) -- 2.7.4

3 66

[PATCH 0/4] Fix the parameter of dma_map_sg()
by chenxiang 04 Mar '21

04 Mar '21

From: Xiang Chen <chenxiang66(a)hisilicon.com> According to Documentation/core-api/dma-api-howto.rst, the parameters of dma_unmap_sg() must be the same as those which are passed in to the scatter/gather mapping API. But for some drivers under crypto, the <nents> parameter of dma_unmap_sg() is number of elements after mapping. So fix them. Part of the document is as follows: To unmap a scatterlist, just call:: dma_unmap_sg(dev, sglist, nents, direction); Again, make sure DMA activity has already finished. .. note:: The 'nents' argument to the dma_unmap_sg call must be the _same_ one you passed into the dma_map_sg call, it should _NOT_ be the 'count' value _returned_ from the dma_map_sg call. chenxiang (4): crypto: amlogic - Fix the parameter of dma_unmap_sg() crypto: cavium - Fix the parameter of dma_unmap_sg() crypto: ux500 - Fix the parameter of dma_unmap_sg() crypto: allwinner - Fix the parameter of dma_unmap_sg() drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c | 9 ++++++--- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c | 3 ++- drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c | 9 ++++++--- drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c | 3 ++- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 6 +++--- drivers/crypto/cavium/nitrox/nitrox_reqmgr.c | 8 ++++---- drivers/crypto/ux500/cryp/cryp_core.c | 4 ++-- drivers/crypto/ux500/hash/hash_core.c | 2 +- 8 files changed, 26 insertions(+), 18 deletions(-) -- 2.8.1

4 10

[PATCH for-next] RDMA/hns: Add support for XRC on HIP09
by Weihang Li 04 Mar '21

04 Mar '21

From: Wenpeng Liang <liangwenpeng(a)huawei.com> The HIP09 supports XRC transport service, it greatly saves the number of QPs required to connect all processes in a large cluster. Signed-off-by: Wenpeng Liang <liangwenpeng(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_alloc.c | 3 + drivers/infiniband/hw/hns/hns_roce_device.h | 25 +++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 147 +++++++++++++++++++--------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 2 + drivers/infiniband/hw/hns/hns_roce_main.c | 32 +++++- drivers/infiniband/hw/hns/hns_roce_pd.c | 51 ++++++++++ drivers/infiniband/hw/hns/hns_roce_qp.c | 63 ++++++++---- drivers/infiniband/hw/hns/hns_roce_srq.c | 3 + include/uapi/rdma/hns-abi.h | 2 + 9 files changed, 258 insertions(+), 70 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_alloc.c b/drivers/infiniband/hw/hns/hns_roce_alloc.c index 4bcaaa05..5d389ed 100644 --- a/drivers/infiniband/hw/hns/hns_roce_alloc.c +++ b/drivers/infiniband/hw/hns/hns_roce_alloc.c @@ -304,6 +304,9 @@ int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev) { + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + hns_roce_cleanup_xrcd_table(hr_dev); + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) hns_roce_cleanup_srq_table(hr_dev); hns_roce_cleanup_qp_table(hr_dev); diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 3d6b7a2d..f74db0f 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -137,6 +137,7 @@ enum { SERV_TYPE_UC, SERV_TYPE_RD, SERV_TYPE_UD, + SERV_TYPE_XRC = 5, }; enum hns_roce_qp_state { @@ -168,6 +169,8 @@ enum hns_roce_event { HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, HNS_ROCE_EVENT_TYPE_MB = 0x13, HNS_ROCE_EVENT_TYPE_FLR = 0x15, + HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, + HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, }; #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 @@ -179,6 +182,7 @@ enum { HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), HNS_ROCE_CAP_FLAG_SRQ = BIT(5), + HNS_ROCE_CAP_FLAG_XRC = BIT(6), HNS_ROCE_CAP_FLAG_MW = BIT(7), HNS_ROCE_CAP_FLAG_FRMR = BIT(8), HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), @@ -244,6 +248,11 @@ struct hns_roce_pd { unsigned long pdn; }; +struct hns_roce_xrcd { + struct ib_xrcd ibxrcd; + unsigned long xrcdn; +}; + struct hns_roce_bitmap { /* Bitmap Traversal last a bit which is 1 */ unsigned long last; @@ -467,6 +476,7 @@ struct hns_roce_srq { u32 rsv_sge; int wqe_shift; u32 cqn; + u32 xrcdn; void __iomem *db_reg_l; atomic_t refcount; @@ -640,6 +650,8 @@ struct hns_roce_qp { enum hns_roce_event event_type); unsigned long qpn; + unsigned long xrcdn; + atomic_t refcount; struct completion free; @@ -766,6 +778,8 @@ struct hns_roce_caps { int reserved_uars; int num_pds; int reserved_pds; + int num_xrcds; + int reserved_xrcds; u32 mtt_entry_sz; u32 cqe_sz; u32 page_size_cap; @@ -963,6 +977,7 @@ struct hns_roce_dev { struct hns_roce_cmdq cmd; struct hns_roce_bitmap pd_bitmap; + struct hns_roce_bitmap xrcd_bitmap; struct hns_roce_uar_table uar_table; struct hns_roce_mr_table mr_table; struct hns_roce_cq_table cq_table; @@ -1004,6 +1019,11 @@ static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) return container_of(ibpd, struct hns_roce_pd, ibpd); } +static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) +{ + return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); +} + static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) { return container_of(ibah, struct hns_roce_ah, ibah); @@ -1136,6 +1156,7 @@ int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); +int hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); @@ -1143,6 +1164,7 @@ void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); +void hns_roce_cleanup_xrcd_table(struct hns_roce_dev *hr_dev); int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, @@ -1207,6 +1229,9 @@ int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, struct ib_udata *udata); int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); +int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); +int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); + struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata); diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index c3934ab..593acf1 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1829,6 +1829,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; + caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; @@ -1846,6 +1847,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; caps->reserved_lkey = 0; caps->reserved_pds = 0; + caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; caps->reserved_mrws = 1; caps->reserved_uars = 0; caps->reserved_cqs = 0; @@ -1900,7 +1902,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | - HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; + HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC; caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; @@ -2131,6 +2133,8 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; caps->ceqe_size = HNS_ROCE_CEQE_SIZE; caps->aeqe_size = HNS_ROCE_AEQE_SIZE; + caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; + caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; caps->mtt_ba_pg_sz = 0; caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; @@ -3909,6 +3913,16 @@ static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, ilog2(hr_qp->rq.wqe_cnt)); } +static inline int get_cqn(struct ib_cq *ib_cq) +{ + return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; +} + +static inline int get_pdn(struct ib_pd *ib_pd) +{ + return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; +} + static void modify_qp_reset_to_init(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, @@ -3925,13 +3939,13 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, * 0 at the same time, else set them to 0x1. */ roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, - V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); + V2_QPC_BYTE_4_TST_S, to_hr_qp_type(ibqp->qp_type)); roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, - V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); + V2_QPC_BYTE_16_PD_S, get_pdn(ibqp->pd)); roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); @@ -3942,6 +3956,9 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); + if (ibqp->qp_type == IB_QPT_XRC_TGT) + context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); + if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) roce_set_bit(context->byte_68_rq_db, V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); @@ -3956,19 +3973,20 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, - V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); + V2_QPC_BYTE_80_RX_CQN_S, get_cqn(ibqp->recv_cq)); + if (ibqp->srq) { + roce_set_bit(context->byte_76_srqn_op_en, + V2_QPC_BYTE_76_SRQ_EN_S, 1); roce_set_field(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, to_hr_srq(ibqp->srq)->srqn); - roce_set_bit(context->byte_76_srqn_op_en, - V2_QPC_BYTE_76_SRQ_EN_S, 1); } roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1); roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, - V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); + V2_QPC_BYTE_252_TX_CQN_S, get_cqn(ibqp->send_cq)); if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) return; @@ -3991,22 +4009,28 @@ static void modify_qp_init_to_init(struct ib_qp *ibqp, * 0 at the same time, else set them to 0x1. */ roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, - V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); + V2_QPC_BYTE_4_TST_S, to_hr_qp_type(ibqp->qp_type)); roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, V2_QPC_BYTE_4_TST_S, 0); + if (ibqp->qp_type == IB_QPT_XRC_TGT) { + context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); + qpc_mask->qkey_xrcd = 0; + } + roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, - V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); + V2_QPC_BYTE_16_PD_S, get_pdn(ibqp->pd)); + roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, V2_QPC_BYTE_16_PD_S, 0); roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, - V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); + V2_QPC_BYTE_80_RX_CQN_S, get_cqn(ibqp->recv_cq)); roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, V2_QPC_BYTE_80_RX_CQN_S, 0); roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, - V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); + V2_QPC_BYTE_252_TX_CQN_S, get_cqn(ibqp->send_cq)); roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, V2_QPC_BYTE_252_TX_CQN_S, 0); @@ -4685,7 +4709,6 @@ static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, V2_QPC_BYTE_244_RNR_CNT_S, 0); } - /* RC&UC&UD required attr */ if (attr_mask & IB_QP_SQ_PSN) { roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, @@ -4763,7 +4786,6 @@ static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); } - /* RC&UC required attr */ if (attr_mask & IB_QP_RQ_PSN) { roce_set_field(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_RX_REQ_EPSN_M, @@ -4806,6 +4828,29 @@ static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, } } +static void clear_qp(struct hns_roce_qp *hr_qp) +{ + struct ib_qp *ibqp = &hr_qp->ibqp; + + if (ibqp->send_cq) + hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), + hr_qp->qpn, NULL); + + if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) + hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), + hr_qp->qpn, ibqp->srq ? + to_hr_srq(ibqp->srq) : NULL); + + if (hr_qp->rq.wqe_cnt) + *hr_qp->rdb.db_record = 0; + + hr_qp->rq.head = 0; + hr_qp->rq.tail = 0; + hr_qp->sq.head = 0; + hr_qp->sq.tail = 0; + hr_qp->next_sge = 0; +} + static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, enum ib_qp_state cur_state, @@ -4840,19 +4885,23 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, /* When QP state is err, SQ and RQ WQE should be flushed */ if (new_state == IB_QPS_ERR) { - spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); - hr_qp->state = IB_QPS_ERR; - roce_set_field(context->byte_160_sq_ci_pi, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, - hr_qp->sq.head); - roce_set_field(qpc_mask->byte_160_sq_ci_pi, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, - V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); - spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); - - if (!ibqp->srq) { + if (ibqp->qp_type != IB_QPT_XRC_TGT) { + spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); + hr_qp->state = IB_QPS_ERR; + roce_set_field(context->byte_160_sq_ci_pi, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, + hr_qp->sq.head); + roce_set_field(qpc_mask->byte_160_sq_ci_pi, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, + V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); + spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); + } + + if (!ibqp->srq && ibqp->qp_type != IB_QPT_XRC_INI && + ibqp->qp_type != IB_QPT_XRC_TGT) { spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); + hr_qp->state = IB_QPS_ERR; roce_set_field(context->byte_84_rq_ci_pi, V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, @@ -4871,7 +4920,8 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, goto out; roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, - ibqp->srq ? 1 : 0); + ((to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC) || + ibqp->srq) ? 1 : 0); roce_set_bit(qpc_mask->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, 0); @@ -4892,21 +4942,8 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); - if (new_state == IB_QPS_RESET && !ibqp->uobject) { - hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, - ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); - if (ibqp->send_cq != ibqp->recv_cq) - hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), - hr_qp->qpn, NULL); - - hr_qp->rq.head = 0; - hr_qp->rq.tail = 0; - hr_qp->sq.head = 0; - hr_qp->sq.tail = 0; - hr_qp->next_sge = 0; - if (hr_qp->rq.wqe_cnt) - *hr_qp->rdb.db_record = 0; - } + if (new_state == IB_QPS_RESET && !ibqp->uobject) + clear_qp(hr_qp); out: return ret; @@ -5017,7 +5054,9 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S); if (hr_qp->ibqp.qp_type == IB_QPT_RC || - hr_qp->ibqp.qp_type == IB_QPT_UC) { + hr_qp->ibqp.qp_type == IB_QPT_UC || + hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || + hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { struct ib_global_route *grh = rdma_ah_retrieve_grh(&qp_attr->ah_attr); @@ -5049,6 +5088,7 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, V2_QPC_BYTE_140_RR_MAX_S); + qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_MIN_RNR_TIME_M, V2_QPC_BYTE_80_MIN_RNR_TIME_S); @@ -5083,6 +5123,15 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, return ret; } +static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) +{ + return ((hr_qp->ibqp.qp_type == IB_QPT_RC || + hr_qp->ibqp.qp_type == IB_QPT_UD || + hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || + hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && + hr_qp->state != IB_QPS_RESET); +} + static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, struct ib_udata *udata) @@ -5092,9 +5141,7 @@ static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, unsigned long flags; int ret = 0; - if ((hr_qp->ibqp.qp_type == IB_QPT_RC || - hr_qp->ibqp.qp_type == IB_QPT_UD) && - hr_qp->state != IB_QPS_RESET) { + if (modify_qp_is_ok(hr_qp)) { /* Modify qp to reset before destroying qp */ ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET); @@ -5275,7 +5322,7 @@ static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) hr_reg_write(ctx, SRQC_SRQ_ST, 1); hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); hr_reg_write(ctx, SRQC_SRQN, srq->srqn); - hr_reg_write(ctx, SRQC_XRCD, 0); + hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); hr_reg_write(ctx, SRQC_RQWS, @@ -5479,6 +5526,12 @@ static void hns_roce_irq_work_handle(struct work_struct *work) case HNS_ROCE_EVENT_TYPE_FLR: ibdev_warn(ibdev, "Function level reset.\n"); break; + case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: + ibdev_err(ibdev, "xrc domain violation error.\n"); + break; + case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: + ibdev_err(ibdev, "invalid xrceth error.\n"); + break; default: break; } @@ -5579,6 +5632,8 @@ static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: + case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: + case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: hns_roce_qp_event(hr_dev, queue_num, event_type); break; case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 39621fb..ffdae15 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -74,6 +74,8 @@ #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 +#define HNS_ROCE_V2_MAX_XRCD_NUM 0x1000000 +#define HNS_ROCE_V2_RSV_XRCD_NUM 0 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c index c9c0836..1a747f7 100644 --- a/drivers/infiniband/hw/hns/hns_roce_main.c +++ b/drivers/infiniband/hw/hns/hns_roce_main.c @@ -207,6 +207,9 @@ static int hns_roce_query_device(struct ib_device *ib_dev, props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; } + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + props->device_cap_flags |= IB_DEVICE_XRC; + return 0; } @@ -300,6 +303,7 @@ static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, return -EAGAIN; resp.qp_tab_size = hr_dev->caps.num_qps; + resp.srq_tab_size = hr_dev->caps.num_srqs; ret = hns_roce_uar_alloc(hr_dev, &context->uar); if (ret) @@ -461,6 +465,13 @@ static const struct ib_device_ops hns_roce_dev_srq_ops = { INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), }; +static const struct ib_device_ops hns_roce_dev_xrcd_ops = { + .alloc_xrcd = hns_roce_alloc_xrcd, + .dealloc_xrcd = hns_roce_dealloc_xrcd, + + INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd), +}; + static int hns_roce_register_device(struct hns_roce_dev *hr_dev) { int ret; @@ -484,20 +495,20 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev) if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); - /* MW */ if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); - /* FRMR */ if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); - /* SRQ */ if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); } + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops); + ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); ib_set_device_ops(ib_dev, &hns_roce_dev_ops); for (i = 0; i < hr_dev->caps.num_ports; i++) { @@ -727,10 +738,19 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) goto err_uar_alloc_free; } + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) { + ret = hns_roce_init_xrcd_table(hr_dev); + if (ret) { + dev_err(dev, "failed to init xrcd table, ret = %d.\n", + ret); + goto err_pd_table_free; + } + } + ret = hns_roce_init_mr_table(hr_dev); if (ret) { dev_err(dev, "Failed to init memory region table.\n"); - goto err_pd_table_free; + goto err_xrcd_table_free; } hns_roce_init_cq_table(hr_dev); @@ -759,6 +779,10 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) hns_roce_cleanup_cq_table(hr_dev); hns_roce_cleanup_mr_table(hr_dev); +err_xrcd_table_free: + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) + hns_roce_cleanup_xrcd_table(hr_dev); + err_pd_table_free: hns_roce_cleanup_pd_table(hr_dev); diff --git a/drivers/infiniband/hw/hns/hns_roce_pd.c b/drivers/infiniband/hw/hns/hns_roce_pd.c index cca818d..9dbd21a 100644 --- a/drivers/infiniband/hw/hns/hns_roce_pd.c +++ b/drivers/infiniband/hw/hns/hns_roce_pd.c @@ -137,3 +137,54 @@ void hns_roce_cleanup_uar_table(struct hns_roce_dev *hr_dev) { hns_roce_bitmap_cleanup(&hr_dev->uar_table.bitmap); } + +static int hns_roce_xrcd_alloc(struct hns_roce_dev *hr_dev, + unsigned long *xrcdn) +{ + return hns_roce_bitmap_alloc(&hr_dev->xrcd_bitmap, xrcdn); +} + +static void hns_roce_xrcd_free(struct hns_roce_dev *hr_dev, + unsigned long xrcdn) +{ + hns_roce_bitmap_free(&hr_dev->xrcd_bitmap, xrcdn, BITMAP_NO_RR); +} + +int hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev) +{ + return hns_roce_bitmap_init(&hr_dev->xrcd_bitmap, + hr_dev->caps.num_xrcds, + hr_dev->caps.num_xrcds - 1, + hr_dev->caps.reserved_xrcds, 0); +} + +void hns_roce_cleanup_xrcd_table(struct hns_roce_dev *hr_dev) +{ + hns_roce_bitmap_cleanup(&hr_dev->xrcd_bitmap); +} + +int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata) +{ + struct hns_roce_dev *hr_dev = to_hr_dev(ib_xrcd->device); + struct hns_roce_xrcd *xrcd = to_hr_xrcd(ib_xrcd); + int ret; + + if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)) + return -EINVAL; + + ret = hns_roce_xrcd_alloc(hr_dev, &xrcd->xrcdn); + if (ret) { + dev_err(hr_dev->dev, "failed to alloc xrcdn, ret = %d.\n", ret); + return ret; + } + + return 0; +} + +int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata) +{ + hns_roce_xrcd_free(to_hr_dev(ib_xrcd->device), + to_hr_xrcd(ib_xrcd)->xrcdn); + + return 0; +} diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index 004aca9..9169225 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -98,7 +98,9 @@ void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 && (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR || event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR || - event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR)) { + event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR || + event_type == HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION || + event_type == HNS_ROCE_EVENT_TYPE_INVALID_XRCETH)) { qp->state = IB_QPS_ERR; if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) init_flush_work(hr_dev, qp); @@ -142,6 +144,8 @@ static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, event.event = IB_EVENT_QP_REQ_ERR; break; case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: + case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: + case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: event.event = IB_EVENT_QP_ACCESS_ERR; break; default: @@ -366,8 +370,13 @@ void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) unsigned long flags; list_del(&hr_qp->node); - list_del(&hr_qp->sq_node); - list_del(&hr_qp->rq_node); + + if (hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) + list_del(&hr_qp->sq_node); + + if (hr_qp->ibqp.qp_type != IB_QPT_XRC_INI && + hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) + list_del(&hr_qp->rq_node); xa_lock_irqsave(xa, flags); __xa_erase(xa, hr_qp->qpn & (hr_dev->caps.num_qps - 1)); @@ -1100,11 +1109,16 @@ static int check_qp_type(struct hns_roce_dev *hr_dev, enum ib_qp_type type, bool is_user) { switch (type) { + case IB_QPT_XRC_INI: + case IB_QPT_XRC_TGT: + if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)) + goto out; + break; case IB_QPT_UD: if (hr_dev->pci_dev->revision <= PCI_REVISION_ID_HIP08 && is_user) goto out; - fallthrough; + break; case IB_QPT_RC: case IB_QPT_GSI: break; @@ -1124,8 +1138,8 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata) { - struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); - struct ib_device *ibdev = &hr_dev->ib_dev; + struct ib_device *ibdev = pd ? pd->device : init_attr->xrcd->device; + struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); struct hns_roce_qp *hr_qp; int ret; @@ -1137,6 +1151,15 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, if (!hr_qp) return ERR_PTR(-ENOMEM); + if (init_attr->qp_type == IB_QPT_XRC_INI) + init_attr->recv_cq = NULL; + + if (init_attr->qp_type == IB_QPT_XRC_TGT) { + hr_qp->xrcdn = to_hr_xrcd(init_attr->xrcd)->xrcdn; + init_attr->recv_cq = NULL; + init_attr->send_cq = NULL; + } + if (init_attr->qp_type == IB_QPT_GSI) { hr_qp->port = init_attr->port_num - 1; hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; @@ -1156,20 +1179,20 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, int to_hr_qp_type(int qp_type) { - int transport_type; - - if (qp_type == IB_QPT_RC) - transport_type = SERV_TYPE_RC; - else if (qp_type == IB_QPT_UC) - transport_type = SERV_TYPE_UC; - else if (qp_type == IB_QPT_UD) - transport_type = SERV_TYPE_UD; - else if (qp_type == IB_QPT_GSI) - transport_type = SERV_TYPE_UD; - else - transport_type = -1; - - return transport_type; + switch (qp_type) { + case IB_QPT_RC: + return SERV_TYPE_RC; + case IB_QPT_UC: + return SERV_TYPE_UC; + case IB_QPT_UD: + case IB_QPT_GSI: + return SERV_TYPE_UD; + case IB_QPT_XRC_INI: + case IB_QPT_XRC_TGT: + return SERV_TYPE_XRC; + default: + return -1; + } } static int check_mtu_validate(struct hns_roce_dev *hr_dev, diff --git a/drivers/infiniband/hw/hns/hns_roce_srq.c b/drivers/infiniband/hw/hns/hns_roce_srq.c index d5a6de0..f71459a 100644 --- a/drivers/infiniband/hw/hns/hns_roce_srq.c +++ b/drivers/infiniband/hw/hns/hns_roce_srq.c @@ -314,6 +314,9 @@ static void set_srq_ext_param(struct hns_roce_srq *srq, { srq->cqn = ib_srq_has_cq(init_attr->srq_type) ? to_hr_cq(init_attr->ext.cq)->cqn : 0; + + srq->xrcdn = (init_attr->srq_type == IB_SRQT_XRC) ? + to_hr_xrcd(init_attr->ext.xrc.xrcd)->xrcdn : 0; } static int set_srq_param(struct hns_roce_srq *srq, diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h index 90b739d..42b1776 100644 --- a/include/uapi/rdma/hns-abi.h +++ b/include/uapi/rdma/hns-abi.h @@ -86,6 +86,8 @@ struct hns_roce_ib_create_qp_resp { struct hns_roce_ib_alloc_ucontext_resp { __u32 qp_tab_size; __u32 cqe_size; + __u32 srq_tab_size; + __u32 reserved; }; struct hns_roce_ib_alloc_pd_resp { -- 2.8.1

3 2

[PATCH rdma-core 0/5] libhns: Support XRC on HIP09
by Weihang Li 02 Mar '21

02 Mar '21

The HIP09 supports XRC transport service, it greatly saves the number of QPs required to connect all processes in a large cluster. This series first adds support of ibv_create_qp/srq_ex which are necessary interfaces for XRC, fixes an issue about CQ locks that is also required, then XRC is fully supported at last. Lang Cheng (1): libhns: Support ibv_create_qp_ex Weihang Li (2): Update kernel headers libhns: Avoid accessing NULL pointer when locking/unlocking CQ Wenpeng Liang (2): libhns: Support ibv_create_srq_ex libhns: Add support for XRC for HIP09 kernel-headers/rdma/hns-abi.h | 2 + providers/hns/hns_roce_u.c | 28 ++- providers/hns/hns_roce_u.h | 40 +++- providers/hns/hns_roce_u_abi.h | 11 +- providers/hns/hns_roce_u_hw_v1.c | 18 +- providers/hns/hns_roce_u_hw_v2.c | 159 +++++++++----- providers/hns/hns_roce_u_hw_v2.h | 1 + providers/hns/hns_roce_u_verbs.c | 455 +++++++++++++++++++++++++++++++-------- 8 files changed, 546 insertions(+), 168 deletions(-) -- 2.8.1

1 5

[PATCH v4] sched/topology: fix the issue groups don't span domain->span for NUMA diameter > 2
by Barry Song 02 Mar '21

02 Mar '21

As long as NUMA diameter > 2, building sched_domain by sibling's child domain will definitely create a sched_domain with sched_group which will span out of the sched_domain: +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 node2 node3 domain1 node0+1 node0+1 node2+3 node2+3 + domain2 node0+1+2 | group: node0+1 | group:node2+3 <-------------------+ when node2 is added into the domain2 of node0, kernel is using the child domain of node2's domain2, which is domain1(node2+3). Node 3 is outside the span of the domain including node0+1+2. This will make load_balance() run based on screwed avg_load and group_type in the sched_group spanning out of the sched_domain, and it also makes select_task_rq_fair() pick an idle CPU outside the sched_domain. Real servers which suffer from this problem include Kunpeng920 and 8-node Sun Fire X4600-M2, at least. Here we move to use the *child* domain of the *child* domain of node2's domain2 as the new added sched_group. At the same, we re-use the lower level sgc directly. +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 +- node2 node3 | domain1 node0+1 node0+1 | node2+3 node2+3 | domain2 node0+1+2 | group: node0+1 | group:node2 <-------------------+ While the lower level sgc is re-used, this patch only changes the remote sched_groups for those sched_domains playing grandchild trick, therefore, sgc->next_update is still safe since it's only touched by CPUs that have the group span as local group. And sgc->imbalance is also safe because sd_parent remains the same in load_balance and LB only tries other CPUs from the local group. Moreover, since local groups are not touched, they are still getting roughly equal size in a TL. And should_we_balance() only matters with local groups, so the pull probability of those groups are still roughly equal. Tested by the below topology: qemu-system-aarch64 -M virt -nographic \ -smp cpus=8 \ -numa node,cpus=0-1,nodeid=0 \ -numa node,cpus=2-3,nodeid=1 \ -numa node,cpus=4-5,nodeid=2 \ -numa node,cpus=6-7,nodeid=3 \ -numa dist,src=0,dst=1,val=12 \ -numa dist,src=0,dst=2,val=20 \ -numa dist,src=0,dst=3,val=22 \ -numa dist,src=1,dst=2,val=22 \ -numa dist,src=2,dst=3,val=12 \ -numa dist,src=1,dst=3,val=24 \ -m 4G -cpu cortex-a57 -kernel arch/arm64/boot/Image w/o patch, we get lots of "groups don't span domain->span": [ 0.802139] CPU0 attaching sched-domain(s): [ 0.802193] domain-0: span=0-1 level=MC [ 0.802443] groups: 0:{ span=0 cap=1013 }, 1:{ span=1 cap=979 } [ 0.802693] domain-1: span=0-3 level=NUMA [ 0.802731] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.802811] domain-2: span=0-5 level=NUMA [ 0.802829] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.802881] ERROR: groups don't span domain->span [ 0.803058] domain-3: span=0-7 level=NUMA [ 0.803080] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804055] CPU1 attaching sched-domain(s): [ 0.804072] domain-0: span=0-1 level=MC [ 0.804096] groups: 1:{ span=1 cap=979 }, 0:{ span=0 cap=1013 } [ 0.804152] domain-1: span=0-3 level=NUMA [ 0.804170] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.804219] domain-2: span=0-5 level=NUMA [ 0.804236] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.804302] ERROR: groups don't span domain->span [ 0.804520] domain-3: span=0-7 level=NUMA [ 0.804546] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804677] CPU2 attaching sched-domain(s): [ 0.804687] domain-0: span=2-3 level=MC [ 0.804705] groups: 2:{ span=2 cap=934 }, 3:{ span=3 cap=1009 } [ 0.804754] domain-1: span=0-3 level=NUMA [ 0.804772] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.804820] domain-2: span=0-5 level=NUMA [ 0.804836] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.804944] ERROR: groups don't span domain->span [ 0.805108] domain-3: span=0-7 level=NUMA [ 0.805134] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805223] CPU3 attaching sched-domain(s): [ 0.805232] domain-0: span=2-3 level=MC [ 0.805249] groups: 3:{ span=3 cap=1009 }, 2:{ span=2 cap=934 } [ 0.805319] domain-1: span=0-3 level=NUMA [ 0.805336] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.805383] domain-2: span=0-5 level=NUMA [ 0.805399] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.805458] ERROR: groups don't span domain->span [ 0.805605] domain-3: span=0-7 level=NUMA [ 0.805626] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805712] CPU4 attaching sched-domain(s): [ 0.805721] domain-0: span=4-5 level=MC [ 0.805738] groups: 4:{ span=4 cap=984 }, 5:{ span=5 cap=924 } [ 0.805787] domain-1: span=4-7 level=NUMA [ 0.805803] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.805851] domain-2: span=0-1,4-7 level=NUMA [ 0.805867] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.805915] ERROR: groups don't span domain->span [ 0.806108] domain-3: span=0-7 level=NUMA [ 0.806130] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.806214] CPU5 attaching sched-domain(s): [ 0.806222] domain-0: span=4-5 level=MC [ 0.806240] groups: 5:{ span=5 cap=924 }, 4:{ span=4 cap=984 } [ 0.806841] domain-1: span=4-7 level=NUMA [ 0.806866] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.806934] domain-2: span=0-1,4-7 level=NUMA [ 0.806953] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.807004] ERROR: groups don't span domain->span [ 0.807312] domain-3: span=0-7 level=NUMA [ 0.807386] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.807686] CPU6 attaching sched-domain(s): [ 0.807710] domain-0: span=6-7 level=MC [ 0.807750] groups: 6:{ span=6 cap=1017 }, 7:{ span=7 cap=1012 } [ 0.807840] domain-1: span=4-7 level=NUMA [ 0.807870] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.807952] domain-2: span=0-1,4-7 level=NUMA [ 0.807985] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.808045] ERROR: groups don't span domain->span [ 0.808257] domain-3: span=0-7 level=NUMA [ 0.808571] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6125 }, 2:{ span=0-5 mask=2-3 cap=5899 } [ 0.808848] CPU7 attaching sched-domain(s): [ 0.808860] domain-0: span=6-7 level=MC [ 0.808880] groups: 7:{ span=7 cap=1012 }, 6:{ span=6 cap=1017 } [ 0.808953] domain-1: span=4-7 level=NUMA [ 0.808974] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.809034] domain-2: span=0-1,4-7 level=NUMA [ 0.809055] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.809128] ERROR: groups don't span domain->span [ 0.810361] domain-3: span=0-7 level=NUMA [ 0.810400] groups: 6:{ span=0-1,4-7 mask=6-7 cap=5961 }, 2:{ span=0-5 mask=2-3 cap=5903 } w/ patch, we don't get "groups don't span domain->span" any more: [ 1.486271] CPU0 attaching sched-domain(s): [ 1.486820] domain-0: span=0-1 level=MC [ 1.500924] groups: 0:{ span=0 cap=980 }, 1:{ span=1 cap=994 } [ 1.515717] domain-1: span=0-3 level=NUMA [ 1.515903] groups: 0:{ span=0-1 cap=1974 }, 2:{ span=2-3 cap=1989 } [ 1.516989] domain-2: span=0-5 level=NUMA [ 1.517124] groups: 0:{ span=0-3 cap=3963 }, 4:{ span=4-5 cap=1949 } [ 1.517369] domain-3: span=0-7 level=NUMA [ 1.517423] groups: 0:{ span=0-5 mask=0-1 cap=5912 }, 6:{ span=4-7 mask=6-7 cap=4054 } [ 1.520027] CPU1 attaching sched-domain(s): [ 1.520097] domain-0: span=0-1 level=MC [ 1.520184] groups: 1:{ span=1 cap=994 }, 0:{ span=0 cap=980 } [ 1.520429] domain-1: span=0-3 level=NUMA [ 1.520487] groups: 0:{ span=0-1 cap=1974 }, 2:{ span=2-3 cap=1989 } [ 1.520687] domain-2: span=0-5 level=NUMA [ 1.520744] groups: 0:{ span=0-3 cap=3963 }, 4:{ span=4-5 cap=1949 } [ 1.520948] domain-3: span=0-7 level=NUMA [ 1.521038] groups: 0:{ span=0-5 mask=0-1 cap=5912 }, 6:{ span=4-7 mask=6-7 cap=4054 } [ 1.522068] CPU2 attaching sched-domain(s): [ 1.522348] domain-0: span=2-3 level=MC [ 1.522606] groups: 2:{ span=2 cap=1003 }, 3:{ span=3 cap=986 } [ 1.522832] domain-1: span=0-3 level=NUMA [ 1.522885] groups: 2:{ span=2-3 cap=1989 }, 0:{ span=0-1 cap=1974 } [ 1.523043] domain-2: span=0-5 level=NUMA [ 1.523092] groups: 2:{ span=0-3 mask=2-3 cap=4037 }, 4:{ span=4-5 cap=1949 } [ 1.523302] domain-3: span=0-7 level=NUMA [ 1.523352] groups: 2:{ span=0-5 mask=2-3 cap=5986 }, 6:{ span=0-1,4-7 mask=6-7 cap=6102 } [ 1.523748] CPU3 attaching sched-domain(s): [ 1.523774] domain-0: span=2-3 level=MC [ 1.523825] groups: 3:{ span=3 cap=986 }, 2:{ span=2 cap=1003 } [ 1.524009] domain-1: span=0-3 level=NUMA [ 1.524086] groups: 2:{ span=2-3 cap=1989 }, 0:{ span=0-1 cap=1974 } [ 1.524281] domain-2: span=0-5 level=NUMA [ 1.524331] groups: 2:{ span=0-3 mask=2-3 cap=4037 }, 4:{ span=4-5 cap=1949 } [ 1.524534] domain-3: span=0-7 level=NUMA [ 1.524586] groups: 2:{ span=0-5 mask=2-3 cap=5986 }, 6:{ span=0-1,4-7 mask=6-7 cap=6102 } [ 1.524847] CPU4 attaching sched-domain(s): [ 1.524873] domain-0: span=4-5 level=MC [ 1.524954] groups: 4:{ span=4 cap=958 }, 5:{ span=5 cap=991 } [ 1.525105] domain-1: span=4-7 level=NUMA [ 1.525153] groups: 4:{ span=4-5 cap=1949 }, 6:{ span=6-7 cap=2006 } [ 1.525368] domain-2: span=0-1,4-7 level=NUMA [ 1.525428] groups: 4:{ span=4-7 cap=3955 }, 0:{ span=0-1 cap=1974 } [ 1.532726] domain-3: span=0-7 level=NUMA [ 1.532811] groups: 4:{ span=0-1,4-7 mask=4-5 cap=6003 }, 2:{ span=0-3 mask=2-3 cap=4037 } [ 1.534125] CPU5 attaching sched-domain(s): [ 1.534159] domain-0: span=4-5 level=MC [ 1.534303] groups: 5:{ span=5 cap=991 }, 4:{ span=4 cap=958 } [ 1.534490] domain-1: span=4-7 level=NUMA [ 1.534572] groups: 4:{ span=4-5 cap=1949 }, 6:{ span=6-7 cap=2006 } [ 1.534734] domain-2: span=0-1,4-7 level=NUMA [ 1.534783] groups: 4:{ span=4-7 cap=3955 }, 0:{ span=0-1 cap=1974 } [ 1.536057] domain-3: span=0-7 level=NUMA [ 1.536430] groups: 4:{ span=0-1,4-7 mask=4-5 cap=6003 }, 2:{ span=0-3 mask=2-3 cap=3896 } [ 1.536815] CPU6 attaching sched-domain(s): [ 1.536846] domain-0: span=6-7 level=MC [ 1.536934] groups: 6:{ span=6 cap=1005 }, 7:{ span=7 cap=1001 } [ 1.537144] domain-1: span=4-7 level=NUMA [ 1.537262] groups: 6:{ span=6-7 cap=2006 }, 4:{ span=4-5 cap=1949 } [ 1.537553] domain-2: span=0-1,4-7 level=NUMA [ 1.537613] groups: 6:{ span=4-7 mask=6-7 cap=4054 }, 0:{ span=0-1 cap=1805 } [ 1.537872] domain-3: span=0-7 level=NUMA [ 1.537998] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6102 }, 2:{ span=0-5 mask=2-3 cap=5845 } [ 1.538448] CPU7 attaching sched-domain(s): [ 1.538505] domain-0: span=6-7 level=MC [ 1.538586] groups: 7:{ span=7 cap=1001 }, 6:{ span=6 cap=1005 } [ 1.538746] domain-1: span=4-7 level=NUMA [ 1.538798] groups: 6:{ span=6-7 cap=2006 }, 4:{ span=4-5 cap=1949 } [ 1.539048] domain-2: span=0-1,4-7 level=NUMA [ 1.539111] groups: 6:{ span=4-7 mask=6-7 cap=4054 }, 0:{ span=0-1 cap=1805 } [ 1.539571] domain-3: span=0-7 level=NUMA [ 1.539610] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6102 }, 2:{ span=0-5 mask=2-3 cap=5845 } Reported-by: Valentin Schneider <valentin.schneider(a)arm.com> Tested-by: Meelis Roos <mroos(a)linux.ee> Reviewed-by: Valentin Schneider <valentin.schneider(a)arm.com> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- -v4: no code changed; mainly rewrote changelog: * add Reviewed-by of Valentin; While the grandchild approach was started by me, Valentin contributed the most useful edit; * add description about sgc->imbalance and next_update according to the comment of Vincent; * add description about the equal size of local group to address Peter's comment kernel/sched/topology.c | 91 +++++++++++++++++++++++++++-------------- 1 file changed, 61 insertions(+), 30 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 09d35044bd88..12f80587e127 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -723,35 +723,6 @@ cpu_attach_domain(struct sched_domain *sd, struct root_domain *rd, int cpu) for (tmp = sd; tmp; tmp = tmp->parent) numa_distance += !!(tmp->flags & SD_NUMA); - /* - * FIXME: Diameter >=3 is misrepresented. - * - * Smallest diameter=3 topology is: - * - * node 0 1 2 3 - * 0: 10 20 30 40 - * 1: 20 10 20 30 - * 2: 30 20 10 20 - * 3: 40 30 20 10 - * - * 0 --- 1 --- 2 --- 3 - * - * NUMA-3 0-3 N/A N/A 0-3 - * groups: {0-2},{1-3} {1-3},{0-2} - * - * NUMA-2 0-2 0-3 0-3 1-3 - * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} - * - * NUMA-1 0-1 0-2 1-3 2-3 - * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} - * - * NUMA-0 0 1 2 3 - * - * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the - * group span isn't a subset of the domain span. - */ - WARN_ONCE(numa_distance > 2, "Shortest NUMA path spans too many nodes\n"); - sched_domain_debug(sd, cpu); rq_attach_root(rq, rd); @@ -982,6 +953,31 @@ static void init_overlap_sched_group(struct sched_domain *sd, sg->sgc->max_capacity = SCHED_CAPACITY_SCALE; } +static struct sched_domain * +find_descended_sibling(struct sched_domain *sd, struct sched_domain *sibling) +{ + /* + * The proper descendant would be the one whose child won't span out + * of sd + */ + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + sched_domain_span(sd))) + sibling = sibling->child; + + /* + * As we are referencing sgc across different topology level, we need + * to go down to skip those sched_domains which don't contribute to + * scheduling because they will be degenerated in cpu_attach_domain + */ + while (sibling->child && + cpumask_equal(sched_domain_span(sibling->child), + sched_domain_span(sibling))) + sibling = sibling->child; + + return sibling; +} + static int build_overlap_sched_groups(struct sched_domain *sd, int cpu) { @@ -1015,6 +1011,41 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) if (!cpumask_test_cpu(i, sched_domain_span(sibling))) continue; + /* + * Usually we build sched_group by sibling's child sched_domain + * But for machines whose NUMA diameter are 3 or above, we move + * to build sched_group by sibling's proper descendant's child + * domain because sibling's child sched_domain will span out of + * the sched_domain being built as below. + * + * Smallest diameter=3 topology is: + * + * node 0 1 2 3 + * 0: 10 20 30 40 + * 1: 20 10 20 30 + * 2: 30 20 10 20 + * 3: 40 30 20 10 + * + * 0 --- 1 --- 2 --- 3 + * + * NUMA-3 0-3 N/A N/A 0-3 + * groups: {0-2},{1-3} {1-3},{0-2} + * + * NUMA-2 0-2 0-3 0-3 1-3 + * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} + * + * NUMA-1 0-1 0-2 1-3 2-3 + * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} + * + * NUMA-0 0 1 2 3 + * + * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the + * group span isn't a subset of the domain span. + */ + if (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), span)) + sibling = find_descended_sibling(sd, sibling); + sg = build_group_from_child_sched_domain(sibling, cpu); if (!sg) goto fail; @@ -1022,7 +1053,7 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) sg_span = sched_group_span(sg); cpumask_or(covered, covered, sg_span); - init_overlap_sched_group(sd, sg); + init_overlap_sched_group(sibling, sg); if (!first) first = sg; -- 2.25.1

2 1

[RFC net-next 0/9] net: hns3: refactor and new features for flow director
by Huazhong Tan 02 Mar '21

02 Mar '21

This patchset refactor some functions and add some new features for flow director. patch 1~3: refactor large functions patch 4, 7: add traffic class and user-def field support for ethtool patch 5: use asynchronously configuration patch 6: clean up for hns3_del_all_fd_entries() patch 8, 9: add support for queue bonding mode Jian Shen (9): net: hns3: refactor out hclge_add_fd_entry() net: hns3: refactor out hclge_fd_get_tuple() net: hns3: refactor for function hclge_fd_convert_tuple net: hns3: add support for traffic class tuple support for flow director by ethtool net: hns3: refactor flow director configuration net: hns3: refine for hns3_del_all_fd_entries() net: hns3: add support for user-def data of flow director net: hns3: add support for queue bonding mode of flow director net: hns3: add queue bonding mode support for VF drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h | 8 + drivers/net/ethernet/hisilicon/hns3/hnae3.h | 9 +- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 4 +- drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 91 +- drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 14 +- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 13 +- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 2 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 21 + .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 1564 ++++++++++++++------ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 63 + .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 2 + .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 74 + .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 7 + .../ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c | 16 + 14 files changed, 1407 insertions(+), 481 deletions(-) -- 2.7.4

1 9

[PATCH V2 net] net: phy: fix save wrong speed and duplex problem if autoneg is on
by Huazhong Tan 02 Mar '21

02 Mar '21

From: Guangbin Huang <huangguangbin2(a)huawei.com> If phy uses generic driver and autoneg is on, enter command "ethtool -s eth0 speed 50" will not change phy speed actually, but command "ethtool eth0" shows speed is 50Mb/s because phydev->speed has been set to 50 and no update later. And duplex setting has same problem too. However, if autoneg is on, phy only changes speed and duplex according to phydev->advertising, but not phydev->speed and phydev->duplex. So in this case, phydev->speed and phydev->duplex don't need to be set in function phy_ethtool_ksettings_set() if autoneg is on. Fixes: 51e2a3846eab ("PHY: Avoid unnecessary aneg restarts") Signed-off-by: Guangbin Huang <huangguangbin2(a)huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong(a)huawei.com> --- V1->V2: add a Fixes tag --- drivers/net/phy/phy.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 1be07e4..fc2e7cb 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -276,14 +276,16 @@ int phy_ethtool_ksettings_set(struct phy_device *phydev, phydev->autoneg = autoneg; - phydev->speed = speed; + if (autoneg == AUTONEG_DISABLE) { + phydev->speed = speed; + phydev->duplex = duplex; + } linkmode_copy(phydev->advertising, advertising); linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising, autoneg == AUTONEG_ENABLE); - phydev->duplex = duplex; phydev->master_slave_set = cmd->base.master_slave_cfg; phydev->mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; -- 2.7.4

2 1

[PATCH 5.4 178/340] perf vendor events arm64: Fix Ampere eMag event typo
by Greg Kroah-Hartman 02 Mar '21

02 Mar '21

From: John Garry <john.garry(a)huawei.com> [ Upstream commit 2bf797be81fa808f05f1a7a65916619132256a27 ] The "briefdescription" for event 0x35 has a typo - fix it. Fixes: d35c595bf005 ("perf vendor events arm64: Revise core JSON events for eMAG") Signed-off-by: John Garry <john.garry(a)huawei.com> Acked-by: Will Deacon <will(a)kernel.org> Cc: James Clark <james.clark(a)arm.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Nakamura, Shunsuke/中村俊介 <nakamura.shun(a)fujitsu.com> Cc: linux-arm-kernel(a)lists.infradead.org Cc: linuxarm(a)openeuler.org Link: https://lore.kernel.org/r/1611835236-34696-2-git-send-email-john.garry@huaw… Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json index df9201434cb6a..b0a10a219b50d 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json @@ -114,7 +114,7 @@ "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count", "EventCode": "0x35", "EventName": "L2I_TLB_ACCESS", - "BriefDescription": "L2D TLB access" + "BriefDescription": "L2I TLB access" }, { "PublicDescription": "Branch target buffer misprediction", -- 2.27.0

1 0

[PATCH 5.10 344/663] perf vendor events arm64: Fix Ampere eMag event typo
by Greg Kroah-Hartman 02 Mar '21

02 Mar '21

From: John Garry <john.garry(a)huawei.com> [ Upstream commit 2bf797be81fa808f05f1a7a65916619132256a27 ] The "briefdescription" for event 0x35 has a typo - fix it. Fixes: d35c595bf005 ("perf vendor events arm64: Revise core JSON events for eMAG") Signed-off-by: John Garry <john.garry(a)huawei.com> Acked-by: Will Deacon <will(a)kernel.org> Cc: James Clark <james.clark(a)arm.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Nakamura, Shunsuke/中村俊介 <nakamura.shun(a)fujitsu.com> Cc: linux-arm-kernel(a)lists.infradead.org Cc: linuxarm(a)openeuler.org Link: https://lore.kernel.org/r/1611835236-34696-2-git-send-email-john.garry@huaw… Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json index 40010a8724b3a..ce6e7e7960579 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json @@ -114,7 +114,7 @@ "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count", "EventCode": "0x35", "EventName": "L2I_TLB_ACCESS", - "BriefDescription": "L2D TLB access" + "BriefDescription": "L2I TLB access" }, { "PublicDescription": "Branch target buffer misprediction", -- 2.27.0

1 0

[PATCH 5.11 415/775] perf vendor events arm64: Fix Ampere eMag event typo
by Greg Kroah-Hartman 02 Mar '21

02 Mar '21

From: John Garry <john.garry(a)huawei.com> [ Upstream commit 2bf797be81fa808f05f1a7a65916619132256a27 ] The "briefdescription" for event 0x35 has a typo - fix it. Fixes: d35c595bf005 ("perf vendor events arm64: Revise core JSON events for eMAG") Signed-off-by: John Garry <john.garry(a)huawei.com> Acked-by: Will Deacon <will(a)kernel.org> Cc: James Clark <james.clark(a)arm.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Nakamura, Shunsuke/中村俊介 <nakamura.shun(a)fujitsu.com> Cc: linux-arm-kernel(a)lists.infradead.org Cc: linuxarm(a)openeuler.org Link: https://lore.kernel.org/r/1611835236-34696-2-git-send-email-john.garry@huaw… Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json index 40010a8724b3a..ce6e7e7960579 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json @@ -114,7 +114,7 @@ "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count", "EventCode": "0x35", "EventName": "L2I_TLB_ACCESS", - "BriefDescription": "L2D TLB access" + "BriefDescription": "L2I TLB access" }, { "PublicDescription": "Branch target buffer misprediction", -- 2.27.0

1 0

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01 Mar '21

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1 0

[RESEND net 0/3] net: hns3: fixes fot -net
by Huazhong Tan 01 Mar '21

01 Mar '21

The patchset includes some fixes for the HNS3 ethernet driver. Jian Shen (3): net: hns3: fix error mask definition of flow director net: hns3: fix query vlan mask value error for flow director net: hns3: fix bug when calculating the TCAM table info drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 6 +++--- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 7 +++---- 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.7.4

2 4

DPDK 21.05 Huawei hns3 Roadmap
by oulijun 01 Mar '21

01 Mar '21

Hi， Following are the work items of hns3 PMD planned for 21.05, Some features are delayed to the current releases. New features: 【1】 Add PTP(Precise Time Protocol) support 【2】 Add query optical module info by API 【3】 Support LSC(Link Status Changed) event The LSC reporting function of the PF has been completed in 21.02. This task involves the LSC reporting function of the VF and the LSC capability setting through the rte_pci_drvier.drv_flags. 【4】 Implement tx_done_cleanup API 【5】 Implement Rx/Tx descriptor status API 【6】 Support runtime config for selecting Tx/Rx function 【7】 Kunpeng930 support electrical port 【8】 Kunpeng930 support flow control auto-negotiation 【9】 Kunpeng930 support for simple BD mode for Tx checksum 【10】 Kunpeng930 Support link speed configuration for PF 【11】 Support new RAS mechanism for Kunpeng930 Enhanced functionality: 【11】 Extend the DPDK stats 【12】 Extend the DPDK rte_dev_get_regs API implementation for query more common register information 【13】 Extend outer UDP cksum offload 【14】 Rx receive function optimization for improving performance support rxd advanced layout support checksum simple computing and ptype optimization 【15】 Support push mode for Tx queue bonding function：【16】 some bonding modes support prepare API testpmd updates：【17】 testpmd support multi-process test Others：【18】 Extend for hns3 document Thanks Lijun Ou

2 1

[PATCH v1] drm/nouveau/device: append a NUL-terminated character for the string which filled by strncpy()
by Luo Jiaxing 27 Feb '21

27 Feb '21

Following warning is found when using W=1 to build kernel: In function ‘nvkm_udevice_info’, inlined from ‘nvkm_udevice_mthd’ at drivers/gpu/drm/nouveau/nvkm/engine/device/user.c:195:10: drivers/gpu/drm/nouveau/nvkm/engine/device/user.c:164:2: warning: ‘strncpy’ specified bound 16 equals destination size [-Wstringop-truncation] 164 | strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip)); drivers/gpu/drm/nouveau/nvkm/engine/device/user.c:165:2: warning: ‘strncpy’ specified bound 64 equals destination size [-Wstringop-truncation] 165 | strncpy(args->v0.name, device->name, sizeof(args->v0.name)); The reason of this warning is strncpy() does not guarantee that the destination buffer will be NUL terminated. If the length of source string is bigger than number we set by third input parameter, only first [number] of characters is copied to the destination, and no NUL-terminated is automatically added. There are some potential risks. Signed-off-by: Luo Jiaxing <luojiaxing(a)huawei.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index fea9d8f..2a32fe0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -161,8 +161,10 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size) if (imem && args->v0.ram_size > 0) args->v0.ram_user = args->v0.ram_user - imem->reserved; - strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip)); - strncpy(args->v0.name, device->name, sizeof(args->v0.name)); + strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip) - 1); + args->v0.chip[sizeof(args->v0.chip) - 1] = '\0'; + strncpy(args->v0.name, device->name, sizeof(args->v0.name) - 1); + args->v0.name[sizeof(args->v0.name) - 1] = '\0'; return 0; } -- 2.7.4

3 2

[PATCH net 0/3] net: hns3: fixes fot -net
by Huazhong Tan 27 Feb '21

27 Feb '21

The patchset includes some fixes for the HNS3 ethernet driver. Jian Shen (3): net: hns3: fix error mask definition of flow director net: hns3: fix query vlan mask value error for flow director net: hns3: fix bug when calculating the TCAM table info drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 6 +++--- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 7 +++---- 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.7.4

1 4

Re: [PATCH 1/2] config/arm: fix Hisilicon kunpeng920 SoC build
by Thierry Herbelot 25 Feb '21

25 Feb '21

> Message: 4 > Date: Wed, 24 Feb 2021 11:24:27 +0100 > From: Thomas Monjalon <thomas(a)monjalon.net> > To: oulijun <oulijun(a)huawei.com> > Cc: ferruh.yigit(a)intel.com, dev(a)dpdk.org, linuxarm(a)openeuler.org, > juraj.linkes(a)pantheon.tech, bruce.richardson(a)intel.com > Subject: Re: [dpdk-dev] [PATCH 1/2] config/arm: fix Hisilicon > kunpeng920 SoC build > Message-ID: <5309744.5Ik2CEZAj8@thomas> > Content-Type: text/plain; charset="UTF-8" > > 24/02/2021 10:17, oulijun: >> >> ? 2021/2/24 15:41, Thomas Monjalon ??: >>> 24/02/2021 02:34, oulijun: >>>> >>>> ? 2021/2/10 17:41, Thomas Monjalon ??: >>>>> 03/02/2021 13:46, Lijun Ou: >>>>>> From: Chengchang Tang <tangchengchang(a)huawei.com> >>>>>> >>>>>> Because of the '9ca2f16' have merged, the current hns3 >>>>>> pmd driver can not be directly complied on the kunpeng920 >>>>>> server board. Therefore, we need to fix the meson build. >>>>>> Besides, add kunpeng 920 SoC meson cross compile target. >>>>>> >>>>>> Fixes: 9ca2f16faa7f ("config/arm: isolate generic build") >>>>> >>>>> Why do you think this patch is fixing the one above? >>>>> It looks just a new config, not a fix. Am I missing something? >>>>> >>>> I'm sorry to see you so late. In the meantime, we are celebrating the >>>> Spring Festival. This patch fixes the problem. If the patch is not >>>> added, the latest version cannot be directly compiled on the Kunpeng 930 >>>> server board.In addition, the cross compilation configuration file is added. >>> >>> Please can you explain what was removed which breaks your compilation? >>> >> I understand that implementation_id is identified in 9ca2f16. If the >> configuration file does not contain implementation_id, it will be >> displayed as unsupported. >> >> The error as follows: >> config/arm/meson.build:227:2: ERROR: Problem encountered: Unsupported >> Arm implementer: 0x48. Please add support for it or use the generic >> (-Dmachine=generic) build. >> >> Besides, we use the -Dmachine=generic, the bug is not resolved. >> the cmd as: >> meson build or meson -Dmachine=generic build > > What is the result of a generic build? Hello, Following dpdk commit 91c730fd4e093cd, the generic compilation for Arm is selected with '-Dmachine=default' The comments in config/arm/meson.build should be updated to follow the change in default machine name: https://git.dpdk.org/dpdk/tree/config/arm/meson.build#n241 https://git.dpdk.org/dpdk/tree/config/arm/meson.build#n256 Regards Thierry > >

3 3

[PATCH v1] drm/nouveau: delete unused variables "dev" in nouveau_ttm_tt_populate()
by Luo Jiaxing 25 Feb '21

25 Feb '21

After switch to new allocator, dev is no longer used here and should be deleted. Fixes: 461619f5c324 ("drm/nouveau: switch to new allocator") Signed-off-by: Luo Jiaxing <luojiaxing(a)huawei.com> --- drivers/gpu/drm/nouveau/nouveau_bo.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 2375711..0b94f8a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1251,7 +1251,6 @@ nouveau_ttm_tt_populate(struct ttm_bo_device *bdev, { struct ttm_tt *ttm_dma = (void *)ttm; struct nouveau_drm *drm; - struct device *dev; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); if (ttm_tt_is_populated(ttm)) @@ -1264,7 +1263,6 @@ nouveau_ttm_tt_populate(struct ttm_bo_device *bdev, } drm = nouveau_bdev(bdev); - dev = drm->dev->dev; return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx); } @@ -1274,14 +1272,12 @@ nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm) { struct nouveau_drm *drm; - struct device *dev; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); if (slave) return; drm = nouveau_bdev(bdev); - dev = drm->dev->dev; return ttm_pool_free(&drm->ttm.bdev.pool, ttm); } -- 2.7.4

1 0

[PATCH v1] drm/nouveau/kms: delete an useless function call in nouveau_framebuffer_new()
by Luo Jiaxing 25 Feb '21

25 Feb '21

nouveau_framebuffer_new() call drm_format_info_plane_width() to get a width of plane, but width is not used then, so it's a useless function call here. Signed-off-by: Luo Jiaxing <luojiaxing(a)huawei.com> --- drivers/gpu/drm/nouveau/nouveau_display.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 17831ee..7d3b1f8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -306,7 +306,7 @@ nouveau_framebuffer_new(struct drm_device *dev, struct nouveau_bo *nvbo = nouveau_gem_object(gem); struct drm_framebuffer *fb; const struct drm_format_info *info; - unsigned int width, height, i; + unsigned int height, i; uint32_t tile_mode; uint8_t kind; int ret; @@ -346,9 +346,6 @@ nouveau_framebuffer_new(struct drm_device *dev, info = drm_get_format_info(dev, mode_cmd); for (i = 0; i < info->num_planes; i++) { - width = drm_format_info_plane_width(info, - mode_cmd->width, - i); height = drm_format_info_plane_height(info, mode_cmd->height, i); -- 2.7.4

1 0

[PATCH v1 1/2] drm/nouveau/kms/nv50-: Remove several set but not used variables "ret" in disp.c
by Luo Jiaxing 25 Feb '21

25 Feb '21

Fixes the following warning when using W=1 to build kernel: drivers/gpu/drm/nouveau/dispnv50/disp.c: In function ‘nv50_mstm_cleanup’: drivers/gpu/drm/nouveau/dispnv50/disp.c:1389:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] 1389 | int ret; | ^~~ drivers/gpu/drm/nouveau/dispnv50/disp.c: In function ‘nv50_mstm_prepare’: drivers/gpu/drm/nouveau/dispnv50/disp.c:1413:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] 1413 | int ret; | ^~~ Signed-off-by: Luo Jiaxing <luojiaxing(a)huawei.com> --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 196612a..828f48d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1386,12 +1386,11 @@ nv50_mstm_cleanup(struct nv50_mstm *mstm) { struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); struct drm_encoder *encoder; - int ret; NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); - ret = drm_dp_check_act_status(&mstm->mgr); + drm_dp_check_act_status(&mstm->mgr); - ret = drm_dp_update_payload_part2(&mstm->mgr); + drm_dp_update_payload_part2(&mstm->mgr); drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { @@ -1410,10 +1409,9 @@ nv50_mstm_prepare(struct nv50_mstm *mstm) { struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); struct drm_encoder *encoder; - int ret; NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); - ret = drm_dp_update_payload_part1(&mstm->mgr); + drm_dp_update_payload_part1(&mstm->mgr); drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { -- 2.7.4

1 0

[PATCH for-next 00/32] spin lock usage optimization for SCSI drivers
by Xiaofei Tan 25 Feb '21

25 Feb '21

Replace spin_lock_irqsave with spin_lock in hard IRQ of SCSI drivers. There are no function changes, but may speed up if interrupt happen too often. Xiaofei Tan (32): scsi: 53c700: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ipr: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: lpfc: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qla4xxx: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: BusLogic: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a100u2w: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a2091: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a3000: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: aha1740: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: bfa: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: esp_scsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: gvp11: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: hptiop: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ibmvscsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: initio: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: megaraid: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mac53c94: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mesh: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mvumi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: myrb: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: myrs: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ncr53c8xx: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: nsp32: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: pmcraid: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: pcmcia: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qlogicfas408: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qlogicpti: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: sgiwd93: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: stex: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: vmw_pvscsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: wd719x: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: advansys: Replace spin_lock_irqsave with spin_lock in hard IRQ drivers/scsi/53c700.c | 5 ++-- drivers/scsi/BusLogic.c | 5 ++-- drivers/scsi/a100u2w.c | 5 ++-- drivers/scsi/a2091.c | 5 ++-- drivers/scsi/a3000.c | 5 ++-- drivers/scsi/advansys.c | 5 ++-- drivers/scsi/aha1740.c | 5 ++-- drivers/scsi/bfa/bfad.c | 20 ++++++------- drivers/scsi/esp_scsi.c | 5 ++-- drivers/scsi/gvp11.c | 5 ++-- drivers/scsi/hptiop.c | 5 ++-- drivers/scsi/ibmvscsi/ibmvfc.c | 5 ++-- drivers/scsi/initio.c | 5 ++-- drivers/scsi/ipr.c | 21 ++++++------- drivers/scsi/lpfc/lpfc_sli.c | 49 +++++++++++++------------------ drivers/scsi/mac53c94.c | 5 ++-- drivers/scsi/megaraid.c | 10 +++---- drivers/scsi/megaraid/megaraid_sas_base.c | 5 ++-- drivers/scsi/mesh.c | 5 ++-- drivers/scsi/mvumi.c | 7 ++--- drivers/scsi/myrb.c | 20 +++++-------- drivers/scsi/myrs.c | 15 ++++------ drivers/scsi/ncr53c8xx.c | 5 ++-- drivers/scsi/nsp32.c | 5 ++-- drivers/scsi/pcmcia/sym53c500_cs.c | 5 ++-- drivers/scsi/pmcraid.c | 8 ++--- drivers/scsi/qla4xxx/ql4_isr.c | 15 ++++------ drivers/scsi/qlogicfas408.c | 5 ++-- drivers/scsi/qlogicpti.c | 5 ++-- drivers/scsi/sgiwd93.c | 5 ++-- drivers/scsi/stex.c | 16 +++++----- drivers/scsi/vmw_pvscsi.c | 4 +-- drivers/scsi/wd719x.c | 7 ++--- 33 files changed, 122 insertions(+), 175 deletions(-) -- 2.8.1

5 62

[PATCH RFC rdma-core 0/5] libhns: Add support for Dynamic Context Attachment
by Weihang Li 25 Feb '21

25 Feb '21

The HIP09 introduces the DCA(Dynamic Context Attachment) feature which supports many RC QPs to share the WQE buffer in a memory pool. If a QP enables DCA feature, the WQE's buffer will not be allocated when creating but when the users start to post WRs. This will reduce the memory consumption when there are too many QPs are inactive. Please note that we didn't find the right way to get user's configuration, so in #4 we still use environment variable to achieve this. We will be appreciated if anyone can provide some sugggestions. This series is associated with the kernel series "RDMA/hns: Add support for Dynamic Context Attachment", you can review it at: https://patchwork.kernel.org/project/linux-rdma/cover/1611394994-50363-1-gi… Weihang Li (1): Update kernel headers Xi Wang (4): libhns: Introduce DCA for RC QP libhns: Add support for shrinking DCA memory pool libhns: Add support for attaching QP's WQE buffer libhns: Add support for configuring DCA kernel-headers/rdma/hns-abi.h | 64 +++++++ libibverbs/cmd_qp.c | 3 +- libibverbs/verbs.h | 1 + providers/hns/hns_roce_u.c | 89 +++++++++ providers/hns/hns_roce_u.h | 42 +++++ providers/hns/hns_roce_u_buf.c | 384 +++++++++++++++++++++++++++++++++++++++ providers/hns/hns_roce_u_hw_v2.c | 138 +++++++++++++- providers/hns/hns_roce_u_hw_v2.h | 7 + providers/hns/hns_roce_u_verbs.c | 44 ++++- 9 files changed, 754 insertions(+), 18 deletions(-) -- 2.8.1

4 15

[PATCH 0/4] Use subdir-ccflags-* to inherit debug flag
by Yicong Yang 24 Feb '21

24 Feb '21

Few drivers use ccflags-* in their top directory to enable -DDEBUG, but don't have config options to enable debug in the sub-directories. They should want the subdirectories inherit the debug flag from the top. Use subdir-ccflags-* instead of ccflags-* to inherit the debug settings from Kconfig when traversing subdirectories. We primarily find this issue when debugging PCIe and other drivers may also have this issues. Previous discussion can be find at https://lore.kernel.org/linux-pci/1612438215-33105-1-git-send-email-yangyic… Junhao He (4): driver core: Use subdir-ccflags-* to inherit debug flag hwmon: Use subdir-ccflags-* to inherit debug flag pps: Use subdir-ccflags-* to inherit debug flag staging: comedi: Use subdir-ccflags-* to inherit debug flag drivers/base/Makefile | 2 +- drivers/base/power/Makefile | 2 -- drivers/hwmon/Makefile | 2 +- drivers/pps/Makefile | 2 +- drivers/staging/comedi/Makefile | 2 +- drivers/staging/comedi/drivers/Makefile | 1 - drivers/staging/comedi/drivers/tests/Makefile | 2 -- drivers/staging/comedi/kcomedilib/Makefile | 2 -- 8 files changed, 4 insertions(+), 11 deletions(-) -- 2.8.1

6 16

[PATCH v2 0/2] scripts/gdb: clarify the platforms supporting lx_current and add arm64 support
by Barry Song 24 Feb '21

24 Feb '21

lx_current depends on per_cpu current_task variable which exists on x86 only. so it actually works on x86 only. the 1st patch documents this clearly; the 2nd patch adds support for arm64. Barry Song (2): scripts/gdb: document lx_current is only supported by x86 scripts/gdb: add lx_current support for arm64 .../dev-tools/gdb-kernel-debugging.rst | 2 +- scripts/gdb/linux/cpus.py | 23 +++++++++++++++++-- 2 files changed, 22 insertions(+), 3 deletions(-) -- 2.25.1

1 2

[PATCH] scripts/gdb: document lx_current is only supported by x86
by Barry Song 24 Feb '21

24 Feb '21

lx_current depends on the per_cpu current_task which exists on x86 only: arch$ git grep current_task | grep -i per_cpu x86/include/asm/current.h:DECLARE_PER_CPU(struct task_struct *, current_task); x86/kernel/cpu/common.c:DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = x86/kernel/cpu/common.c:EXPORT_PER_CPU_SYMBOL(current_task); x86/kernel/cpu/common.c:DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; x86/kernel/cpu/common.c:EXPORT_PER_CPU_SYMBOL(current_task); x86/kernel/smpboot.c: per_cpu(current_task, cpu) = idle; On other architectures, lx_current() will lead to a python exception: (gdb) p $lx_current().pid Python Exception <class 'gdb.error'> No symbol "current_task" in current context.: Error occurred in Python: No symbol "current_task" in current context. To avoid more people struggling and wasting time in other architectures, document it. Cc: Jan Kiszka <jan.kiszka(a)siemens.com> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- Documentation/dev-tools/gdb-kernel-debugging.rst | 2 +- scripts/gdb/linux/cpus.py | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/dev-tools/gdb-kernel-debugging.rst b/Documentation/dev-tools/gdb-kernel-debugging.rst index 4756f6b3a04e..1586901b683c 100644 --- a/Documentation/dev-tools/gdb-kernel-debugging.rst +++ b/Documentation/dev-tools/gdb-kernel-debugging.rst @@ -114,7 +114,7 @@ Examples of using the Linux-provided gdb helpers [ 0.000000] BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved .... -- Examine fields of the current task struct:: +- Examine fields of the current task struct(supported by x86 only):: (gdb) p $lx_current().pid $1 = 4998 diff --git a/scripts/gdb/linux/cpus.py b/scripts/gdb/linux/cpus.py index 008e62f3190d..f382762509d3 100644 --- a/scripts/gdb/linux/cpus.py +++ b/scripts/gdb/linux/cpus.py @@ -156,6 +156,13 @@ Note that VAR has to be quoted as string.""" PerCpu() +def get_current_task(cpu): + if utils.is_target_arch("x86"): + var_ptr = gdb.parse_and_eval("&current_task") + return per_cpu(var_ptr, cpu).dereference() + else: + raise gdb.GdbError("Sorry, obtaining the current task is not yet " + "supported with this arch") class LxCurrentFunc(gdb.Function): """Return current task. @@ -167,8 +174,7 @@ number. If CPU is omitted, the CPU of the current context is used.""" super(LxCurrentFunc, self).__init__("lx_current") def invoke(self, cpu=-1): - var_ptr = gdb.parse_and_eval("&current_task") - return per_cpu(var_ptr, cpu).dereference() + return get_current_task(cpu) LxCurrentFunc() -- 2.25.1

4 5

[PATCH 00/13] Features and bugfixes for hns3
by Lijun Ou 23 Feb '21

23 Feb '21

This series add three feature according to the 21.05 roadmap as well as fix some bugs. Chengchang Tang (4): net/hns3: support module EEPROM dump net/hns3: add more registers to dump net/hns3: fix maximum frame size update after buffer alloc net/hns3: fix imprecise statistics Chengwen Feng (2): net/hns3: implement cleanup for Tx done net/hns3: support RXD advanced layout Hongbo Zheng (1): net/hns3: add process for MAC interrupt Huisong Li (4): net/hns3: encapsulate a port shaping interface net/hns3: support PF on electrical net device net/hns3: remove unused parameter from func declaration net/hns3: fix memory leakage for mbuf Min Hu (Connor) (2): net/hns3: add Rx and Tx bytes stats net/hns3: add imissed packet stats doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 5 + drivers/net/hns3/hns3_cmd.c | 8 +- drivers/net/hns3/hns3_cmd.h | 81 +++++++ drivers/net/hns3/hns3_dcb.c | 22 +- drivers/net/hns3/hns3_dcb.h | 2 +- drivers/net/hns3/hns3_ethdev.c | 419 +++++++++++++++++++++++++++++---- drivers/net/hns3/hns3_ethdev.h | 22 ++ drivers/net/hns3/hns3_ethdev_vf.c | 46 ++-- drivers/net/hns3/hns3_intr.c | 20 ++ drivers/net/hns3/hns3_intr.h | 4 + drivers/net/hns3/hns3_regs.c | 171 +++++++++++++- drivers/net/hns3/hns3_regs.h | 1 + drivers/net/hns3/hns3_rxtx.c | 283 ++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 12 + drivers/net/hns3/hns3_rxtx_vec_neon.h | 15 ++ drivers/net/hns3/hns3_rxtx_vec_sve.c | 11 + drivers/net/hns3/hns3_stats.c | 293 +++++++++++++---------- drivers/net/hns3/hns3_stats.h | 12 +- 20 files changed, 1231 insertions(+), 198 deletions(-) -- 2.7.4

1 13

Re: [PATCH v13 00/15] SMMUv3 Nested Stage Setup (IOMMU part)
by Shameerali Kolothum Thodi 22 Feb '21

22 Feb '21

Hi Eric, > -----Original Message----- > From: Eric Auger [mailto:eric.auger@redhat.com] > Sent: 18 November 2020 11:22 > To: eric.auger.pro(a)gmail.com; eric.auger(a)redhat.com; > iommu(a)lists.linux-foundation.org; linux-kernel(a)vger.kernel.org; > kvm(a)vger.kernel.org; kvmarm(a)lists.cs.columbia.edu; will(a)kernel.org; > joro(a)8bytes.org; maz(a)kernel.org; robin.murphy(a)arm.com; > alex.williamson(a)redhat.com > Cc: jean-philippe(a)linaro.org; zhangfei.gao(a)linaro.org; > zhangfei.gao(a)gmail.com; vivek.gautam(a)arm.com; Shameerali Kolothum > Thodi <shameerali.kolothum.thodi(a)huawei.com>; > jacob.jun.pan(a)linux.intel.com; yi.l.liu(a)intel.com; tn(a)semihalf.com; > nicoleotsuka(a)gmail.com; yuzenghui <yuzenghui(a)huawei.com> > Subject: [PATCH v13 00/15] SMMUv3 Nested Stage Setup (IOMMU part) > > This series brings the IOMMU part of HW nested paging support > in the SMMUv3. The VFIO part is submitted separately. > > The IOMMU API is extended to support 2 new API functionalities: > 1) pass the guest stage 1 configuration > 2) pass stage 1 MSI bindings > > Then those capabilities gets implemented in the SMMUv3 driver. > > The virtualizer passes information through the VFIO user API > which cascades them to the iommu subsystem. This allows the guest > to own stage 1 tables and context descriptors (so-called PASID > table) while the host owns stage 2 tables and main configuration > structures (STE). I am seeing an issue with Guest testpmd run with this series. I have two different setups and testpmd works fine with the first one but not with the second. 1). Guest doesn't have kernel driver built-in for pass-through dev. root@ubuntu:/# lspci -v ... 00:02.0 Ethernet controller: Huawei Technologies Co., Ltd. Device a22e (rev 21) Subsystem: Huawei Technologies Co., Ltd. Device 0000 Flags: fast devsel Memory at 8000100000 (64-bit, prefetchable) [disabled] [size=64K] Memory at 8000000000 (64-bit, prefetchable) [disabled] [size=1M] Capabilities: [40] Express Root Complex Integrated Endpoint, MSI 00 Capabilities: [a0] MSI-X: Enable- Count=67 Masked- Capabilities: [b0] Power Management version 3 Capabilities: [100] Access Control Services Capabilities: [300] Transaction Processing Hints root@ubuntu:/# echo vfio-pci > /sys/bus/pci/devices/0000:00:02.0/driver_override root@ubuntu:/# echo 0000:00:02.0 > /sys/bus/pci/drivers_probe root@ubuntu:/mnt/dpdk/build/app# ./testpmd -w 0000:00:02.0 --file-prefix socket0 -l 0-1 -n 2 -- -i EAL: Detected 8 lcore(s) EAL: Detected 1 NUMA nodes EAL: Multi-process socket /var/run/dpdk/socket0/mp_socket EAL: Selected IOVA mode 'VA' EAL: No available hugepages reported in hugepages-32768kB EAL: No available hugepages reported in hugepages-64kB EAL: No available hugepages reported in hugepages-1048576kB EAL: Probing VFIO support... EAL: VFIO support initialized EAL: Invalid NUMA socket, default to 0 EAL: using IOMMU type 1 (Type 1) EAL: Probe PCI driver: net_hns3_vf (19e5:a22e) device: 0000:00:02.0 (socket 0) EAL: No legacy callbacks, legacy socket not created Interactive-mode selected testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=155456, size=2176, socket=0 testpmd: preferred mempool ops selected: ring_mp_mc Warning! port-topology=paired and odd forward ports number, the last port will pair with itself. Configuring Port 0 (socket 0) Port 0: 8E:A6:8C:43:43:45 Checking link statuses... Done testpmd> 2). Guest have kernel driver built-in for pass-through dev. root@ubuntu:/# lspci -v ... 00:02.0 Ethernet controller: Huawei Technologies Co., Ltd. Device a22e (rev 21) Subsystem: Huawei Technologies Co., Ltd. Device 0000 Flags: bus master, fast devsel, latency 0 Memory at 8000100000 (64-bit, prefetchable) [size=64K] Memory at 8000000000 (64-bit, prefetchable) [size=1M] Capabilities: [40] Express Root Complex Integrated Endpoint, MSI 00 Capabilities: [a0] MSI-X: Enable+ Count=67 Masked- Capabilities: [b0] Power Management version 3 Capabilities: [100] Access Control Services Capabilities: [300] Transaction Processing Hints Kernel driver in use: hns3 root@ubuntu:/# echo vfio-pci > /sys/bus/pci/devices/0000:00:02.0/driver_override root@ubuntu:/# echo 0000:00:02.0 > /sys/bus/pci/drivers/hns3/unbind root@ubuntu:/# echo 0000:00:02.0 > /sys/bus/pci/drivers_probe root@ubuntu:/mnt/dpdk/build/app# ./testpmd -w 0000:00:02.0 --file-prefix socket0 -l 0-1 -n 2 -- -i EAL: Detected 8 lcore(s) EAL: Detected 1 NUMA nodes EAL: Multi-process socket /var/run/dpdk/socket0/mp_socket EAL: Selected IOVA mode 'VA' EAL: No available hugepages reported in hugepages-32768kB EAL: No available hugepages reported in hugepages-64kB EAL: No available hugepages reported in hugepages-1048576kB EAL: Probing VFIO support... EAL: VFIO support initialized EAL: Invalid NUMA socket, default to 0 EAL: using IOMMU type 1 (Type 1) EAL: Probe PCI driver: net_hns3_vf (19e5:a22e) device: 0000:00:02.0 (socket 0) 0000:00:02.0 hns3_get_mbx_resp(): VF could not get mbx(11,0) head(1) tail(0) lost(1) from PF in_irq:0 hns3vf_get_queue_info(): Failed to get tqp info from PF: -62 hns3vf_init_vf(): Failed to fetch configuration: -62 hns3vf_dev_init(): Failed to init vf: -62 EAL: Releasing pci mapped resource for 0000:00:02.0 EAL: Calling pci_unmap_resource for 0000:00:02.0 at 0x1100800000 EAL: Calling pci_unmap_resource for 0000:00:02.0 at 0x1100810000 EAL: Requested device 0000:00:02.0 cannot be used EAL: Bus (pci) probe failed. EAL: No legacy callbacks, legacy socket not created testpmd: No probed ethernet devices Interactive-mode selected testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=155456, size=2176, socket=0 testpmd: preferred mempool ops selected: ring_mp_mc Done testpmd> And in this case, smmu(host) reports a translation fault, [ 6542.670624] arm-smmu-v3 arm-smmu-v3.2.auto: event 0x10 received: [ 6542.670630] arm-smmu-v3 arm-smmu-v3.2.auto: 0x00007d1200000010 [ 6542.670631] arm-smmu-v3 arm-smmu-v3.2.auto: 0x000012000000007c [ 6542.670633] arm-smmu-v3 arm-smmu-v3.2.auto: 0x00000000fffef040 [ 6542.670634] arm-smmu-v3 arm-smmu-v3.2.auto: 0x00000000fffef000 Tested with Intel 82599 card(ixgbevf) as well. but same errror. Not able to root cause the problem yet. With the hope that, this is related to tlb entries not being invlaidated properly, I tried explicitly issuing CMD_TLBI_NSNH_ALL and CMD_CFGI_CD_ALL just before the STE update, but no luck yet :( Please let me know if I am missing something here or has any clue if you can replicate this on your setup. Thanks, Shameer > > Best Regards > > Eric > > This series can be found at: > https://github.com/eauger/linux/tree/5.10-rc4-2stage-v13 > (including the VFIO part in his last version: v11) > > The series includes a patch from Jean-Philippe. It is better to > review the original patch: > [PATCH v8 2/9] iommu/arm-smmu-v3: Maintain a SID->device structure > > The VFIO series is sent separately. > > History: > > v12 -> v13: > - fixed compilation issue with CONFIG_ARM_SMMU_V3_SVA > reported by Shameer. This urged me to revisit patch 4 into > iommu/smmuv3: Allow s1 and s2 configs to coexist where > s1_cfg and s2_cfg are not dynamically allocated anymore. > Instead I use a new set field in existing structs > - fixed 2 others config checks > - Updated "iommu/arm-smmu-v3: Maintain a SID->device structure" > according to the last version > > v11 -> v12: > - rebase on top of v5.10-rc4 > > Eric Auger (14): > iommu: Introduce attach/detach_pasid_table API > iommu: Introduce bind/unbind_guest_msi > iommu/smmuv3: Allow s1 and s2 configs to coexist > iommu/smmuv3: Get prepared for nested stage support > iommu/smmuv3: Implement attach/detach_pasid_table > iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs > iommu/smmuv3: Implement cache_invalidate > dma-iommu: Implement NESTED_MSI cookie > iommu/smmuv3: Nested mode single MSI doorbell per domain enforcement > iommu/smmuv3: Enforce incompatibility between nested mode and HW MSI > regions > iommu/smmuv3: Implement bind/unbind_guest_msi > iommu/smmuv3: Report non recoverable faults > iommu/smmuv3: Accept configs with more than one context descriptor > iommu/smmuv3: Add PASID cache invalidation per PASID > > Jean-Philippe Brucker (1): > iommu/arm-smmu-v3: Maintain a SID->device structure > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 659 > ++++++++++++++++++-- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 103 ++- > drivers/iommu/dma-iommu.c | 142 ++++- > drivers/iommu/iommu.c | 105 ++++ > include/linux/dma-iommu.h | 16 + > include/linux/iommu.h | 41 ++ > include/uapi/linux/iommu.h | 54 ++ > 7 files changed, 1042 insertions(+), 78 deletions(-) > > -- > 2.21.3

2 3

[PATCH hulk-4.19-next for SDI V2] net: hns3: adds support for setting pf max tx rate via sysfs
by Yonglong Liu 19 Feb '21

19 Feb '21

driver inclusion category: feature bugzilla: NA CVE: NA DTS:SR20210201768145 ---------------------------- This patch adds support for setting/getting pf max tx rate via sysfs: echo <rate Mbit/s> > /sys/class/net/<eth name>/kunpeng/pf/max_tx_rate cat /sys/class/net/<eth name>/kunpeng/pf/max_tx_rate Signed-off-by: Yonglong Liu <liuyonglong(a)huawei.com> --- drivers/net/ethernet/hisilicon/hns3/Makefile | 3 +- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 8 ++ .../hns3/hns3_extension/hns3pf/hclge_main_it.c | 33 +++++ .../hns3/hns3_extension/hns3pf/hclge_sysfs.c | 140 +++++++++++++++++++++ .../hns3/hns3_extension/hns3pf/hclge_sysfs.h | 14 +++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 17 +++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 5 + 7 files changed, 219 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile index bd607c0..5efa685 100644 --- a/drivers/net/ethernet/hisilicon/hns3/Makefile +++ b/drivers/net/ethernet/hisilicon/hns3/Makefile @@ -38,7 +38,8 @@ HCLGE_OBJ = hns3pf/hclge_main.o \ hns3pf/hclge_err.o -HCLGE_OBJ_IT_MAIN = hns3_extension/hns3pf/hclge_main_it.o +HCLGE_OBJ_IT_MAIN = hns3_extension/hns3pf/hclge_main_it.o \ + hns3_extension/hns3pf/hclge_sysfs.o obj-$(CONFIG_HNS3_HCLGE) += hclge.o hclge-objs := $(HCLGE_OBJ) $(HCLGE_OBJ_IT_MAIN) hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index 3c56cbc..7b39380 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -578,6 +578,9 @@ struct hnae3_ae_ops { int (*ecc_handle)(struct hnae3_ae_dev *ae_dev); int (*priv_ops)(struct hnae3_handle *handle, int opcode, void *data, int length); + void (*ext_init)(struct hnae3_handle *handle); + void (*ext_uninit)(struct hnae3_handle *handle); + void (*ext_reset_done)(struct hnae3_handle *handle); #endif }; @@ -713,6 +716,11 @@ struct hnae3_handle { /* Network interface message level enabled bits */ u32 msg_enable; + +#ifdef CONFIG_HNS3_TEST + /* for sysfs */ + struct kobject *kobj; +#endif }; #define hnae3_set_field(origin, mask, shift, val) \ diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c index 01f0e19..59e2878 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c @@ -18,6 +18,9 @@ #include "hclge_main.h" #include "hnae3.h" #include "hclge_main_it.h" +#ifdef CONFIG_HNS3_TEST +#include "hclge_sysfs.h" +#endif #ifdef CONFIG_IT_VALIDATION #define HCLGE_RESET_MAX_FAIL_CNT 1 @@ -174,8 +177,38 @@ bool hclge_reset_done_it(struct hnae3_handle *handle, bool done) return done; } +#ifdef CONFIG_HNS3_TEST +void hclge_ext_init(struct hnae3_handle *handle) +{ + hclge_sysfs_init(handle); +} + +void hclge_ext_uninit(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + hclge_reset_pf_rate(hdev); + hclge_sysfs_uninit(handle); +} + +void hclge_ext_reset_done(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + hclge_resume_pf_rate(hdev); +} +#endif + int hclge_init_it(void) { +#ifdef CONFIG_HNS3_TEST + hclge_ops.ext_init = hclge_ext_init; + hclge_ops.ext_uninit = hclge_ext_uninit; + hclge_ops.ext_reset_done = hclge_ext_reset_done; +#endif + hclge_ops.reset_event = hclge_reset_event_it; hclge_ops.reset_done = hclge_reset_done_it; hclge_ops.handle_imp_error = hclge_handle_imp_error_it; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c new file mode 100644 index 00000000..86e6093 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2018-2021 Hisilicon Limited. */ + +#include <linux/device.h> +#include "hnae3.h" +#include "hclge_main.h" +#include "hclge_tm.h" +#include "hclge_sysfs.h" + +void hclge_reset_pf_rate(struct hclge_dev *hdev) +{ + struct hclge_vport *vport = &hdev->vport[0]; + int ret; + + /* zero means max rate, if max_tx_rate is zero, just return */ + if (!vport->vf_info.max_tx_rate) + return; + + vport->vf_info.max_tx_rate = 0; + + ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); + if (ret) + dev_err(&hdev->pdev->dev, + "failed to reset pf tx rate to default, ret = %d.\n", + ret); +} + +int hclge_resume_pf_rate(struct hclge_dev *hdev) +{ + struct hclge_vport *vport = &hdev->vport[0]; + int ret; + + /* zero means max rate, after reset, firmware already set it to + * max rate, so just continue. + */ + if (!vport->vf_info.max_tx_rate) + return 0; + + ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to resume pf tx rate:%u, ret = %d.\n", + vport->vf_info.max_tx_rate, ret); + return ret; + } + + return 0; +} + +static ssize_t hclge_max_tx_rate_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + struct hclge_vport *vport = + container_of(kobj, struct hclge_vport, kobj); + + return sprintf(buf, "%d Mbit/s (0 means no limit)\n", + vport->vf_info.max_tx_rate); +} + +static ssize_t hclge_max_tx_rate_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t size) +{ + struct hclge_vport *vport = + container_of(kobj, struct hclge_vport, kobj); + struct hclge_dev *hdev = vport->back; + int max_tx_rate; + int ret; + + ret = kstrtoint(buf, 0, &max_tx_rate); + if (ret) + return -EINVAL; + + if (max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { + dev_err(&hdev->pdev->dev, + "invalid max_tx_rate:%d [0, %u]\n", + max_tx_rate, hdev->hw.mac.max_speed); + return -EINVAL; + } + + ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); + if (ret) + return ret; + + vport->vf_info.max_tx_rate = max_tx_rate; + + return ret ? (ssize_t)ret : size; +} + +static struct kobj_attribute hclge_attr_max_tx_rate = { + .attr = {.name = "max_tx_rate", + .mode = 0644 }, + .show = hclge_max_tx_rate_show, + .store = hclge_max_tx_rate_store, +}; + +static struct attribute *hclge_sysfs_attrs[] = { + &hclge_attr_max_tx_rate.attr, + NULL, +}; + +static struct kobj_type hclge_sysfs_type = { + .sysfs_ops = &kobj_sysfs_ops, + .default_attrs = hclge_sysfs_attrs, +}; + +void hclge_sysfs_init(struct hnae3_handle *handle) +{ + struct net_device *netdev = handle->netdev; + struct hclge_vport *vport = hclge_get_vport(handle); + int ret; + + handle->kobj = kobject_create_and_add("kunpeng", &netdev->dev.kobj); + if (!handle->kobj) { + netdev_err(netdev, "failed to create kobj, ret = %d\n", ret); + return; + } + + ret = kobject_init_and_add(&vport->kobj, &hclge_sysfs_type, + handle->kobj, "pf"); + if (ret) { + netdev_err(netdev, "failed to init kobj, ret = %d\n", ret); + kobject_put(handle->kobj); + handle->kobj = NULL; + } +} + +void hclge_sysfs_uninit(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + + if (!handle->kobj) + return; + + kobject_put(&vport->kobj); + kobject_put(handle->kobj); + handle->kobj = NULL; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h new file mode 100644 index 00000000..8eb3335 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * Copyright (c) 2018-2021 Hisilicon Limited. + */ + +#ifndef __HCLGE_SYSFS_H +#define __HCLGE_SYSFS_H + +void hclge_reset_pf_rate(struct hclge_dev *hdev); +int hclge_resume_pf_rate(struct hclge_dev *hdev); + +void hclge_sysfs_init(struct hnae3_handle *handle); +void hclge_sysfs_uninit(struct hnae3_handle *handle); + +#endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index b40cf43..7b6d7c1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -9946,6 +9946,11 @@ static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, if (ret) return ret; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_init) + ae_dev->ops->ext_init(&vport->nic); +#endif + set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || rst_cnt != hdev->rst_stats.reset_cnt) { @@ -10087,6 +10092,13 @@ static void hclge_uninit_client_instance(struct hnae3_client *client, struct hclge_vport *vport; int i; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_uninit) { + vport = &hdev->vport[0]; + ae_dev->ops->ext_uninit(&vport->nic); + } +#endif + for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { vport = &hdev->vport[i]; if (hdev->roce_client) { @@ -10817,6 +10829,11 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) if (ret) return ret; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_reset_done) + ae_dev->ops->ext_reset_done(&hdev->vport->nic); +#endif + dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", HCLGE_DRIVER_NAME); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index 08d17ba..f803a9d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -970,6 +970,11 @@ struct hclge_vport { struct list_head uc_mac_list; /* Store VF unicast table */ struct list_head mc_mac_list; /* Store VF multicast table */ struct list_head vlan_list; /* Store VF vlan table */ + +#ifdef CONFIG_HNS3_TEST + /* for sysfs */ + struct kobject kobj; +#endif }; int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, -- 2.7.4

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[PATCH v2] sched/topology: fix the issue groups don't span domain->span for NUMA diameter > 2
by Barry Song 19 Feb '21

19 Feb '21

As long as NUMA diameter > 2, building sched_domain by sibling's child domain will definitely create a sched_domain with sched_group which will span out of the sched_domain: +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 node2 node3 domain1 node0+1 node0+1 node2+3 node2+3 + domain2 node0+1+2 | group: node0+1 | group:node2+3 <-------------------+ when node2 is added into the domain2 of node0, kernel is using the child domain of node2's domain2, which is domain1(node2+3). Node 3 is outside the span of the domain including node0+1+2. This will make load_balance() run based on screwed avg_load and group_type in the sched_group spanning out of the sched_domain, and it also makes select_task_rq_fair() pick an idle CPU out of the sched_domain. Real servers which suffer from this problem include Kunpeng920 and 8-node Sun Fire X4600-M2, at least. Here we move to use the *child* domain of the *child* domain of node2's domain2 as the new added sched_group. At the same time, we re-use the lower level sgc directly. +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 +- node2 node3 | domain1 node0+1 node0+1 | node2+3 node2+3 | domain2 node0+1+2 | group: node0+1 | group:node2 <-------------------+ Tested by the below topology: qemu-system-aarch64 -M virt -nographic \ -smp cpus=8 \ -numa node,cpus=0-1,nodeid=0 \ -numa node,cpus=2-3,nodeid=1 \ -numa node,cpus=4-5,nodeid=2 \ -numa node,cpus=6-7,nodeid=3 \ -numa dist,src=0,dst=1,val=12 \ -numa dist,src=0,dst=2,val=20 \ -numa dist,src=0,dst=3,val=22 \ -numa dist,src=1,dst=2,val=22 \ -numa dist,src=2,dst=3,val=12 \ -numa dist,src=1,dst=3,val=24 \ -m 4G -cpu cortex-a57 -kernel arch/arm64/boot/Image w/o patch, we get lots of "groups don't span domain->span": [ 0.802139] CPU0 attaching sched-domain(s): [ 0.802193] domain-0: span=0-1 level=MC [ 0.802443] groups: 0:{ span=0 cap=1013 }, 1:{ span=1 cap=979 } [ 0.802693] domain-1: span=0-3 level=NUMA [ 0.802731] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.802811] domain-2: span=0-5 level=NUMA [ 0.802829] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.802881] ERROR: groups don't span domain->span [ 0.803058] domain-3: span=0-7 level=NUMA [ 0.803080] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804055] CPU1 attaching sched-domain(s): [ 0.804072] domain-0: span=0-1 level=MC [ 0.804096] groups: 1:{ span=1 cap=979 }, 0:{ span=0 cap=1013 } [ 0.804152] domain-1: span=0-3 level=NUMA [ 0.804170] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.804219] domain-2: span=0-5 level=NUMA [ 0.804236] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.804302] ERROR: groups don't span domain->span [ 0.804520] domain-3: span=0-7 level=NUMA [ 0.804546] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804677] CPU2 attaching sched-domain(s): [ 0.804687] domain-0: span=2-3 level=MC [ 0.804705] groups: 2:{ span=2 cap=934 }, 3:{ span=3 cap=1009 } [ 0.804754] domain-1: span=0-3 level=NUMA [ 0.804772] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.804820] domain-2: span=0-5 level=NUMA [ 0.804836] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.804944] ERROR: groups don't span domain->span [ 0.805108] domain-3: span=0-7 level=NUMA [ 0.805134] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805223] CPU3 attaching sched-domain(s): [ 0.805232] domain-0: span=2-3 level=MC [ 0.805249] groups: 3:{ span=3 cap=1009 }, 2:{ span=2 cap=934 } [ 0.805319] domain-1: span=0-3 level=NUMA [ 0.805336] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.805383] domain-2: span=0-5 level=NUMA [ 0.805399] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.805458] ERROR: groups don't span domain->span [ 0.805605] domain-3: span=0-7 level=NUMA [ 0.805626] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805712] CPU4 attaching sched-domain(s): [ 0.805721] domain-0: span=4-5 level=MC [ 0.805738] groups: 4:{ span=4 cap=984 }, 5:{ span=5 cap=924 } [ 0.805787] domain-1: span=4-7 level=NUMA [ 0.805803] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.805851] domain-2: span=0-1,4-7 level=NUMA [ 0.805867] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.805915] ERROR: groups don't span domain->span [ 0.806108] domain-3: span=0-7 level=NUMA [ 0.806130] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.806214] CPU5 attaching sched-domain(s): [ 0.806222] domain-0: span=4-5 level=MC [ 0.806240] groups: 5:{ span=5 cap=924 }, 4:{ span=4 cap=984 } [ 0.806841] domain-1: span=4-7 level=NUMA [ 0.806866] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.806934] domain-2: span=0-1,4-7 level=NUMA [ 0.806953] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.807004] ERROR: groups don't span domain->span [ 0.807312] domain-3: span=0-7 level=NUMA [ 0.807386] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.807686] CPU6 attaching sched-domain(s): [ 0.807710] domain-0: span=6-7 level=MC [ 0.807750] groups: 6:{ span=6 cap=1017 }, 7:{ span=7 cap=1012 } [ 0.807840] domain-1: span=4-7 level=NUMA [ 0.807870] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.807952] domain-2: span=0-1,4-7 level=NUMA [ 0.807985] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.808045] ERROR: groups don't span domain->span [ 0.808257] domain-3: span=0-7 level=NUMA [ 0.808571] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6125 }, 2:{ span=0-5 mask=2-3 cap=5899 } [ 0.808848] CPU7 attaching sched-domain(s): [ 0.808860] domain-0: span=6-7 level=MC [ 0.808880] groups: 7:{ span=7 cap=1012 }, 6:{ span=6 cap=1017 } [ 0.808953] domain-1: span=4-7 level=NUMA [ 0.808974] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.809034] domain-2: span=0-1,4-7 level=NUMA [ 0.809055] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.809128] ERROR: groups don't span domain->span [ 0.810361] domain-3: span=0-7 level=NUMA [ 0.810400] groups: 6:{ span=0-1,4-7 mask=6-7 cap=5961 }, 2:{ span=0-5 mask=2-3 cap=5903 } w/ patch, we don't get "groups don't span domain->span" any more: [ 1.486271] CPU0 attaching sched-domain(s): [ 1.486820] domain-0: span=0-1 level=MC [ 1.500924] groups: 0:{ span=0 cap=980 }, 1:{ span=1 cap=994 } [ 1.515717] domain-1: span=0-3 level=NUMA [ 1.515903] groups: 0:{ span=0-1 cap=1974 }, 2:{ span=2-3 cap=1989 } [ 1.516989] domain-2: span=0-5 level=NUMA [ 1.517124] groups: 0:{ span=0-3 cap=3963 }, 4:{ span=4-5 cap=1949 } [ 1.517369] domain-3: span=0-7 level=NUMA [ 1.517423] groups: 0:{ span=0-5 mask=0-1 cap=5912 }, 6:{ span=4-7 mask=6-7 cap=4054 } [ 1.520027] CPU1 attaching sched-domain(s): [ 1.520097] domain-0: span=0-1 level=MC [ 1.520184] groups: 1:{ span=1 cap=994 }, 0:{ span=0 cap=980 } [ 1.520429] domain-1: span=0-3 level=NUMA [ 1.520487] groups: 0:{ span=0-1 cap=1974 }, 2:{ span=2-3 cap=1989 } [ 1.520687] domain-2: span=0-5 level=NUMA [ 1.520744] groups: 0:{ span=0-3 cap=3963 }, 4:{ span=4-5 cap=1949 } [ 1.520948] domain-3: span=0-7 level=NUMA [ 1.521038] groups: 0:{ span=0-5 mask=0-1 cap=5912 }, 6:{ span=4-7 mask=6-7 cap=4054 } [ 1.522068] CPU2 attaching sched-domain(s): [ 1.522348] domain-0: span=2-3 level=MC [ 1.522606] groups: 2:{ span=2 cap=1003 }, 3:{ span=3 cap=986 } [ 1.522832] domain-1: span=0-3 level=NUMA [ 1.522885] groups: 2:{ span=2-3 cap=1989 }, 0:{ span=0-1 cap=1974 } [ 1.523043] domain-2: span=0-5 level=NUMA [ 1.523092] groups: 2:{ span=0-3 mask=2-3 cap=4037 }, 4:{ span=4-5 cap=1949 } [ 1.523302] domain-3: span=0-7 level=NUMA [ 1.523352] groups: 2:{ span=0-5 mask=2-3 cap=5986 }, 6:{ span=0-1,4-7 mask=6-7 cap=6102 } [ 1.523748] CPU3 attaching sched-domain(s): [ 1.523774] domain-0: span=2-3 level=MC [ 1.523825] groups: 3:{ span=3 cap=986 }, 2:{ span=2 cap=1003 } [ 1.524009] domain-1: span=0-3 level=NUMA [ 1.524086] groups: 2:{ span=2-3 cap=1989 }, 0:{ span=0-1 cap=1974 } [ 1.524281] domain-2: span=0-5 level=NUMA [ 1.524331] groups: 2:{ span=0-3 mask=2-3 cap=4037 }, 4:{ span=4-5 cap=1949 } [ 1.524534] domain-3: span=0-7 level=NUMA [ 1.524586] groups: 2:{ span=0-5 mask=2-3 cap=5986 }, 6:{ span=0-1,4-7 mask=6-7 cap=6102 } [ 1.524847] CPU4 attaching sched-domain(s): [ 1.524873] domain-0: span=4-5 level=MC [ 1.524954] groups: 4:{ span=4 cap=958 }, 5:{ span=5 cap=991 } [ 1.525105] domain-1: span=4-7 level=NUMA [ 1.525153] groups: 4:{ span=4-5 cap=1949 }, 6:{ span=6-7 cap=2006 } [ 1.525368] domain-2: span=0-1,4-7 level=NUMA [ 1.525428] groups: 4:{ span=4-7 cap=3955 }, 0:{ span=0-1 cap=1974 } [ 1.532726] domain-3: span=0-7 level=NUMA [ 1.532811] groups: 4:{ span=0-1,4-7 mask=4-5 cap=6003 }, 2:{ span=0-3 mask=2-3 cap=4037 } [ 1.534125] CPU5 attaching sched-domain(s): [ 1.534159] domain-0: span=4-5 level=MC [ 1.534303] groups: 5:{ span=5 cap=991 }, 4:{ span=4 cap=958 } [ 1.534490] domain-1: span=4-7 level=NUMA [ 1.534572] groups: 4:{ span=4-5 cap=1949 }, 6:{ span=6-7 cap=2006 } [ 1.534734] domain-2: span=0-1,4-7 level=NUMA [ 1.534783] groups: 4:{ span=4-7 cap=3955 }, 0:{ span=0-1 cap=1974 } [ 1.536057] domain-3: span=0-7 level=NUMA [ 1.536430] groups: 4:{ span=0-1,4-7 mask=4-5 cap=6003 }, 2:{ span=0-3 mask=2-3 cap=3896 } [ 1.536815] CPU6 attaching sched-domain(s): [ 1.536846] domain-0: span=6-7 level=MC [ 1.536934] groups: 6:{ span=6 cap=1005 }, 7:{ span=7 cap=1001 } [ 1.537144] domain-1: span=4-7 level=NUMA [ 1.537262] groups: 6:{ span=6-7 cap=2006 }, 4:{ span=4-5 cap=1949 } [ 1.537553] domain-2: span=0-1,4-7 level=NUMA [ 1.537613] groups: 6:{ span=4-7 mask=6-7 cap=4054 }, 0:{ span=0-1 cap=1805 } [ 1.537872] domain-3: span=0-7 level=NUMA [ 1.537998] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6102 }, 2:{ span=0-5 mask=2-3 cap=5845 } [ 1.538448] CPU7 attaching sched-domain(s): [ 1.538505] domain-0: span=6-7 level=MC [ 1.538586] groups: 7:{ span=7 cap=1001 }, 6:{ span=6 cap=1005 } [ 1.538746] domain-1: span=4-7 level=NUMA [ 1.538798] groups: 6:{ span=6-7 cap=2006 }, 4:{ span=4-5 cap=1949 } [ 1.539048] domain-2: span=0-1,4-7 level=NUMA [ 1.539111] groups: 6:{ span=4-7 mask=6-7 cap=4054 }, 0:{ span=0-1 cap=1805 } [ 1.539571] domain-3: span=0-7 level=NUMA [ 1.539610] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6102 }, 2:{ span=0-5 mask=2-3 cap=5845 } Reported-by: Valentin Schneider <valentin.schneider(a)arm.com> Tested-by: Meelis Roos <mroos(a)linux.ee> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- -v2: merged Valentin's edit on v1, thus fixed two issues * "one cpu in one numa" was not supported * the capacity of groups from grandchild couldn't be updated Thanks for Valentin's nice edit! And also added some comments in build_balance_mask kernel/sched/topology.c | 85 +++++++++++++++++++++++++---------------- 1 file changed, 53 insertions(+), 32 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 5d3675c7a76b..964ed89001fe 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -723,35 +723,6 @@ cpu_attach_domain(struct sched_domain *sd, struct root_domain *rd, int cpu) for (tmp = sd; tmp; tmp = tmp->parent) numa_distance += !!(tmp->flags & SD_NUMA); - /* - * FIXME: Diameter >=3 is misrepresented. - * - * Smallest diameter=3 topology is: - * - * node 0 1 2 3 - * 0: 10 20 30 40 - * 1: 20 10 20 30 - * 2: 30 20 10 20 - * 3: 40 30 20 10 - * - * 0 --- 1 --- 2 --- 3 - * - * NUMA-3 0-3 N/A N/A 0-3 - * groups: {0-2},{1-3} {1-3},{0-2} - * - * NUMA-2 0-2 0-3 0-3 1-3 - * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} - * - * NUMA-1 0-1 0-2 1-3 2-3 - * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} - * - * NUMA-0 0 1 2 3 - * - * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the - * group span isn't a subset of the domain span. - */ - WARN_ONCE(numa_distance > 2, "Shortest NUMA path spans too many nodes\n"); - sched_domain_debug(sd, cpu); rq_attach_root(rq, rd); @@ -908,6 +879,17 @@ build_balance_mask(struct sched_domain *sd, struct sched_group *sg, struct cpuma for_each_cpu(i, sg_span) { sibling = *per_cpu_ptr(sdd->sd, i); + /* + * for NUMA diameter >= 3, while sibling->child spans out of + * the domain being built, we are using the grandchild; + * build_overlap_sched_groups includes words on how this could + * happen + */ + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + sched_domain_span(sd))) + sibling = sibling->child; + /* * Can happen in the asymmetric case, where these siblings are * unused. The mask will not be empty because those CPUs that @@ -955,10 +937,11 @@ build_group_from_child_sched_domain(struct sched_domain *sd, int cpu) } static void init_overlap_sched_group(struct sched_domain *sd, - struct sched_group *sg) + struct sched_group *sg, + struct sched_domain *grandchild) { struct cpumask *mask = sched_domains_tmpmask2; - struct sd_data *sdd = sd->private; + struct sd_data *sdd = grandchild ? grandchild->private : sd->private; struct cpumask *sg_span; int cpu; @@ -996,6 +979,7 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) for_each_cpu_wrap(i, span, cpu) { struct cpumask *sg_span; + bool from_grandchild = false; if (cpumask_test_cpu(i, covered)) continue; @@ -1015,6 +999,43 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) if (!cpumask_test_cpu(i, sched_domain_span(sibling))) continue; + /* + * for NUMA diameter >= 3, building sched_domain by sibling's + * child's child domain to prevent sched_group from spanning + * out of sched_domain + * if we don't do this, Diameter >=3 is misrepresented: + * + * Smallest diameter=3 topology is: + * + * node 0 1 2 3 + * 0: 10 20 30 40 + * 1: 20 10 20 30 + * 2: 30 20 10 20 + * 3: 40 30 20 10 + * + * 0 --- 1 --- 2 --- 3 + * + * NUMA-3 0-3 N/A N/A 0-3 + * groups: {0-2},{1-3} {1-3},{0-2} + * + * NUMA-2 0-2 0-3 0-3 1-3 + * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} + * + * NUMA-1 0-1 0-2 1-3 2-3 + * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} + * + * NUMA-0 0 1 2 3 + * + * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the + * group span isn't a subset of the domain span. + */ + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + span)) { + sibling = sibling->child; + from_grandchild = true; + } + sg = build_group_from_child_sched_domain(sibling, cpu); if (!sg) goto fail; @@ -1022,7 +1043,7 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) sg_span = sched_group_span(sg); cpumask_or(covered, covered, sg_span); - init_overlap_sched_group(sd, sg); + init_overlap_sched_group(sd, sg, from_grandchild ? sibling : NULL); if (!first) first = sg; -- 2.25.1

5 10

Re: [PATCH v11 12/13] vfio/pci: Register a DMA fault response region
by Shameerali Kolothum Thodi 18 Feb '21

18 Feb '21

Hi Eric, > > -----Original Message----- > > From: Eric Auger [mailto:eric.auger@redhat.com] > > Sent: 16 November 2020 11:00 > > To: eric.auger.pro(a)gmail.com; eric.auger(a)redhat.com; > > iommu(a)lists.linux-foundation.org; linux-kernel(a)vger.kernel.org; > > kvm(a)vger.kernel.org; kvmarm(a)lists.cs.columbia.edu; will(a)kernel.org; > > joro(a)8bytes.org; maz(a)kernel.org; robin.murphy(a)arm.com; > > alex.williamson(a)redhat.com > > Cc: jean-philippe(a)linaro.org; zhangfei.gao(a)linaro.org; > > zhangfei.gao(a)gmail.com; vivek.gautam(a)arm.com; Shameerali Kolothum > > Thodi <shameerali.kolothum.thodi(a)huawei.com>; > > jacob.jun.pan(a)linux.intel.com; yi.l.liu(a)intel.com; tn(a)semihalf.com; > > nicoleotsuka(a)gmail.com; yuzenghui <yuzenghui(a)huawei.com> > > Subject: [PATCH v11 12/13] vfio/pci: Register a DMA fault response > > region > > > > In preparation for vSVA, let's register a DMA fault response region, > > where the userspace will push the page responses and increment the > > head of the buffer. The kernel will pop those responses and inject > > them on iommu side. > > > > Signed-off-by: Eric Auger <eric.auger(a)redhat.com> > > --- > > drivers/vfio/pci/vfio_pci.c | 114 +++++++++++++++++++++++++--- > > drivers/vfio/pci/vfio_pci_private.h | 5 ++ > > drivers/vfio/pci/vfio_pci_rdwr.c | 39 ++++++++++ > > include/uapi/linux/vfio.h | 32 ++++++++ > > 4 files changed, 181 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c > > index 65a83fd0e8c0..e9a904ce3f0d 100644 > > --- a/drivers/vfio/pci/vfio_pci.c > > +++ b/drivers/vfio/pci/vfio_pci.c > > @@ -318,9 +318,20 @@ static void vfio_pci_dma_fault_release(struct > > vfio_pci_device *vdev, > > kfree(vdev->fault_pages); > > } > > > > -static int vfio_pci_dma_fault_mmap(struct vfio_pci_device *vdev, > > - struct vfio_pci_region *region, > > - struct vm_area_struct *vma) > > +static void > > +vfio_pci_dma_fault_response_release(struct vfio_pci_device *vdev, > > + struct vfio_pci_region *region) { > > + if (vdev->dma_fault_response_wq) > > + destroy_workqueue(vdev->dma_fault_response_wq); > > + kfree(vdev->fault_response_pages); > > + vdev->fault_response_pages = NULL; > > +} > > + > > +static int __vfio_pci_dma_fault_mmap(struct vfio_pci_device *vdev, > > + struct vfio_pci_region *region, > > + struct vm_area_struct *vma, > > + u8 *pages) > > { > > u64 phys_len, req_len, pgoff, req_start; > > unsigned long long addr; > > @@ -333,14 +344,14 @@ static int vfio_pci_dma_fault_mmap(struct > > vfio_pci_device *vdev, > > ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); > > req_start = pgoff << PAGE_SHIFT; > > > > - /* only the second page of the producer fault region is mmappable */ > > + /* only the second page of the fault region is mmappable */ > > if (req_start < PAGE_SIZE) > > return -EINVAL; > > > > if (req_start + req_len > phys_len) > > return -EINVAL; > > > > - addr = virt_to_phys(vdev->fault_pages); > > + addr = virt_to_phys(pages); > > vma->vm_private_data = vdev; > > vma->vm_pgoff = (addr >> PAGE_SHIFT) + pgoff; > > > > @@ -349,13 +360,29 @@ static int vfio_pci_dma_fault_mmap(struct > > vfio_pci_device *vdev, > > return ret; > > } > > > > -static int vfio_pci_dma_fault_add_capability(struct vfio_pci_device *vdev, > > - struct vfio_pci_region *region, > > - struct vfio_info_cap *caps) > > +static int vfio_pci_dma_fault_mmap(struct vfio_pci_device *vdev, > > + struct vfio_pci_region *region, > > + struct vm_area_struct *vma) > > +{ > > + return __vfio_pci_dma_fault_mmap(vdev, region, vma, > > vdev->fault_pages); > > +} > > + > > +static int > > +vfio_pci_dma_fault_response_mmap(struct vfio_pci_device *vdev, > > + struct vfio_pci_region *region, > > + struct vm_area_struct *vma) > > +{ > > + return __vfio_pci_dma_fault_mmap(vdev, region, vma, > > vdev->fault_response_pages); > > +} > > + > > +static int __vfio_pci_dma_fault_add_capability(struct vfio_pci_device *vdev, > > + struct vfio_pci_region *region, > > + struct vfio_info_cap *caps, > > + u32 cap_id) > > { > > struct vfio_region_info_cap_sparse_mmap *sparse = NULL; > > struct vfio_region_info_cap_fault cap = { > > - .header.id = VFIO_REGION_INFO_CAP_DMA_FAULT, > > + .header.id = cap_id, > > .header.version = 1, > > .version = 1, > > }; > > @@ -383,6 +410,14 @@ static int > > vfio_pci_dma_fault_add_capability(struct > > vfio_pci_device *vdev, > > return ret; > > } > > > > +static int vfio_pci_dma_fault_add_capability(struct vfio_pci_device *vdev, > > + struct vfio_pci_region *region, > > + struct vfio_info_cap *caps) { > > + return __vfio_pci_dma_fault_add_capability(vdev, region, caps, > > + VFIO_REGION_INFO_CAP_DMA_FAULT); } > > + > > static const struct vfio_pci_regops vfio_pci_dma_fault_regops = { > > .rw = vfio_pci_dma_fault_rw, > > .release = vfio_pci_dma_fault_release, > > @@ -390,6 +425,13 @@ static const struct vfio_pci_regops > > vfio_pci_dma_fault_regops = { > > .add_capability = vfio_pci_dma_fault_add_capability, > > }; > > > > +static const struct vfio_pci_regops vfio_pci_dma_fault_response_regops = { > > + .rw = vfio_pci_dma_fault_response_rw, > > + .release = vfio_pci_dma_fault_response_release, > > + .mmap = vfio_pci_dma_fault_response_mmap, > > + .add_capability = vfio_pci_dma_fault_add_capability, As I mentioned in the Qemu patch ([RFC v7 26/26] vfio/pci: Implement return_page_response page response callback), it looks like we are using the VFIO_REGION_INFO_CAP_DMA_FAULT cap id for the dma_fault_response here as well. Is that intentional? (Was wondering how it worked in the first place and noted this). Please check. Thanks, Shameer

2 1

Re: [PATCH v2] iommu: Check dev->iommu in iommu_dev_xxx functions
by Shameerali Kolothum Thodi 16 Feb '21

16 Feb '21

Hi Robin/Joerg, > -----Original Message----- > From: Shameer Kolothum [mailto:shameerali.kolothum.thodi@huawei.com] > Sent: 01 February 2021 12:41 > To: linux-kernel(a)vger.kernel.org; iommu(a)lists.linux-foundation.org > Cc: joro(a)8bytes.org; robin.murphy(a)arm.com; jean-philippe(a)linaro.org; > will(a)kernel.org; Zengtao (B) <prime.zeng(a)hisilicon.com>; > linuxarm(a)openeuler.org > Subject: [Linuxarm] [PATCH v2] iommu: Check dev->iommu in iommu_dev_xxx > functions > > The device iommu probe/attach might have failed leaving dev->iommu > to NULL and device drivers may still invoke these functions resulting > in a crash in iommu vendor driver code. Hence make sure we check that. > > Also added iommu_ops to the "struct dev_iommu" and set it if the dev > is successfully associated with an iommu. > > Fixes: a3a195929d40 ("iommu: Add APIs for multiple domains per device") > Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi(a)huawei.com> > --- > v1 --> v2: > -Added iommu_ops to struct dev_iommu based on the discussion with Robin. > -Rebased against iommu-tree core branch. A gentle ping on this... Thanks, Shameer > --- > drivers/iommu/iommu.c | 19 +++++++------------ > include/linux/iommu.h | 2 ++ > 2 files changed, 9 insertions(+), 12 deletions(-) > > diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c > index fd76e2f579fe..6023d0b7c542 100644 > --- a/drivers/iommu/iommu.c > +++ b/drivers/iommu/iommu.c > @@ -217,6 +217,7 @@ static int __iommu_probe_device(struct device *dev, > struct list_head *group_list > } > > dev->iommu->iommu_dev = iommu_dev; > + dev->iommu->ops = iommu_dev->ops; > > group = iommu_group_get_for_dev(dev); > if (IS_ERR(group)) { > @@ -2865,10 +2866,8 @@ EXPORT_SYMBOL_GPL(iommu_fwspec_add_ids); > */ > int iommu_dev_enable_feature(struct device *dev, enum > iommu_dev_features feat) > { > - const struct iommu_ops *ops = dev->bus->iommu_ops; > - > - if (ops && ops->dev_enable_feat) > - return ops->dev_enable_feat(dev, feat); > + if (dev->iommu && dev->iommu->ops->dev_enable_feat) > + return dev->iommu->ops->dev_enable_feat(dev, feat); > > return -ENODEV; > } > @@ -2881,10 +2880,8 @@ > EXPORT_SYMBOL_GPL(iommu_dev_enable_feature); > */ > int iommu_dev_disable_feature(struct device *dev, enum > iommu_dev_features feat) > { > - const struct iommu_ops *ops = dev->bus->iommu_ops; > - > - if (ops && ops->dev_disable_feat) > - return ops->dev_disable_feat(dev, feat); > + if (dev->iommu && dev->iommu->ops->dev_disable_feat) > + return dev->iommu->ops->dev_disable_feat(dev, feat); > > return -EBUSY; > } > @@ -2892,10 +2889,8 @@ > EXPORT_SYMBOL_GPL(iommu_dev_disable_feature); > > bool iommu_dev_feature_enabled(struct device *dev, enum > iommu_dev_features feat) > { > - const struct iommu_ops *ops = dev->bus->iommu_ops; > - > - if (ops && ops->dev_feat_enabled) > - return ops->dev_feat_enabled(dev, feat); > + if (dev->iommu && dev->iommu->ops->dev_feat_enabled) > + return dev->iommu->ops->dev_feat_enabled(dev, feat); > > return false; > } > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index 524ffc2ff64f..ff0c76bdfb67 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -354,6 +354,7 @@ struct iommu_fault_param { > * @fault_param: IOMMU detected device fault reporting data > * @fwspec: IOMMU fwspec data > * @iommu_dev: IOMMU device this device is linked to > + * @ops: iommu-ops for talking to the iommu_dev > * @priv: IOMMU Driver private data > * > * TODO: migrate other per device data pointers under iommu_dev_data, > e.g. > @@ -364,6 +365,7 @@ struct dev_iommu { > struct iommu_fault_param *fault_param; > struct iommu_fwspec *fwspec; > struct iommu_device *iommu_dev; > + const struct iommu_ops *ops; > void *priv; > }; > > -- > 2.17.1 > _______________________________________________ > Linuxarm mailing list -- linuxarm(a)openeuler.org > To unsubscribe send an email to linuxarm-leave(a)openeuler.org

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[PATCH V2 net-next 00/13] net: hns3: some cleanups for -next
by Huazhong Tan 13 Feb '21

13 Feb '21

To improve code readability and maintainability, the series refactor out some bloated functions in the HNS3 ethernet driver. change log: V2: remove an unused variable in #5 previous version: V1: https://patchwork.kernel.org/project/netdevbpf/cover/1612943005-59416-1-git… Hao Chen (1): net: hns3: refactor out hclge_rm_vport_all_mac_table() Huazhong Tan (2): net: hns3: refactor out hclge_set_rss_tuple() net: hns3: refactor out hclgevf_set_rss_tuple() Jian Shen (3): net: hns3: refactor out hclge_get_rss_tuple() net: hns3: refactor out hclgevf_get_rss_tuple() net: hns3: split out hclge_dbg_dump_qos_buf_cfg() Jiaran Zhang (1): net: hns3: use ipv6_addr_any() helper Peng Li (4): net: hns3: refactor out hclge_cmd_convert_err_code() net: hns3: refactor out hclgevf_cmd_convert_err_code() net: hns3: clean up hns3_dbg_cmd_write() net: hns3: refactor out hclge_set_vf_vlan_common() Yufeng Mo (2): net: hns3: split out hclge_cmd_send() net: hns3: split out hclgevf_cmd_send() .../ethernet/hisilicon/hns3/hns3_debugfs.c | 44 +-- .../hisilicon/hns3/hns3pf/hclge_cmd.c | 155 ++++++----- .../hisilicon/hns3/hns3pf/hclge_debugfs.c | 158 ++++++++--- .../hisilicon/hns3/hns3pf/hclge_main.c | 254 +++++++++++------- .../hisilicon/hns3/hns3vf/hclgevf_cmd.c | 194 +++++++------ .../hisilicon/hns3/hns3vf/hclgevf_main.c | 114 +++++--- 6 files changed, 571 insertions(+), 348 deletions(-) -- 2.25.1

2 9

[PATCH for next v1 0/2] gpio: few clean up patches to replace spin_lock_irqsave with spin_lock
by Luo Jiaxing 13 Feb '21

13 Feb '21

There is no need to use API with _irqsave in hard IRQ handler, So replace those with spin_lock. Luo Jiaxing (2): gpio: omap: Replace raw_spin_lock_irqsave with raw_spin_lock in omap_gpio_irq_handler() gpio: grgpio: Replace spin_lock_irqsave with spin_lock in grgpio_irq_handler() drivers/gpio/gpio-grgpio.c | 5 ++--- drivers/gpio/gpio-omap.c | 15 ++++++--------- 2 files changed, 8 insertions(+), 12 deletions(-) -- 2.7.4

6 29

[PATCH] i2c: busses: Replace spin_lock_irqsave with spin_lock in hard IRQ
by Weihang Li 12 Feb '21

12 Feb '21

There is no need to do irqsave and irqrestore in context of hard IRQ. Cc: Baruch Siach <baruch(a)tkos.co.il> Cc: Paul Cercueil <paul(a)crapouillou.net> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/i2c/busses/i2c-digicolor.c | 5 ++--- drivers/i2c/busses/i2c-jz4780.c | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-digicolor.c b/drivers/i2c/busses/i2c-digicolor.c index f67639d..60c838c 100644 --- a/drivers/i2c/busses/i2c-digicolor.c +++ b/drivers/i2c/busses/i2c-digicolor.c @@ -160,12 +160,11 @@ static irqreturn_t dc_i2c_irq(int irq, void *dev_id) { struct dc_i2c *i2c = dev_id; int cmd_status = dc_i2c_cmd_status(i2c); - unsigned long flags; u8 addr_cmd; writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR); - spin_lock_irqsave(&i2c->lock, flags); + spin_lock(&i2c->lock); if (cmd_status == II_CMD_STATUS_ACK_BAD || cmd_status == II_CMD_STATUS_ABORT) { @@ -207,7 +206,7 @@ static irqreturn_t dc_i2c_irq(int irq, void *dev_id) } out: - spin_unlock_irqrestore(&i2c->lock, flags); + spin_unlock(&i2c->lock); return IRQ_HANDLED; } diff --git a/drivers/i2c/busses/i2c-jz4780.c b/drivers/i2c/busses/i2c-jz4780.c index cb4a25e..8509c5f 100644 --- a/drivers/i2c/busses/i2c-jz4780.c +++ b/drivers/i2c/busses/i2c-jz4780.c @@ -437,9 +437,8 @@ static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id) unsigned short intst; unsigned short intmsk; struct jz4780_i2c *i2c = dev_id; - unsigned long flags; - spin_lock_irqsave(&i2c->lock, flags); + spin_lock(&i2c->lock); intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM); intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST); @@ -551,7 +550,7 @@ static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id) } done: - spin_unlock_irqrestore(&i2c->lock, flags); + spin_unlock(&i2c->lock); return IRQ_HANDLED; } -- 2.8.1

2 1

[PATCH V2 net-next 09/13] net: hns3: split out hclge_cmd_send()
by Huazhong Tan 12 Feb '21

12 Feb '21

From: Yufeng Mo <moyufeng(a)huawei.com> hclge_cmd_send() is bloated, so split it into separate functions for readability and maintainability. Signed-off-by: Yufeng Mo <moyufeng(a)huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong(a)huawei.com> --- .../hisilicon/hns3/hns3pf/hclge_cmd.c | 100 +++++++++++------- 1 file changed, 59 insertions(+), 41 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c index cb2c955ce52c..1bd0ddfaec4d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c @@ -194,6 +194,22 @@ struct errcode { int common_errno; }; +static void hclge_cmd_copy_desc(struct hclge_hw *hw, struct hclge_desc *desc, + int num) +{ + struct hclge_desc *desc_to_use; + int handle = 0; + + while (handle < num) { + desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use]; + *desc_to_use = desc[handle]; + (hw->cmq.csq.next_to_use)++; + if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num) + hw->cmq.csq.next_to_use = 0; + handle++; + } +} + static int hclge_cmd_convert_err_code(u16 desc_ret) { struct errcode hclge_cmd_errcode[] = { @@ -243,6 +259,44 @@ static int hclge_cmd_check_retval(struct hclge_hw *hw, struct hclge_desc *desc, return hclge_cmd_convert_err_code(desc_ret); } +static int hclge_cmd_check_result(struct hclge_hw *hw, struct hclge_desc *desc, + int num, int ntc) +{ + struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw); + bool is_completed = false; + u32 timeout = 0; + int handle, ret; + + /** + * If the command is sync, wait for the firmware to write back, + * if multi descriptors to be sent, use the first one to check + */ + if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) { + do { + if (hclge_cmd_csq_done(hw)) { + is_completed = true; + break; + } + udelay(1); + timeout++; + } while (timeout < hw->cmq.tx_timeout); + } + + if (!is_completed) + ret = -EBADE; + else + ret = hclge_cmd_check_retval(hw, desc, num, ntc); + + /* Clean the command send queue */ + handle = hclge_cmd_csq_clean(hw); + if (handle < 0) + ret = handle; + else if (handle != num) + dev_warn(&hdev->pdev->dev, + "cleaned %d, need to clean %d\n", handle, num); + return ret; +} + /** * hclge_cmd_send - send command to command queue * @hw: pointer to the hw struct @@ -256,11 +310,7 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) { struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw); struct hclge_cmq_ring *csq = &hw->cmq.csq; - struct hclge_desc *desc_to_use; - bool complete = false; - u32 timeout = 0; - int handle = 0; - int retval; + int ret; int ntc; spin_lock_bh(&hw->cmq.csq.lock); @@ -284,49 +334,17 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) * which will be use for hardware to write back */ ntc = hw->cmq.csq.next_to_use; - while (handle < num) { - desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use]; - *desc_to_use = desc[handle]; - (hw->cmq.csq.next_to_use)++; - if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num) - hw->cmq.csq.next_to_use = 0; - handle++; - } + + hclge_cmd_copy_desc(hw, desc, num); /* Write to hardware */ hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use); - /** - * If the command is sync, wait for the firmware to write back, - * if multi descriptors to be sent, use the first one to check - */ - if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) { - do { - if (hclge_cmd_csq_done(hw)) { - complete = true; - break; - } - udelay(1); - timeout++; - } while (timeout < hw->cmq.tx_timeout); - } - - if (!complete) - retval = -EBADE; - else - retval = hclge_cmd_check_retval(hw, desc, num, ntc); - - /* Clean the command send queue */ - handle = hclge_cmd_csq_clean(hw); - if (handle < 0) - retval = handle; - else if (handle != num) - dev_warn(&hdev->pdev->dev, - "cleaned %d, need to clean %d\n", handle, num); + ret = hclge_cmd_check_result(hw, desc, num, ntc); spin_unlock_bh(&hw->cmq.csq.lock); - return retval; + return ret; } static void hclge_set_default_capability(struct hclge_dev *hdev) -- 2.25.1

1 4

Re: [PATCH for-next 00/32] spin lock usage optimization for SCSI drivers
by Song Bao Hua (Barry Song) 12 Feb '21

12 Feb '21

> > > > On Wed, 10 Feb 2021, Song Bao Hua (Barry Song) wrote: > > > > > > On Wed, 10 Feb 2021, Song Bao Hua (Barry Song) wrote: > > > > > > > > > > On Wed, 10 Feb 2021, Song Bao Hua (Barry Song) wrote: > > > > > > > > > > > > > > There is no warning from m68k builds. That's because > > > > > > > > arch_irqs_disabled() returns true when the IPL is non-zero. > > > > > > > > > > > > > > So for m68k, the case is arch_irqs_disabled() is true, but > > > > > > > interrupts can still come? > > > > > > > > > > > > > > Then it seems it is very confusing. If prioritized interrupts > > > > > > > can still come while arch_irqs_disabled() is true, > > > > > > > > > > > > Yes, on m68k CPUs, an IRQ having a priority level higher than the > > > > > > present priority mask will get serviced. > > > > > > > > > > > > Non-Maskable Interrupt (NMI) is not subject to this rule and gets > > > > > > serviced regardless. > > > > > > > > > > > > > how could spin_lock_irqsave() block the prioritized interrupts? > > > > > > > > > > > > It raises the the mask level to 7. Again, please see > > > > > > arch/m68k/include/asm/irqflags.h > > > > > > > > > > Hi Finn, > > > > > Thanks for your explanation again. > > > > > > > > > > TBH, that is why m68k is so confusing. irqs_disabled() on m68k > > > > > should just reflect the status of all interrupts have been disabled > > > > > except NMI. > > > > > > > > > > irqs_disabled() should be consistent with the calling of APIs such > > > > > as local_irq_disable, local_irq_save, spin_lock_irqsave etc. > > > > > > > > > > > > > When irqs_disabled() returns true, we cannot infer that > > > > arch_local_irq_disable() was called. But I have not yet found driver > > > > code or core kernel code attempting that inference. > > > > > > > > > > > > > > > > > Isn't arch_irqs_disabled() a status reflection of irq disable > > > > > > > API? > > > > > > > > > > > > > > > > > > > Why not? > > > > > > > > > > If so, arch_irqs_disabled() should mean all interrupts have been > > > > > masked except NMI as NMI is unmaskable. > > > > > > > > > > > > > Can you support that claim with a reference to core kernel code or > > > > documentation? (If some arch code agrees with you, that's neither here > > > > nor there.) > > > > > > I think those links I share you have supported this. Just you don't > > > believe :-) > > > > > > > Your links show that the distinction between fast and slow handlers was > > removed. Your links don't support your claim that "arch_irqs_disabled() > > should mean all interrupts have been masked". Where is the code that makes > > that inference? Where is the documentation that supports your claim? > > (1) > https://lwn.net/Articles/380931/ > Looking at all these worries, one might well wonder if a system which *disabled > interrupts for all handlers* would function well at all. So it is interesting > to note one thing: any system which has the lockdep locking checker enabled > has been running all handlers that way for some years now. Many developers > and testers run lockdep-enabled kernels, and they are available for some of > the more adventurous distributions (Rawhide, for example) as well. So we > have quite a bit of test coverage for this mode of operation already. > > (2) > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/ > ?id=b738a50a > > "We run all handlers *with interrupts disabled* and expect them not to > enable them. Warn when we catch one who does." > > (3) > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/ > ?id=e58aa3d2d0cc > genirq: Run irq handlers *with interrupts disabled* > > Running interrupt handlers with interrupts enabled can cause stack > overflows. That has been observed with multiqueue NICs delivering all > their interrupts to a single core. We might band aid that somehow by > checking the interrupt stacks, but the real safe fix is to *run the irq > handlers with interrupts disabled*. > > > All these documents say we are running irq handler with interrupts > disabled. but it seems you think high-prio interrupts don't belong > to "interrupts" in those documents :-) > > that is why we can't get agreement. I think "interrupts" mean > all except NMI in these documents, but you insist high-prio IRQ > is an exception. > > > > > > > > > > > > > > > > > > > Are all interrupts (including NMI) masked whenever > > > > > > arch_irqs_disabled() returns true on your platforms? > > > > > > > > > > On my platform, once irqs_disabled() is true, all interrupts are > > > > > masked except NMI. NMI just ignore spin_lock_irqsave or > > > > > local_irq_disable. > > > > > > > > > > On ARM64, we also have high-priority interrupts, but they are > > > > > running as PESUDO_NMI: > > > > > https://lwn.net/Articles/755906/ > > > > > > > > > > > > > A glance at the ARM GIC specification suggests that your hardware > > > > works much like 68000 hardware. > > > > > > > > When enabled, a CPU interface takes the highest priority pending > > > > interrupt for its connected processor and determines whether the > > > > interrupt has sufficient priority for it to signal the interrupt > > > > request to the processor. [...] > > > > > > > > When the processor acknowledges the interrupt at the CPU interface, > > > > the Distributor changes the status of the interrupt from pending to > > > > either active, or active and pending. At this point the CPU > > > > interface can signal another interrupt to the processor, to preempt > > > > interrupts that are active on the processor. If there is no pending > > > > interrupt with sufficient priority for signaling to the processor, > > > > the interface deasserts the interrupt request signal to the > > > > processor. > > > > > > > > https://developer.arm.com/documentation/ihi0048/b/ > > > > > > > > Have you considered that Linux/arm might benefit if it could fully > > > > exploit hardware features already available, such as the interrupt > > > > priority masking feature in the GIC in existing arm systems? > > > > > > I guess no:-) there are only two levels: IRQ and NMI. Injecting a > > > high-prio IRQ level between them makes no sense. > > > > > > To me, arm64's design is quite clear and has no any confusion. > > > > > > > Are you saying that the ARM64 hardware design is confusing because it > > implements a priority mask, and that's why you had to simplify it with a > > pseudo-nmi scheme in software? > > No, I was not saying this. I think both m68k and arm64 have good hardware > design. Just Linux's implementation is running irq-handlers with interrupts > disabled. So ARM64's pseudo-nmi is adapted to Linux better. > > > > > > > > > > > > On m68k, it seems you mean： > > > > > irq_disabled() is true, but high-priority interrupts can still come; > > > > > local_irq_disable() can disable high-priority interrupts, and at that > > > > > time, irq_disabled() is also true. > > > > > > > > > > TBH, this is wrong and confusing on m68k. > > > > > > > > > > > > > Like you, I was surprised when I learned about it. But that doesn't mean > > > > it's wrong. The fact that it works should tell you something. > > > > > > > > > > The fact is that m68k lets arch_irq_disabled() return true to pretend > > > all IRQs are disabled while high-priority IRQ is still open, thus "pass" > > > all sanitizing check in genirq and kernel core. > > > > > > > The fact is that m68k has arch_irq_disabled() return false when all IRQs > > are enabled. So there is no bug. > > But it has arch_irq_disabled() return true while some interrupts(not NMI) > are still open. > > > > > > > Things could always be made simpler. But discarding features isn't > > > > necessarily an improvement. > > > > > > This feature could be used by calling local_irq_enable_in_hardirq() in > > > those IRQ handlers who hope high-priority interrupts to preempt it for a > > > while. > > > > > > > So, if one handler is sensitive to interrupt latency, all other handlers > > should be modified? I don't think that's workable. > > I think we just enable preempt_rt or force threaded_irq, and then improve > the priority of the irq thread who is sensitive to latency. No need to > touch all threads. > > I also understand your point, we let one high-prio interrupt preempt > low priority interrupt, then we don't need to change the whole system. > But I think Linux prefers the method of threaded_irq or preempt_rt > for this kind of problems. > > > > > In anycase, what you're describing is a completely different nested > > interrupt scheme that would defeat the priority level mechanism that the > > hardware provides us with. > > Yes. Indeed. > > > > > > It shouldn't hide somewhere and make confusion. > > > > > > > The problem is hiding so well that no-one has found it! I say it doesn't > > exist. > > Long long ago(before 2.6.38), we had a kernel supporting IRQF_DISABLED and > nested interrupts were widely supported, but system also ran well in most > cases. That means nested interrupts don't really matter in most cases. > That is why m68k is also running well even though it is still nesting. > > > > > > On the other hand, those who care about realtime should use threaded IRQ > > > and let IRQ threads preempt each other. > > > > > > > Yes. And those threads also have priority levels. > > Finn, I am not a m68k guy, would you help check if this could activate a > warning on m68k. maybe we can discuss this question in genirq maillist from > this warning if you are happy. Thanks very much. > > diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h > index 7c9d6a2d7e90..b8ca27555c76 100644 > --- a/include/linux/hardirq.h > +++ b/include/linux/hardirq.h > @@ -32,6 +32,7 @@ static __always_inline void rcu_irq_enter_check_tick(void) > */ > #define __irq_enter() \ > do { \ > + WARN_ONCE(in_hardirq() && irqs_disabled(), "nested > interrupts\n"); \ > preempt_count_add(HARDIRQ_OFFSET); \ > lockdep_hardirq_enter(); \ > account_hardirq_enter(current); \ > @@ -44,6 +45,7 @@ static __always_inline void rcu_irq_enter_check_tick(void) > */ > #define __irq_enter_raw() \ > do { \ > + WARN_ONCE(in_hardirq() && irqs_disabled(), "nested > interrupts\n"); \ > preempt_count_add(HARDIRQ_OFFSET); \ > lockdep_hardirq_enter(); \ > } while (0) > I am not a m68k guy, here I can show you some code in cortex-m, which supports full interrupt priority preemption in hardware, but its arch code just disables it to satisfy Linux: arch/arm/kernel/entry-header.S .macro v7m_exception_entry ... @ Linux expects to have irqs off. Do it here before taking stack space cpsid i arch/arm/kernel/entry-v7m.S __irq_entry: v7m_exception_entry @ @ Invoke the IRQ handler @ ... @ routine called with r0 = irq number, r1 = struct pt_regs * bl nvic_handle_irq pop {lr} Another example in arch/arc/kernel/entry-arcv2.S: ENTRY(handle_interrupt) INTERRUPT_PROLOGUE # irq control APIs local_irq_save/restore/disable/enable fiddle with # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) # However a taken interrupt doesn't clear these bits. Thus irqs_disabled() # query in hard ISR path would return false (since .IE is set) which would # trips genirq interrupt handling asserts. # # So do a "soft" disable of interrutps here. # # Note this disable is only for consistent book-keeping as further interrupts # will be disabled anyways even w/o this. Hardware tracks active interrupts # seperately in AUX_IRQ_ACT.active and will not take new interrupts # unless this one returns (or higher prio becomes pending in 2-prio scheme) IRQ_DISABLE ; icause is banked: one per priority level ; so a higher prio interrupt taken here won't clobber prev prio icause lr r0, [ICAUSE] mov blink, ret_from_exception b.d arch_do_IRQ mov r1, sp Actually in m68k, I also saw its IRQ entry disabled interrupts by ' move #0x2700,%sr /* disable intrs */' arch/m68k/include/asm/entry.h: .macro SAVE_ALL_SYS move #0x2700,%sr /* disable intrs */ btst #5,%sp@(2) /* from user? */ bnes 6f /* no, skip */ movel %sp,sw_usp /* save user sp */ ... .macro SAVE_ALL_INT SAVE_ALL_SYS moveq #-1,%d0 /* not system call entry */ movel %d0,%sp@(PT_OFF_ORIG_D0) .endm arch/m68k/kernel/entry.S: /* This is the main interrupt handler for autovector interrupts */ ENTRY(auto_inthandler) SAVE_ALL_INT GET_CURRENT(%d0) | put exception # in d0 bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0 subw #VEC_SPUR,%d0 movel %sp,%sp@- movel %d0,%sp@- | put vector # on stack auto_irqhandler_fixup = . + 2 jsr do_IRQ | process the IRQ addql #8,%sp | pop parameters off stack jra ret_from_exception So my question is that " move #0x2700,%sr" is actually disabling all interrupts? And is m68k actually running irq handlers with interrupts disabled? Best Regards Barry

2 4

[PATCH v3 for-next] RDMA/hns: Adjust definition of FRMR fields
by Weihang Li 11 Feb '21

11 Feb '21

From: Yixing Liu <liuyixing1(a)huawei.com> FRMR is not well-supported on HIP08, it is re-designed for HIP09 and the position of related fields is changed. Then the ULPs should be forbidden to use FRMR on older hardwares. Signed-off-by: Yixing Liu <liuyixing1(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- This patch is one of series "RDMA/hns: Updates for 5.12", the others have been applied. Changes since v2: * Aovid setting IB_DEVICE_MEM_MGT_EXTENSIONS for HIP08 or older hardwares. * Link: https://patchwork.kernel.org/project/linux-rdma/patch/1612859923-44041-1-gi… Changes since v1: * Add check for HW version and rewrite the description. * Link: https://patchwork.kernel.org/project/linux-rdma/patch/1612517974-31867-6-gi… drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 45 +++++++++++++++++------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 12 ++++---- drivers/infiniband/hw/hns/hns_roce_main.c | 3 +- 3 files changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 012076a..c3934ab 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -99,16 +99,16 @@ static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, u64 pbl_ba; /* use ib_access_flags */ - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S, - wr->access & IB_ACCESS_MW_BIND ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S, - wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S, - wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S, - wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S, - wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_BIND_EN_S, + !!(wr->access & IB_ACCESS_MW_BIND)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_ATOMIC_S, + !!(wr->access & IB_ACCESS_REMOTE_ATOMIC)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_RR_S, + !!(wr->access & IB_ACCESS_REMOTE_READ)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_RW_S, + !!(wr->access & IB_ACCESS_REMOTE_WRITE)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_LW_S, + !!(wr->access & IB_ACCESS_LOCAL_WRITE)); /* Data structure reuse may lead to confusion */ pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; @@ -121,12 +121,10 @@ static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); fseg->pbl_size = cpu_to_le32(mr->npages); - roce_set_field(fseg->mode_buf_pg_sz, - V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, + roce_set_field(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S, to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); - roce_set_bit(fseg->mode_buf_pg_sz, - V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); } static void set_atomic_seg(const struct ib_send_wr *wr, @@ -522,10 +520,12 @@ static inline int set_ud_wqe(struct hns_roce_qp *qp, return 0; } -static int set_rc_opcode(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, +static int set_rc_opcode(struct hns_roce_dev *hr_dev, + struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, const struct ib_send_wr *wr) { u32 ib_op = wr->opcode; + int ret = 0; rc_sq_wqe->immtdata = get_immtdata(wr); @@ -545,7 +545,10 @@ static int set_rc_opcode(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); break; case IB_WR_REG_MR: - set_frmr_seg(rc_sq_wqe, reg_wr(wr)); + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) + set_frmr_seg(rc_sq_wqe, reg_wr(wr)); + else + ret = -EOPNOTSUPP; break; case IB_WR_LOCAL_INV: roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); @@ -554,19 +557,23 @@ static int set_rc_opcode(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); break; default: - return -EINVAL; + ret = -EINVAL; } + if (unlikely(ret)) + return ret; + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); - return 0; + return ret; } static inline int set_rc_wqe(struct hns_roce_qp *qp, const struct ib_send_wr *wr, void *wqe, unsigned int *sge_idx, unsigned int owner_bit) { + struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; unsigned int curr_idx = *sge_idx; unsigned int valid_num_sge; @@ -577,7 +584,7 @@ static inline int set_rc_wqe(struct hns_roce_qp *qp, rc_sq_wqe->msg_len = cpu_to_le32(msg_len); - ret = set_rc_opcode(rc_sq_wqe, wr); + ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); if (WARN_ON(ret)) return ret; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 7a0f8ac..39621fb 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -1255,15 +1255,15 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 -#define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19 +#define V2_RC_FRMR_WQE_BYTE_40_BIND_EN_S 10 -#define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20 +#define V2_RC_FRMR_WQE_BYTE_40_ATOMIC_S 11 -#define V2_RC_FRMR_WQE_BYTE_4_RR_S 21 +#define V2_RC_FRMR_WQE_BYTE_40_RR_S 12 -#define V2_RC_FRMR_WQE_BYTE_4_RW_S 22 +#define V2_RC_FRMR_WQE_BYTE_40_RW_S 13 -#define V2_RC_FRMR_WQE_BYTE_4_LW_S 23 +#define V2_RC_FRMR_WQE_BYTE_40_LW_S 14 #define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31 @@ -1280,7 +1280,7 @@ struct hns_roce_v2_rc_send_wqe { struct hns_roce_wqe_frmr_seg { __le32 pbl_size; - __le32 mode_buf_pg_sz; + __le32 byte_40; }; #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4 diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c index c29215a..c9c0836 100644 --- a/drivers/infiniband/hw/hns/hns_roce_main.c +++ b/drivers/infiniband/hw/hns/hns_roce_main.c @@ -201,7 +201,8 @@ static int hns_roce_query_device(struct ib_device *ib_dev, props->max_srq_sge = hr_dev->caps.max_srq_sges; } - if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) { + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR && + hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; } -- 2.8.1

2 1

[PATCH for next v1 0/2] gpio: few clean up patches to replace spin_lock_irqsave with spin_lock
by Luo Jiaxing 10 Feb '21

10 Feb '21

There is no need to use API with _irqsave in hard IRQ handler, So replace those with spin_lock. Luo Jiaxing (2): gpio: omap: Replace raw_spin_lock_irqsave with raw_spin_lock in omap_gpio_irq_handler() gpio: grgpio: Replace spin_lock_irqsave with spin_lock in grgpio_irq_handler() drivers/gpio/gpio-grgpio.c | 5 ++--- drivers/gpio/gpio-omap.c | 15 ++++++--------- 2 files changed, 8 insertions(+), 12 deletions(-) -- 2.7.4

2 3

[PATCH v2 0/4] Use subdir-ccflags-* to inherit debug flag
by Yicong Yang 10 Feb '21

10 Feb '21

Few drivers use ccflags-* in their top directory to enable -DDEBUG, but don't have config options to enable debug in the sub-directories, or they use per subdirectory ccflags-* to have DEBUG with the same kconfig option. Considering they intends to enable debug for all the files under the directory with the same kconfig option, it will be clearer to use subdir-ccflags-* instead of ccflags-* to inherit the debug settings from Kconfig when traversing subdirectories. We primarily find this issue when debugging PCIe and thought other drivers may also have this issues. Previous discussion can be find at https://lore.kernel.org/linux-pci/1612438215-33105-1-git-send-email-yangyic… Change since v1: - reword the commits to illustrate the reasons of the change and the benefits. v1: https://lore.kernel.org/lkml/1612518255-23052-1-git-send-email-yangyicong@h… Junhao He (4): driver core: Use subdir-ccflags-* to inherit debug flag hwmon: Use subdir-ccflags-* to inherit debug flag pps: Use subdir-ccflags-* to inherit debug flag staging: comedi: Use subdir-ccflags-* to inherit debug flag drivers/base/Makefile | 2 +- drivers/base/power/Makefile | 2 -- drivers/hwmon/Makefile | 2 +- drivers/pps/Makefile | 2 +- drivers/staging/comedi/Makefile | 2 +- drivers/staging/comedi/drivers/Makefile | 1 - drivers/staging/comedi/drivers/tests/Makefile | 2 -- drivers/staging/comedi/kcomedilib/Makefile | 2 -- 8 files changed, 4 insertions(+), 11 deletions(-) -- 2.8.1

3 7

[PATCH v3] sched/topology: fix the issue groups don't span domain->span for NUMA diameter > 2
by Barry Song 10 Feb '21

10 Feb '21

As long as NUMA diameter > 2, building sched_domain by sibling's child domain will definitely create a sched_domain with sched_group which will span out of the sched_domain: +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 node2 node3 domain1 node0+1 node0+1 node2+3 node2+3 + domain2 node0+1+2 | group: node0+1 | group:node2+3 <-------------------+ when node2 is added into the domain2 of node0, kernel is using the child domain of node2's domain2, which is domain1(node2+3). Node 3 is outside the span of the domain including node0+1+2. This will make load_balance() run based on screwed avg_load and group_type in the sched_group spanning out of the sched_domain, and it also makes select_task_rq_fair() pick an idle CPU outside the sched_domain. Real servers which suffer from this problem include Kunpeng920 and 8-node Sun Fire X4600-M2, at least. Here we move to use the *child* domain of the *child* domain of node2's domain2 as the new added sched_group. At the same, we re-use the lower level sgc directly. +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 +- node2 node3 | domain1 node0+1 node0+1 | node2+3 node2+3 | domain2 node0+1+2 | group: node0+1 | group:node2 <-------------------+ Tested by the below topology: qemu-system-aarch64 -M virt -nographic \ -smp cpus=8 \ -numa node,cpus=0-1,nodeid=0 \ -numa node,cpus=2-3,nodeid=1 \ -numa node,cpus=4-5,nodeid=2 \ -numa node,cpus=6-7,nodeid=3 \ -numa dist,src=0,dst=1,val=12 \ -numa dist,src=0,dst=2,val=20 \ -numa dist,src=0,dst=3,val=22 \ -numa dist,src=1,dst=2,val=22 \ -numa dist,src=2,dst=3,val=12 \ -numa dist,src=1,dst=3,val=24 \ -m 4G -cpu cortex-a57 -kernel arch/arm64/boot/Image w/o patch, we get lots of "groups don't span domain->span": [ 0.802139] CPU0 attaching sched-domain(s): [ 0.802193] domain-0: span=0-1 level=MC [ 0.802443] groups: 0:{ span=0 cap=1013 }, 1:{ span=1 cap=979 } [ 0.802693] domain-1: span=0-3 level=NUMA [ 0.802731] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.802811] domain-2: span=0-5 level=NUMA [ 0.802829] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.802881] ERROR: groups don't span domain->span [ 0.803058] domain-3: span=0-7 level=NUMA [ 0.803080] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804055] CPU1 attaching sched-domain(s): [ 0.804072] domain-0: span=0-1 level=MC [ 0.804096] groups: 1:{ span=1 cap=979 }, 0:{ span=0 cap=1013 } [ 0.804152] domain-1: span=0-3 level=NUMA [ 0.804170] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.804219] domain-2: span=0-5 level=NUMA [ 0.804236] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.804302] ERROR: groups don't span domain->span [ 0.804520] domain-3: span=0-7 level=NUMA [ 0.804546] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804677] CPU2 attaching sched-domain(s): [ 0.804687] domain-0: span=2-3 level=MC [ 0.804705] groups: 2:{ span=2 cap=934 }, 3:{ span=3 cap=1009 } [ 0.804754] domain-1: span=0-3 level=NUMA [ 0.804772] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.804820] domain-2: span=0-5 level=NUMA [ 0.804836] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.804944] ERROR: groups don't span domain->span [ 0.805108] domain-3: span=0-7 level=NUMA [ 0.805134] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805223] CPU3 attaching sched-domain(s): [ 0.805232] domain-0: span=2-3 level=MC [ 0.805249] groups: 3:{ span=3 cap=1009 }, 2:{ span=2 cap=934 } [ 0.805319] domain-1: span=0-3 level=NUMA [ 0.805336] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.805383] domain-2: span=0-5 level=NUMA [ 0.805399] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.805458] ERROR: groups don't span domain->span [ 0.805605] domain-3: span=0-7 level=NUMA [ 0.805626] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805712] CPU4 attaching sched-domain(s): [ 0.805721] domain-0: span=4-5 level=MC [ 0.805738] groups: 4:{ span=4 cap=984 }, 5:{ span=5 cap=924 } [ 0.805787] domain-1: span=4-7 level=NUMA [ 0.805803] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.805851] domain-2: span=0-1,4-7 level=NUMA [ 0.805867] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.805915] ERROR: groups don't span domain->span [ 0.806108] domain-3: span=0-7 level=NUMA [ 0.806130] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.806214] CPU5 attaching sched-domain(s): [ 0.806222] domain-0: span=4-5 level=MC [ 0.806240] groups: 5:{ span=5 cap=924 }, 4:{ span=4 cap=984 } [ 0.806841] domain-1: span=4-7 level=NUMA [ 0.806866] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.806934] domain-2: span=0-1,4-7 level=NUMA [ 0.806953] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.807004] ERROR: groups don't span domain->span [ 0.807312] domain-3: span=0-7 level=NUMA [ 0.807386] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.807686] CPU6 attaching sched-domain(s): [ 0.807710] domain-0: span=6-7 level=MC [ 0.807750] groups: 6:{ span=6 cap=1017 }, 7:{ span=7 cap=1012 } [ 0.807840] domain-1: span=4-7 level=NUMA [ 0.807870] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.807952] domain-2: span=0-1,4-7 level=NUMA [ 0.807985] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.808045] ERROR: groups don't span domain->span [ 0.808257] domain-3: span=0-7 level=NUMA [ 0.808571] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6125 }, 2:{ span=0-5 mask=2-3 cap=5899 } [ 0.808848] CPU7 attaching sched-domain(s): [ 0.808860] domain-0: span=6-7 level=MC [ 0.808880] groups: 7:{ span=7 cap=1012 }, 6:{ span=6 cap=1017 } [ 0.808953] domain-1: span=4-7 level=NUMA [ 0.808974] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.809034] domain-2: span=0-1,4-7 level=NUMA [ 0.809055] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.809128] ERROR: groups don't span domain->span [ 0.810361] domain-3: span=0-7 level=NUMA [ 0.810400] groups: 6:{ span=0-1,4-7 mask=6-7 cap=5961 }, 2:{ span=0-5 mask=2-3 cap=5903 } w/ patch, we don't get "groups don't span domain->span" any more: [ 1.486271] CPU0 attaching sched-domain(s): [ 1.486820] domain-0: span=0-1 level=MC [ 1.500924] groups: 0:{ span=0 cap=980 }, 1:{ span=1 cap=994 } [ 1.515717] domain-1: span=0-3 level=NUMA [ 1.515903] groups: 0:{ span=0-1 cap=1974 }, 2:{ span=2-3 cap=1989 } [ 1.516989] domain-2: span=0-5 level=NUMA [ 1.517124] groups: 0:{ span=0-3 cap=3963 }, 4:{ span=4-5 cap=1949 } [ 1.517369] domain-3: span=0-7 level=NUMA [ 1.517423] groups: 0:{ span=0-5 mask=0-1 cap=5912 }, 6:{ span=4-7 mask=6-7 cap=4054 } [ 1.520027] CPU1 attaching sched-domain(s): [ 1.520097] domain-0: span=0-1 level=MC [ 1.520184] groups: 1:{ span=1 cap=994 }, 0:{ span=0 cap=980 } [ 1.520429] domain-1: span=0-3 level=NUMA [ 1.520487] groups: 0:{ span=0-1 cap=1974 }, 2:{ span=2-3 cap=1989 } [ 1.520687] domain-2: span=0-5 level=NUMA [ 1.520744] groups: 0:{ span=0-3 cap=3963 }, 4:{ span=4-5 cap=1949 } [ 1.520948] domain-3: span=0-7 level=NUMA [ 1.521038] groups: 0:{ span=0-5 mask=0-1 cap=5912 }, 6:{ span=4-7 mask=6-7 cap=4054 } [ 1.522068] CPU2 attaching sched-domain(s): [ 1.522348] domain-0: span=2-3 level=MC [ 1.522606] groups: 2:{ span=2 cap=1003 }, 3:{ span=3 cap=986 } [ 1.522832] domain-1: span=0-3 level=NUMA [ 1.522885] groups: 2:{ span=2-3 cap=1989 }, 0:{ span=0-1 cap=1974 } [ 1.523043] domain-2: span=0-5 level=NUMA [ 1.523092] groups: 2:{ span=0-3 mask=2-3 cap=4037 }, 4:{ span=4-5 cap=1949 } [ 1.523302] domain-3: span=0-7 level=NUMA [ 1.523352] groups: 2:{ span=0-5 mask=2-3 cap=5986 }, 6:{ span=0-1,4-7 mask=6-7 cap=6102 } [ 1.523748] CPU3 attaching sched-domain(s): [ 1.523774] domain-0: span=2-3 level=MC [ 1.523825] groups: 3:{ span=3 cap=986 }, 2:{ span=2 cap=1003 } [ 1.524009] domain-1: span=0-3 level=NUMA [ 1.524086] groups: 2:{ span=2-3 cap=1989 }, 0:{ span=0-1 cap=1974 } [ 1.524281] domain-2: span=0-5 level=NUMA [ 1.524331] groups: 2:{ span=0-3 mask=2-3 cap=4037 }, 4:{ span=4-5 cap=1949 } [ 1.524534] domain-3: span=0-7 level=NUMA [ 1.524586] groups: 2:{ span=0-5 mask=2-3 cap=5986 }, 6:{ span=0-1,4-7 mask=6-7 cap=6102 } [ 1.524847] CPU4 attaching sched-domain(s): [ 1.524873] domain-0: span=4-5 level=MC [ 1.524954] groups: 4:{ span=4 cap=958 }, 5:{ span=5 cap=991 } [ 1.525105] domain-1: span=4-7 level=NUMA [ 1.525153] groups: 4:{ span=4-5 cap=1949 }, 6:{ span=6-7 cap=2006 } [ 1.525368] domain-2: span=0-1,4-7 level=NUMA [ 1.525428] groups: 4:{ span=4-7 cap=3955 }, 0:{ span=0-1 cap=1974 } [ 1.532726] domain-3: span=0-7 level=NUMA [ 1.532811] groups: 4:{ span=0-1,4-7 mask=4-5 cap=6003 }, 2:{ span=0-3 mask=2-3 cap=4037 } [ 1.534125] CPU5 attaching sched-domain(s): [ 1.534159] domain-0: span=4-5 level=MC [ 1.534303] groups: 5:{ span=5 cap=991 }, 4:{ span=4 cap=958 } [ 1.534490] domain-1: span=4-7 level=NUMA [ 1.534572] groups: 4:{ span=4-5 cap=1949 }, 6:{ span=6-7 cap=2006 } [ 1.534734] domain-2: span=0-1,4-7 level=NUMA [ 1.534783] groups: 4:{ span=4-7 cap=3955 }, 0:{ span=0-1 cap=1974 } [ 1.536057] domain-3: span=0-7 level=NUMA [ 1.536430] groups: 4:{ span=0-1,4-7 mask=4-5 cap=6003 }, 2:{ span=0-3 mask=2-3 cap=3896 } [ 1.536815] CPU6 attaching sched-domain(s): [ 1.536846] domain-0: span=6-7 level=MC [ 1.536934] groups: 6:{ span=6 cap=1005 }, 7:{ span=7 cap=1001 } [ 1.537144] domain-1: span=4-7 level=NUMA [ 1.537262] groups: 6:{ span=6-7 cap=2006 }, 4:{ span=4-5 cap=1949 } [ 1.537553] domain-2: span=0-1,4-7 level=NUMA [ 1.537613] groups: 6:{ span=4-7 mask=6-7 cap=4054 }, 0:{ span=0-1 cap=1805 } [ 1.537872] domain-3: span=0-7 level=NUMA [ 1.537998] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6102 }, 2:{ span=0-5 mask=2-3 cap=5845 } [ 1.538448] CPU7 attaching sched-domain(s): [ 1.538505] domain-0: span=6-7 level=MC [ 1.538586] groups: 7:{ span=7 cap=1001 }, 6:{ span=6 cap=1005 } [ 1.538746] domain-1: span=4-7 level=NUMA [ 1.538798] groups: 6:{ span=6-7 cap=2006 }, 4:{ span=4-5 cap=1949 } [ 1.539048] domain-2: span=0-1,4-7 level=NUMA [ 1.539111] groups: 6:{ span=4-7 mask=6-7 cap=4054 }, 0:{ span=0-1 cap=1805 } [ 1.539571] domain-3: span=0-7 level=NUMA [ 1.539610] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6102 }, 2:{ span=0-5 mask=2-3 cap=5845 } Reported-by: Valentin Schneider <valentin.schneider(a)arm.com> Tested-by: Meelis Roos <mroos(a)linux.ee> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- -v3: Mainly updated according to Valentin's comments. While the approach was started by me, Valentin contributed the most useful edit and comments. Thanks, Valentin! * fixed a potential issue that re-used sgc might be located in a sched_domain which will be degenrated; * code cleanup to make it more readable While Valentin started another approach which completely removed overlapped sched_group, we both agree that it is better to have a solution which won't touch machines without 3-hops issue first: https://lore.kernel.org/lkml/jhjpn1a232z.mognet@arm.com/ kernel/sched/topology.c | 91 +++++++++++++++++++++++++++-------------- 1 file changed, 61 insertions(+), 30 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 5d3675c7a76b..ab5ebf17f30a 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -723,35 +723,6 @@ cpu_attach_domain(struct sched_domain *sd, struct root_domain *rd, int cpu) for (tmp = sd; tmp; tmp = tmp->parent) numa_distance += !!(tmp->flags & SD_NUMA); - /* - * FIXME: Diameter >=3 is misrepresented. - * - * Smallest diameter=3 topology is: - * - * node 0 1 2 3 - * 0: 10 20 30 40 - * 1: 20 10 20 30 - * 2: 30 20 10 20 - * 3: 40 30 20 10 - * - * 0 --- 1 --- 2 --- 3 - * - * NUMA-3 0-3 N/A N/A 0-3 - * groups: {0-2},{1-3} {1-3},{0-2} - * - * NUMA-2 0-2 0-3 0-3 1-3 - * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} - * - * NUMA-1 0-1 0-2 1-3 2-3 - * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} - * - * NUMA-0 0 1 2 3 - * - * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the - * group span isn't a subset of the domain span. - */ - WARN_ONCE(numa_distance > 2, "Shortest NUMA path spans too many nodes\n"); - sched_domain_debug(sd, cpu); rq_attach_root(rq, rd); @@ -982,6 +953,31 @@ static void init_overlap_sched_group(struct sched_domain *sd, sg->sgc->max_capacity = SCHED_CAPACITY_SCALE; } +static struct sched_domain * +find_descended_sibling(struct sched_domain *sd, struct sched_domain *sibling) +{ + /* + * The proper descendant would be the one whose child won't span out + * of sd + */ + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + sched_domain_span(sd))) + sibling = sibling->child; + + /* + * As we are referencing sgc across different topology level, we need + * to go down to skip those sched_domains which don't contribute to + * scheduling because they will be degenerated in cpu_attach_domain + */ + while (sibling->child && + cpumask_equal(sched_domain_span(sibling->child), + sched_domain_span(sibling))) + sibling = sibling->child; + + return sibling; +} + static int build_overlap_sched_groups(struct sched_domain *sd, int cpu) { @@ -1015,6 +1011,41 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) if (!cpumask_test_cpu(i, sched_domain_span(sibling))) continue; + /* + * Usually we build sched_group by sibling's child sched_domain + * But for machines whose NUMA diameter are 3 or above, we move + * to build sched_group by sibling's proper descendant's child + * domain because sibling's child sched_domain will span out of + * the sched_domain being built as below. + * + * Smallest diameter=3 topology is: + * + * node 0 1 2 3 + * 0: 10 20 30 40 + * 1: 20 10 20 30 + * 2: 30 20 10 20 + * 3: 40 30 20 10 + * + * 0 --- 1 --- 2 --- 3 + * + * NUMA-3 0-3 N/A N/A 0-3 + * groups: {0-2},{1-3} {1-3},{0-2} + * + * NUMA-2 0-2 0-3 0-3 1-3 + * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} + * + * NUMA-1 0-1 0-2 1-3 2-3 + * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} + * + * NUMA-0 0 1 2 3 + * + * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the + * group span isn't a subset of the domain span. + */ + if (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), span)) + sibling = find_descended_sibling(sd, sibling); + sg = build_group_from_child_sched_domain(sibling, cpu); if (!sg) goto fail; @@ -1022,7 +1053,7 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) sg_span = sched_group_span(sg); cpumask_or(covered, covered, sg_span); - init_overlap_sched_group(sd, sg); + init_overlap_sched_group(sibling, sg); if (!first) first = sg; -- 2.25.1

5 6

[PATCH] PCI: Use subdir-ccflags-* to inherit debug flag
by Yicong Yang 10 Feb '21

10 Feb '21

From: Junhao He <hejunhao2(a)hisilicon.com> Use subdir-ccflags-* instead of ccflags-* to inherit the debug settings from Kconfig when traversing subdirectories. Signed-off-by: Junhao He <hejunhao2(a)hisilicon.com> Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> --- drivers/pci/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 11cc794..d62c4ac 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -36,4 +36,4 @@ obj-$(CONFIG_PCI_ENDPOINT) += endpoint/ obj-y += controller/ obj-y += switch/ -ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG +subdir-ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG -- 2.8.1

3 9

[PATCH net-next 00/13] net: hns3: some cleanups for -next
by Huazhong Tan 10 Feb '21

10 Feb '21

To improve code readability and maintainability, the series refactor out some bloated functions in the HNS3 ethernet driver. Hao Chen (1): net: hns3: refactor out hclge_rm_vport_all_mac_table() Huazhong Tan (2): net: hns3: refactor out hclge_set_rss_tuple() net: hns3: refactor out hclgevf_set_rss_tuple() Jian Shen (3): net: hns3: refactor out hclge_get_rss_tuple() net: hns3: refactor out hclgevf_get_rss_tuple() net: hns3: split out hclge_dbg_dump_qos_buf_cfg() Jiaran Zhang (1): net: hns3: use ipv6_addr_any() helper Peng Li (4): net: hns3: refactor out hclge_cmd_convert_err_code() net: hns3: refactor out hclgevf_cmd_convert_err_code() net: hns3: clean up hns3_dbg_cmd_write() net: hns3: refactor out hclge_set_vf_vlan_common() Yufeng Mo (2): net: hns3: split out hclge_cmd_send() net: hns3: split out hclgevf_cmd_send() drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 44 ++-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 155 +++++++------ .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 158 +++++++++---- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 244 ++++++++++++++------- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 194 ++++++++-------- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 114 ++++++---- 6 files changed, 567 insertions(+), 342 deletions(-) -- 2.7.4

1 13

[PATCH v2 for-next] RDMA/hns: Adjust definition of FRMR fields
by Weihang Li 10 Feb '21

10 Feb '21

From: Yixing Liu <liuyixing1(a)huawei.com> FRMR is not well-supported on HIP08, it is re-designed for HIP09 and the position of related fields is changed. Then the ULPs should be forbidden to use FRMR on older hardwares. Signed-off-by: Yixing Liu <liuyixing1(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- This patch is one of series "RDMA/hns: Updates for 5.12", the others have been applied. Changes since v1: * Add check for HW version and rewrite the description. * Link: https://patchwork.kernel.org/project/linux-rdma/patch/1612517974-31867-6-gi… drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 45 +++++++++++++++++------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 12 ++++---- 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index d9f94b4..1789273 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -99,16 +99,16 @@ static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, u64 pbl_ba; /* use ib_access_flags */ - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S, - wr->access & IB_ACCESS_MW_BIND ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S, - wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S, - wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S, - wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0); - roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S, - wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_BIND_EN_S, + !!(wr->access & IB_ACCESS_MW_BIND)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_ATOMIC_S, + !!(wr->access & IB_ACCESS_REMOTE_ATOMIC)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_RR_S, + !!(wr->access & IB_ACCESS_REMOTE_READ)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_RW_S, + !!(wr->access & IB_ACCESS_REMOTE_WRITE)); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_LW_S, + !!(wr->access & IB_ACCESS_LOCAL_WRITE)); /* Data structure reuse may lead to confusion */ pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; @@ -121,12 +121,10 @@ static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); fseg->pbl_size = cpu_to_le32(mr->npages); - roce_set_field(fseg->mode_buf_pg_sz, - V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, + roce_set_field(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S, to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); - roce_set_bit(fseg->mode_buf_pg_sz, - V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); + roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); } static void set_atomic_seg(const struct ib_send_wr *wr, @@ -522,10 +520,12 @@ static inline int set_ud_wqe(struct hns_roce_qp *qp, return 0; } -static int set_rc_opcode(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, +static int set_rc_opcode(struct hns_roce_dev *hr_dev, + struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, const struct ib_send_wr *wr) { u32 ib_op = wr->opcode; + int ret = 0; rc_sq_wqe->immtdata = get_immtdata(wr); @@ -545,7 +545,10 @@ static int set_rc_opcode(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); break; case IB_WR_REG_MR: - set_frmr_seg(rc_sq_wqe, reg_wr(wr)); + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) + set_frmr_seg(rc_sq_wqe, reg_wr(wr)); + else + ret = -EOPNOTSUPP; break; case IB_WR_LOCAL_INV: roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); @@ -554,19 +557,23 @@ static int set_rc_opcode(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); break; default: - return -EINVAL; + ret = -EINVAL; } + if (unlikely(ret)) + return ret; + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); - return 0; + return ret; } static inline int set_rc_wqe(struct hns_roce_qp *qp, const struct ib_send_wr *wr, void *wqe, unsigned int *sge_idx, unsigned int owner_bit) { + struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; unsigned int curr_idx = *sge_idx; unsigned int valid_num_sge; @@ -577,7 +584,7 @@ static inline int set_rc_wqe(struct hns_roce_qp *qp, rc_sq_wqe->msg_len = cpu_to_le32(msg_len); - ret = set_rc_opcode(rc_sq_wqe, wr); + ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); if (WARN_ON(ret)) return ret; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index f29438c..1da980c 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -1255,15 +1255,15 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 -#define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19 +#define V2_RC_FRMR_WQE_BYTE_40_BIND_EN_S 10 -#define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20 +#define V2_RC_FRMR_WQE_BYTE_40_ATOMIC_S 11 -#define V2_RC_FRMR_WQE_BYTE_4_RR_S 21 +#define V2_RC_FRMR_WQE_BYTE_40_RR_S 12 -#define V2_RC_FRMR_WQE_BYTE_4_RW_S 22 +#define V2_RC_FRMR_WQE_BYTE_40_RW_S 13 -#define V2_RC_FRMR_WQE_BYTE_4_LW_S 23 +#define V2_RC_FRMR_WQE_BYTE_40_LW_S 14 #define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31 @@ -1280,7 +1280,7 @@ struct hns_roce_v2_rc_send_wqe { struct hns_roce_wqe_frmr_seg { __le32 pbl_size; - __le32 mode_buf_pg_sz; + __le32 byte_40; }; #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4 -- 2.8.1

3 2

[PATCH V2 net-next 00/11] net: hns3: some cleanups for -next
by Huazhong Tan 10 Feb '21

10 Feb '21

There are some cleanups for the HNS3 ethernet driver. change log: V2: remove previous #3 which should target net. previous version: V1: https://patchwork.kernel.org/project/netdevbpf/cover/1612784382-27262-1-git… Huazhong Tan (2): net: hns3: remove redundant return value of hns3_uninit_all_ring() net: hns3: remove an unused parameter in hclge_vf_rate_param_check() Jian Shen (2): net: hns3: remove redundant client_setup_tc handle net: hns3: cleanup for endian issue for VF RSS Jiaran Zhang (1): net: hns3: modify some unmacthed types print parameter Peng Li (4): net: hns3: remove the shaper param magic number net: hns3: change hclge_parse_speed() param type net: hns3: change hclge_query_bd_num() param type net: hns3: remove unused macro definition Yonglong Liu (1): net: hns3: clean up some incorrect variable types in hclge_dbg_dump_tm_map() Yufeng Mo (1): net: hns3: clean up unnecessary parentheses in macro definitions drivers/net/ethernet/hisilicon/hns3/hnae3.h | 7 +++-- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 +- drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 31 ++++------------------ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 11 ++++---- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 2 +- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 4 +-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 27 ------------------- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 11 ++++---- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 4 +-- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 14 +++++----- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 5 +--- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c | 2 +- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 14 +++++----- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 6 ++--- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 11 ++++---- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 19 ++++++++----- 16 files changed, 61 insertions(+), 109 deletions(-) -- 2.7.4

3 13

[PATCH net 0/3] net: hns3: fixes for -net
by Huazhong Tan 10 Feb '21

10 Feb '21

The parameters sent from vf may be unreliable. If these parameters are used directly, memory overwriting may occur. So this series adds some checks for this case. Yufeng Mo (3): net: hns3: add a check for queue_id in hclge_reset_vf_queue() net: hns3: add a check for tqp_index in hclge_get_ring_chain_from_mbx() net: hns3: add a check for index in hclge_get_rss_key() .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 7 ++++++ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c | 29 +++++++++++++++++++--- 2 files changed, 32 insertions(+), 4 deletions(-) -- 2.7.4

3 5

[PATCH v4 00/12] add IRQF_NO_AUTOEN for request_irq
by Barry Song 10 Feb '21

10 Feb '21

This patchset added IRQF_NO_AUTOEN for request_irq() and converted drivers/input to this new API. Other drivers will be handled afterwards. -v4: remove the irq_settings magic for NOAUTOEN Barry Song (12): genirq: add IRQF_NO_AUTOEN for request_irq Input: ar1021 - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: atmel_mxt_ts - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: melfas_mip4 - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: bu21029_ts - request_irq by IRQF_NO_AUTOEN and remove irq_set_status_flags Input: stmfts - request_irq by IRQF_NO_AUTOEN and remove irq_set_status_flags Input: zinitix - request_irq by IRQF_NO_AUTOEN and remove irq_set_status_flags Input: mms114 - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: wm831x-ts - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: cyttsp - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: tegra-kbc - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: tca6416-keypad - request_irq by IRQF_NO_AUTOEN and remove disable_irq drivers/input/keyboard/tca6416-keypad.c | 3 +-- drivers/input/keyboard/tegra-kbc.c | 5 ++--- drivers/input/touchscreen/ar1021_i2c.c | 5 +---- drivers/input/touchscreen/atmel_mxt_ts.c | 5 ++--- drivers/input/touchscreen/bu21029_ts.c | 4 ++-- drivers/input/touchscreen/cyttsp_core.c | 5 ++--- drivers/input/touchscreen/melfas_mip4.c | 5 ++--- drivers/input/touchscreen/mms114.c | 4 ++-- drivers/input/touchscreen/stmfts.c | 3 +-- drivers/input/touchscreen/wm831x-ts.c | 3 +-- drivers/input/touchscreen/zinitix.c | 4 ++-- include/linux/interrupt.h | 3 +++ kernel/irq/manage.c | 8 +++++++- 13 files changed, 28 insertions(+), 29 deletions(-) -- 2.25.1

2 13

[PATCH v2 for-next 0/5] RDMA/hns: Fix and refactor CMDQ related code
by Weihang Li 10 Feb '21

10 Feb '21

Remove some dead code in process of CMDQ transmission, and fix an issue about missing error code. Changes since v1: * Drop #2 from the v1 series because the compatibility with the firmware needs to be considered. * Link: https://patchwork.kernel.org/project/linux-rdma/cover/1612419786-39173-1-gi… Lang Cheng (5): RDMA/hns: Remove unused member and variable of CMDQ RDMA/hns: Fixes missing error code of CMDQ RDMA/hns: Remove redundant operations on CMDQ RDMA/hns: Adjust fields and variables about CMDQ tail/head RDMA/hns: Refactor process of posting CMDQ drivers/infiniband/hw/hns/hns_roce_common.h | 4 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 125 ++++++++-------------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 5 -- 3 files changed, 37 insertions(+), 97 deletions(-) -- 2.8.1

2 6

[RFC PATCH 0/2] sched/topology: Get rid of overlapping groups
by Valentin Schneider 09 Feb '21

09 Feb '21

Hi folks, My keyboard still hasn't been taken away from me, so I went down and did what I was rambling about in [1]. The preemptive degeneration check is the worst wart, but I think I'll have to sleep on it before I can figure out a better way. Something tells me the increase in group numbers isn't going to make me any friends, so I've included 3/2 which is Barry's approach (with the subset check condensed in a single spot). Cheers, Valentin [1]: http://lore.kernel.org/r/jhj4kiu4hz8.mognet@arm.com Valentin Schneider (2): sched/topology: Get rid of NUMA overlapping groups Revert "sched/topology: Warn when NUMA diameter > 2" kernel/sched/topology.c | 77 +++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 34 deletions(-) -- 2.27.0

2 8

[PATCH for-next 00/12] RDMA/hns: Updates for 5.12
by Weihang Li 09 Feb '21

09 Feb '21

As usual, this series collects some miscellaneous fixes and cleanups at the end of 5.12 for the hns driver: * #1 ~ #3 fix some non-urgent issues. * #4 ~ #6 make some changes on existing features. * #7 ~ #12 are cleanups, just do some refactor and delete dead code. This series is made based on the series named "RDMA/hns: Several fixes and cleanups of RQ/SRQ" which is still being reviewed: https://patchwork.kernel.org/project/linux-rdma/cover/1611997090-48820-1-gi… I'm worried that it will be too late for 5.12 if any patch of this series needs changes, so I send it before the previous one is merged. If there is any comment or merge conflict on it, I will fix them as soon as possible, thanks. Lang Cheng (3): RDMA/hns: Replace wmb&__raw_writeq with writeq RDMA/hns: Move HIP06 related definitions into hns_roce_hw_v1.h RDMA/hns: Avoid unnecessary memset on WQEs in post_send Lijun Ou (1): RDMA/hns: Disable RQ inline by default Weihang Li (2): RDMA/hns: Avoid filling sgid index when modifying QP to RTR RDMA/hns: Fix type of sq_signal_bits Xi Wang (1): RDMA/hns: Add mapped page count checking for MTR Xinhao Liu (2): RDMA/hns: Remove some magic numbers RDMA/hns: Delete redundant judgment when preparing descriptors Yixian Liu (1): RDMA/hns: Remove unnecessary wrap around for EQ's consumer index Yixing Liu (2): RDMA/hns: Adjust definition of FRMR fields RDMA/hns: Skip qp_flow_control_init() for HIP09 drivers/infiniband/hw/hns/hns_roce_device.h | 45 +--------- drivers/infiniband/hw/hns/hns_roce_hem.c | 9 +- drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 31 +++---- drivers/infiniband/hw/hns/hns_roce_hw_v1.h | 43 ++++++++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 125 +++++++++------------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 12 +-- drivers/infiniband/hw/hns/hns_roce_main.c | 16 ---- drivers/infiniband/hw/hns/hns_roce_mr.c | 56 ++++++++----- 8 files changed, 148 insertions(+), 189 deletions(-) -- 2.8.1

3 15

[PATCH v1 0/2] irqchip/gic-v3-its: don't set bitmap for LPI which user didn't allocate
by Luo Jiaxing 09 Feb '21

09 Feb '21

When the number of online CPUs is less than 16, we found that it will fail to allocate 32 MSI interrupts (including 16 affinity interrupts) after the hisi_sas module is unloaded and then reloaded. After analysis, it is found that a bug exists when the ITS releases interrupt resources, and this patch set contains a bugfix patch and a patch for appending debugging information. Luo Jiaxing (2): irqchip/gic-v3-its: don't set bitmap for LPI which user didn't allocate genirq/msi: add an error print when __irq_domain_alloc_irqs() failed drivers/irqchip/irq-gic-v3-its.c | 4 ++++ kernel/irq/msi.c | 1 + 2 files changed, 5 insertions(+) -- 2.7.4

4 5

[PATCH net-next 00/12] net: hns3: some cleanups for -next
by Huazhong Tan 09 Feb '21

09 Feb '21

There are some cleanups for the HNS3 ethernet driver. Huazhong Tan (2): net: hns3: remove redundant return value of hns3_uninit_all_ring() net: hns3: remove an unused parameter in hclge_vf_rate_param_check() Jian Shen (2): net: hns3: remove redundant client_setup_tc handle net: hns3: cleanup for endian issue for VF RSS Jiaran Zhang (1): net: hns3: modify some unmacthed types print parameter Peng Li (4): net: hns3: remove the shaper param magic number net: hns3: change hclge_parse_speed() param type net: hns3: change hclge_query_bd_num() param type net: hns3: remove unused macro definition Yonglong Liu (1): net: hns3: clean up some incorrect variable types in hclge_dbg_dump_tm_map() Yufeng Mo (2): net: hns3: check cmdq message parameters sent from VF net: hns3: clean up unnecessary parentheses in macro definitions drivers/net/ethernet/hisilicon/hns3/hnae3.h | 7 +++-- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 +- drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 31 ++++------------------ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 11 ++++---- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 2 +- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 4 +-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 27 ------------------- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 11 ++++---- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 4 +-- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 21 ++++++++++----- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 5 +--- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c | 31 ++++++++++++++++++---- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 14 +++++----- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 6 ++--- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 11 ++++---- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 19 ++++++++----- 16 files changed, 93 insertions(+), 113 deletions(-) -- 2.7.4

2 14

[dpdk-dev] [Question about 'rte_eth_tx_prepare']
by Chengchang Tang 09 Feb '21

09 Feb '21

Hi, Thomas Monjalon and Ferruh Yigit and others. I have some questions about 'rte_eth_tx_prepare'. When I use TSO offload in bond mode, the checksum error occurs. It is because the bond PMD does not implement 'tx_prepare'. So, it will not invoke the 'tx_prepare' of each PMDs to do prepare for the PMDs. I am not sure whether to add the 'tx_preapre' implementation for the bond PMD or put the process of pseudo header in the apps. And we are now designing the outer UDP cksum offload for HNS3 PMD. I find that many PMDs process these pseudo headers in 'tx_prepare', but does not process the pseudo header for outer UDP checksum offload. Instead, it is processed in csum forward mode of testpmd. Does this mean that the pseudo header should be completed by the apps and the apps does not need to call 'tx_prepare' to avoid repeated processing? (it seems not transplantable) If so, it seems that PMDs need to avoid doing this in 'tx_prepare'. Here are two questions: 1. What functions should be included in the 'tx_prepare' for PMDs? 2. Whether an app must invoke 'rte_eth_tx_prepare' or under which conditions an app must invoke the 'rte_eth_tx_prepare'? Thanks Chengchang Tang

3 3

[PATCH v2 for-next] RDMA/hns: Add support of direct wqe
by Weihang Li 09 Feb '21

09 Feb '21

From: Yixing Liu <liuyixing1(a)huawei.com> Direct wqe is a mechanism to fill wqe directly into the hardware. In the case of light load, the wqe will be filled into pcie bar space of the hardware, this will reduce one memory access operation and therefore reduce the latency. Signed-off-by: Yixing Liu <liuyixing1(a)huawei.com> Signed-off-by: Lang Cheng <chenglang(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- Changes since v1: * Delete an extra blank line. * Link: https://patchwork.kernel.org/project/linux-rdma/patch/1611395717-11081-1-gi… drivers/infiniband/hw/hns/hns_roce_device.h | 6 ++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 44 ++++++++++++++++++++++++++++- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 13 +++++++++ 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index f62851f..907bf71 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -90,6 +90,7 @@ #define HNS_ROCE_MAX_PORTS 6 #define HNS_ROCE_GID_SIZE 16 #define HNS_ROCE_SGE_SIZE 16 +#define HNS_ROCE_DWQE_SIZE 65536 #define HNS_ROCE_HOP_NUM_0 0xff @@ -643,6 +644,10 @@ struct hns_roce_work { u32 queue_num; }; +enum { + HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5), +}; + struct hns_roce_qp { struct ib_qp ibqp; struct hns_roce_wq rq; @@ -984,6 +989,7 @@ struct hns_roce_dev { struct mutex pgdir_mutex; int irq[HNS_ROCE_MAX_IRQ_NUM]; u8 __iomem *reg_base; + void __iomem *mem_base; struct hns_roce_caps caps; struct xarray qp_table_xa; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index a5bbfb1..8ae3317 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -503,6 +503,8 @@ static inline int set_ud_wqe(struct hns_roce_qp *qp, if (ret) return ret; + qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; + set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); /* @@ -635,6 +637,8 @@ static inline void update_sq_db(struct hns_roce_dev *hr_dev, V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); + /* indicates data on new BAR, 0 : SQ doorbell, 1 : DWQE */ + roce_set_bit(sq_db.byte_4, V2_DB_FLAG_S, 0); roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, V2_DB_PARAMETER_IDX_S, qp->sq.head); roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, @@ -644,6 +648,38 @@ static inline void update_sq_db(struct hns_roce_dev *hr_dev, } } +static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, + u64 __iomem *dest) +{ +#define HNS_ROCE_WRITE_TIMES 8 + struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; + struct hnae3_handle *handle = priv->handle; + const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + int i; + + if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) + for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) + writeq_relaxed(*(val + i), dest + i); +} + +static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, + void *wqe) +{ + struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; + + /* All kinds of DirectWQE have the same header field layout */ + roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M, + V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M, + V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, + V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); + + hns_roce_write512(hr_dev, wqe, hr_dev->mem_base + + HNS_ROCE_DWQE_SIZE * qp->ibqp.qp_num); +} + static int hns_roce_v2_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) @@ -710,7 +746,12 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, qp->next_sge = sge_idx; /* Memory barrier */ wmb(); - update_sq_db(hr_dev, qp); + + if (nreq == 1 && qp->sq.head == qp->sq.tail + 1 && + (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) + write_dwqe(hr_dev, qp, wqe); + else + update_sq_db(hr_dev, qp); } spin_unlock_irqrestore(&qp->sq.lock, flags); @@ -6273,6 +6314,7 @@ static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, /* Get info from NIC driver. */ hr_dev->reg_base = handle->rinfo.roce_io_base; + hr_dev->mem_base = handle->rinfo.roce_mem_base; hr_dev->caps.num_ports = 1; hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; hr_dev->iboe.phy_port[0] = 0; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 69bc072..add1816 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -1098,6 +1098,8 @@ struct hns_roce_v2_mpt_entry { #define V2_DB_BYTE_4_CMD_S 24 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) +#define V2_DB_FLAG_S 31 + #define V2_DB_PARAMETER_IDX_S 0 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0) @@ -1194,6 +1196,15 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5 +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5) + +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13 +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13) + +#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15 +#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15) + #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 @@ -1216,6 +1227,8 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23 +#define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31 + #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) -- 2.8.1

2 1

[PATCH for-next 00/12] RDMA/hns: Several fixes and cleanups of RQ/SRQ
by Weihang Li 09 Feb '21

09 Feb '21

There are some issues when using SRQ on HIP08/HIP09, the first part of this series is some fixes on them. In addition, the codes about RQ/SRQ including the creation and post recv flow are a bit hard to understand, they need to be refactored. Lang Cheng (2): RDMA/hns: Allocate one more recv SGE for HIP08 RDMA/hns: Use new interfaces to write SRQC Wenpeng Liang (8): RDMA/hns: Bugfix for checking whether the srq is full when post wr RDMA/hns: Force srq_limit to 0 when creating SRQ RDMA/hns: Fixed wrong judgments in the goto branch RDMA/hns: Remove the reserved WQE of SRQ RDMA/hns: Refactor hns_roce_create_srq() RDMA/hns: Refactor code about SRQ Context RDMA/hns: Refactor hns_roce_v2_post_srq_recv() RDMA/hns: Add verification of QP type when post_recv Xi Wang (2): RDMA/hns: Refactor post recv flow RDMA/hns: Clear remaining unused sges when post_recv drivers/infiniband/hw/hns/hns_roce_device.h | 16 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 407 +++++++++++++++------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 72 +++-- drivers/infiniband/hw/hns/hns_roce_main.c | 3 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 37 ++- drivers/infiniband/hw/hns/hns_roce_srq.c | 329 ++++++++++++---------- 6 files changed, 510 insertions(+), 354 deletions(-) -- 2.8.1

2 13

[PATCH] mmc: cavium: Replace spin_lock_irqsave with spin_lock in hard IRQ
by Xiaofei Tan 08 Feb '21

08 Feb '21

It is redundant to do irqsave and irqrestore in hardIRQ context, where it has been in a irq-disabled context. Signed-off-by: Xiaofei Tan <tanxiaofei(a)huawei.com> --- drivers/mmc/host/cavium.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/cavium.c b/drivers/mmc/host/cavium.c index c5da3aa..4bb8f28 100644 --- a/drivers/mmc/host/cavium.c +++ b/drivers/mmc/host/cavium.c @@ -436,12 +436,11 @@ irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id) { struct cvm_mmc_host *host = dev_id; struct mmc_request *req; - unsigned long flags = 0; u64 emm_int, rsp_sts; bool host_done; if (host->need_irq_handler_lock) - spin_lock_irqsave(&host->irq_handler_lock, flags); + spin_lock(&host->irq_handler_lock); else __acquire(&host->irq_handler_lock); @@ -504,7 +503,7 @@ irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id) host->release_bus(host); out: if (host->need_irq_handler_lock) - spin_unlock_irqrestore(&host->irq_handler_lock, flags); + spin_unlock(&host->irq_handler_lock); else __release(&host->irq_handler_lock); return IRQ_RETVAL(emm_int != 0); -- 2.8.1

2 1

[PATCH for-next 00/32] spin lock usage optimization for SCSI drivers
by Xiaofei Tan 07 Feb '21

07 Feb '21

Replace spin_lock_irqsave with spin_lock in hard IRQ of SCSI drivers. There are no function changes, but may speed up if interrupt happen too often. Xiaofei Tan (32): scsi: 53c700: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ipr: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: lpfc: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qla4xxx: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: BusLogic: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a100u2w: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a2091: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a3000: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: aha1740: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: bfa: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: esp_scsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: gvp11: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: hptiop: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ibmvscsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: initio: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: megaraid: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mac53c94: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mesh: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mvumi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: myrb: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: myrs: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ncr53c8xx: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: nsp32: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: pmcraid: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: pcmcia: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qlogicfas408: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qlogicpti: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: sgiwd93: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: stex: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: vmw_pvscsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: wd719x: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: advansys: Replace spin_lock_irqsave with spin_lock in hard IRQ drivers/scsi/53c700.c | 5 ++-- drivers/scsi/BusLogic.c | 5 ++-- drivers/scsi/a100u2w.c | 5 ++-- drivers/scsi/a2091.c | 5 ++-- drivers/scsi/a3000.c | 5 ++-- drivers/scsi/advansys.c | 5 ++-- drivers/scsi/aha1740.c | 5 ++-- drivers/scsi/bfa/bfad.c | 20 ++++++------- drivers/scsi/esp_scsi.c | 5 ++-- drivers/scsi/gvp11.c | 5 ++-- drivers/scsi/hptiop.c | 5 ++-- drivers/scsi/ibmvscsi/ibmvfc.c | 5 ++-- drivers/scsi/initio.c | 5 ++-- drivers/scsi/ipr.c | 21 ++++++------- drivers/scsi/lpfc/lpfc_sli.c | 49 +++++++++++++------------------ drivers/scsi/mac53c94.c | 5 ++-- drivers/scsi/megaraid.c | 10 +++---- drivers/scsi/megaraid/megaraid_sas_base.c | 5 ++-- drivers/scsi/mesh.c | 5 ++-- drivers/scsi/mvumi.c | 7 ++--- drivers/scsi/myrb.c | 20 +++++-------- drivers/scsi/myrs.c | 15 ++++------ drivers/scsi/ncr53c8xx.c | 5 ++-- drivers/scsi/nsp32.c | 5 ++-- drivers/scsi/pcmcia/sym53c500_cs.c | 5 ++-- drivers/scsi/pmcraid.c | 8 ++--- drivers/scsi/qla4xxx/ql4_isr.c | 15 ++++------ drivers/scsi/qlogicfas408.c | 5 ++-- drivers/scsi/qlogicpti.c | 5 ++-- drivers/scsi/sgiwd93.c | 5 ++-- drivers/scsi/stex.c | 16 +++++----- drivers/scsi/vmw_pvscsi.c | 4 +-- drivers/scsi/wd719x.c | 7 ++--- 33 files changed, 122 insertions(+), 175 deletions(-) -- 2.8.1

1 32

[PATCH for-next 0/6] RDMA/hns: Fix and refactor CMDQ related code
by Weihang Li 07 Feb '21

07 Feb '21

Remove some dead code in process of CMDQ transmission, and fix an issue about missing error code. Lang Cheng (6): RDMA/hns: Remove unused member and variable of CMDQ RDMA/hns: Remove unsupported CMDQ mode RDMA/hns: Fixes missing error code of CMDQ RDMA/hns: Remove redundant operations on CMDQ RDMA/hns: Adjust fields and variables about CMDQ tail/head RDMA/hns: Refactor process of posting CMDQ drivers/infiniband/hw/hns/hns_roce_common.h | 4 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 142 ++++++++-------------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 7 -- 3 files changed, 42 insertions(+), 111 deletions(-) -- 2.8.1

4 10

[PATCH v2 RFC 0/7] RDMA/hns: Add support for Dynamic Context Attachment
by Weihang Li 07 Feb '21

07 Feb '21

The hip09 introduces the DCA(Dynamic Context Attachment) feature which supports many RC QPs to share the WQE buffer in a memory pool. If a QP enables DCA feature, the WQE's buffer will not be allocated when creating but when the users start to post WRs. This will reduce the memory consumption when there are too many QPs are inactive. Changes since v1: * Replace all GFP_ATOMIC with GFP_NOWAIT, because the former may use emergency pool if no regular memory can be found. * Change size of cap_flags of alloc_ucontext_resp from 32 to 64 to avoid a potential problem when pass it back to the userspace. * Move definition of HNS_ROCE_CAP_FLAG_DCA_MODE to hns-abi.h. * Rename free_mem_states() to free_dca_states() in #1. * Link: https://patchwork.kernel.org/project/linux-rdma/cover/1610706138-4219-1-git… Xi Wang (7): RDMA/hns: Introduce DCA for RC QP RDMA/hns: Add method for shrinking DCA memory pool RDMA/hns: Configure DCA mode for the userspace QP RDMA/hns: Add method for attaching WQE buffer RDMA/hns: Setup the configuration of WQE addressing to QPC RDMA/hns: Add method to detach WQE buffer RDMA/hns: Add method to query WQE buffer's address drivers/infiniband/hw/hns/Makefile | 2 +- drivers/infiniband/hw/hns/hns_roce_dca.c | 1264 +++++++++++++++++++++++++++ drivers/infiniband/hw/hns/hns_roce_dca.h | 68 ++ drivers/infiniband/hw/hns/hns_roce_device.h | 31 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 223 ++++- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 3 + drivers/infiniband/hw/hns/hns_roce_main.c | 27 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 119 ++- include/uapi/rdma/hns-abi.h | 64 ++ 9 files changed, 1754 insertions(+), 47 deletions(-) create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.c create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.h -- 2.8.1

3 9

[PATCH V2 net-next 0/6] net: hns3: updates for -nex
by Huazhong Tan 07 Feb '21

07 Feb '21

This series adds some code optimizations and compatibility handlings for the HNS3 ethernet driver. change log: V2: refactor #2 as Jukub Kicinski reported and remove the part about RSS size which will not be different in different hw. updates netdev->max_mtu as well in #4 reported by Jakub Kicinski. previous version: V1: https://patchwork.kernel.org/project/netdevbpf/cover/1612269593-18691-1-git… Guangbin Huang (3): net: hns3: RSS indirection table use device specification net: hns3: debugfs add max tm rate specification print net: hns3: replace macro of max qset number with specification GuoJia Liao (1): net: hns3: optimize the code when update the tc info Jian Shen (1): net: hns3: add api capability bits for firmware Yufeng Mo (1): net: hns3: add support for obtaining the maximum frame size drivers/net/ethernet/hisilicon/hns3/hnae3.h | 5 +- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 3 ++ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 3 +- drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 5 +- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 6 +-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 10 ++++ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 9 +++- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 8 ++- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 57 +++++++++++++++------- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 8 +-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 15 ++++-- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 10 ++++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 9 +++- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 47 ++++++++++++------ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 8 +-- 15 files changed, 140 insertions(+), 63 deletions(-) -- 2.7.4

2 7

[PATCH for-next] RDMA/pvrdma: Replace spin_lock_irqsave with spin_lock in hard IRQ
by Weihang Li 06 Feb '21

06 Feb '21

There is no need to do irqsave and irqrestore in context of hard IRQ. Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c index 00a3309..4b6019e 100644 --- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c +++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c @@ -474,7 +474,6 @@ static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id) int ring_slots = (dev->dsr->cq_ring_pages.num_pages - 1) * PAGE_SIZE / sizeof(struct pvrdma_cqne); unsigned int head; - unsigned long flags; dev_dbg(&dev->pdev->dev, "interrupt x (completion) handler\n"); @@ -483,11 +482,11 @@ static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id) struct pvrdma_cq *cq; cqne = get_cqne(dev, head); - spin_lock_irqsave(&dev->cq_tbl_lock, flags); + spin_lock(&dev->cq_tbl_lock); cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq]; if (cq) refcount_inc(&cq->refcnt); - spin_unlock_irqrestore(&dev->cq_tbl_lock, flags); + spin_unlock(&dev->cq_tbl_lock); if (cq && cq->ibcq.comp_handler) cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); -- 2.8.1

2 1

[PATCH v3 1/2] dma-mapping: benchmark: use u8 for reserved field in uAPI structure
by Barry Song 05 Feb '21

05 Feb '21

The original code put five u32 before a u64 expansion[10] array. Five is odd, this will cause trouble in the extension of the structure by adding new features. This patch moves to use u8 for reserved field to avoid future alignment risk. Meanwhile, it also clears the memory of struct map_benchmark in tools, otherwise, if users use old version to run on newer kernel, the random expansion value will cause side effect on newer kernel. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/dma/map_benchmark.c | 2 +- tools/testing/selftests/dma/dma_map_benchmark.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index 1b1b8ff875cb..da95df381483 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -36,7 +36,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ - __u64 expansion[10]; /* For future use */ + __u8 expansion[84]; /* For future use */ }; struct map_benchmark_data { diff --git a/tools/testing/selftests/dma/dma_map_benchmark.c b/tools/testing/selftests/dma/dma_map_benchmark.c index 7065163a8388..537d65968c48 100644 --- a/tools/testing/selftests/dma/dma_map_benchmark.c +++ b/tools/testing/selftests/dma/dma_map_benchmark.c @@ -6,6 +6,7 @@ #include <fcntl.h> #include <stdio.h> #include <stdlib.h> +#include <string.h> #include <unistd.h> #include <sys/ioctl.h> #include <sys/mman.h> @@ -35,7 +36,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ - __u64 expansion[10]; /* For future use */ + __u8 expansion[84]; /* For future use */ }; int main(int argc, char **argv) @@ -102,6 +103,7 @@ int main(int argc, char **argv) exit(1); } + memset(&map, 0, sizeof(map)); map.seconds = seconds; map.threads = threads; map.node = node; -- 2.25.1

2 2

[PATCH v2] dma-mapping: benchmark: pretend DMA is transmitting
by Barry Song 05 Feb '21

05 Feb '21

In a real dma mapping user case, after dma_map is done, data will be transmit. Thus, in multi-threaded user scenario, IOMMU contention should not be that severe. For example, if users enable multiple threads to send network packets through 1G/10G/100Gbps NIC, usually the steps will be: map -> transmission -> unmap. Transmission delay reduces the contention of IOMMU. Here a delay is added to simulate the transmission between map and unmap so that the tested result could be more accurate for TX and simple RX. A typical TX transmission for NIC would be like: map -> TX -> unmap since the socket buffers come from OS. Simple RX model eg. disk driver, is also map -> RX -> unmap, but real RX model in a NIC could be more complicated considering packets can come spontaneously and many drivers are using pre-mapped buffers pool. This is in the TBD list. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- -v2: cleanup according to Robin's feedback. thanks, Robin. kernel/dma/map_benchmark.c | 10 ++++++++++ .../testing/selftests/dma/dma_map_benchmark.c | 19 +++++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index 1b1b8ff875cb..06636406a245 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -21,6 +21,7 @@ #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * NSEC_PER_MSEC) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -36,6 +37,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* time for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -87,6 +89,9 @@ static int map_benchmark_thread(void *data) map_etime = ktime_get(); map_delta = ktime_sub(map_etime, map_stime); + /* Pretend DMA is transmitting */ + ndelay(map->bparam.dma_trans_ns); + unmap_stime = ktime_get(); dma_unmap_single(map->dev, dma_addr, PAGE_SIZE, map->dir); unmap_etime = ktime_get(); @@ -218,6 +223,11 @@ static long map_benchmark_ioctl(struct file *file, unsigned int cmd, return -EINVAL; } + if (map->bparam.dma_trans_ns > DMA_MAP_MAX_TRANS_DELAY) { + pr_err("invalid transmission delay\n"); + return -EINVAL; + } + if (map->bparam.node != NUMA_NO_NODE && !node_possible(map->bparam.node)) { pr_err("invalid numa node\n"); diff --git a/tools/testing/selftests/dma/dma_map_benchmark.c b/tools/testing/selftests/dma/dma_map_benchmark.c index 7065163a8388..a370290d9503 100644 --- a/tools/testing/selftests/dma/dma_map_benchmark.c +++ b/tools/testing/selftests/dma/dma_map_benchmark.c @@ -11,9 +11,12 @@ #include <sys/mman.h> #include <linux/types.h> +#define NSEC_PER_MSEC 1000000L + #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * NSEC_PER_MSEC) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -35,6 +38,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* delay for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -45,12 +49,12 @@ int main(int argc, char **argv) /* default single thread, run 20 seconds on NUMA_NO_NODE */ int threads = 1, seconds = 20, node = -1; /* default dma mask 32bit, bidirectional DMA */ - int bits = 32, dir = DMA_MAP_BIDIRECTIONAL; + int bits = 32, xdelay = 0, dir = DMA_MAP_BIDIRECTIONAL; int cmd = DMA_MAP_BENCHMARK; char *p; - while ((opt = getopt(argc, argv, "t:s:n:b:d:")) != -1) { + while ((opt = getopt(argc, argv, "t:s:n:b:d:x:")) != -1) { switch (opt) { case 't': threads = atoi(optarg); @@ -67,6 +71,9 @@ int main(int argc, char **argv) case 'd': dir = atoi(optarg); break; + case 'x': + xdelay = atoi(optarg); + break; default: return -1; } @@ -84,6 +91,12 @@ int main(int argc, char **argv) exit(1); } + if (xdelay < 0 || xdelay > DMA_MAP_MAX_TRANS_DELAY) { + fprintf(stderr, "invalid transmit delay, must be in 0-%ld\n", + DMA_MAP_MAX_TRANS_DELAY); + exit(1); + } + /* suppose the mininum DMA zone is 1MB in the world */ if (bits < 20 || bits > 64) { fprintf(stderr, "invalid dma mask bit, must be in 20-64\n"); @@ -107,6 +120,8 @@ int main(int argc, char **argv) map.node = node; map.dma_bits = bits; map.dma_dir = dir; + map.dma_trans_ns = xdelay; + if (ioctl(fd, cmd, &map)) { perror("ioctl"); exit(1); -- 2.25.1

3 5

[PATCH] perf metricgroup: Fix system PMU metrics
by John Garry 05 Feb '21

05 Feb '21

Joakim reports that getting "perf stat" for multiple system PMU metrics segfaults: ./perf stat -a -I 1000 -M imx8mm_ddr_write.all,imx8mm_ddr_write.all Segmentation fault While the same works without issue for a single metric. The logic in metricgroup__add_metric_sys_event_iter() is broken, in that add_metric() @m argument should be NULL for each new metric. Fix by not passing a holder for that, and rather make local in metricgroup__add_metric_sys_event_iter(). Fixes: be335ec28efa ("perf metricgroup: Support adding metrics for system PMUs") Reported-by: Joakim Zhang <qiangqing.zhang(a)nxp.com> Signed-off-by: John Garry <john.garry(a)huawei.com> diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index ee94d3e8dd65..2e60ee170abc 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -766,7 +766,6 @@ int __weak arch_get_runtimeparam(struct pmu_event *pe __maybe_unused) struct metricgroup_add_iter_data { struct list_head *metric_list; const char *metric; - struct metric **m; struct expr_ids *ids; int *ret; bool *has_match; @@ -1058,12 +1057,13 @@ static int metricgroup__add_metric_sys_event_iter(struct pmu_event *pe, void *data) { struct metricgroup_add_iter_data *d = data; + struct metric *m = NULL; int ret; if (!match_pe_metric(pe, d->metric)) return 0; - ret = add_metric(d->metric_list, pe, d->metric_no_group, d->m, NULL, d->ids); + ret = add_metric(d->metric_list, pe, d->metric_no_group, &m, NULL, d->ids); if (ret) return ret; @@ -1114,7 +1114,6 @@ static int metricgroup__add_metric(const char *metric, bool metric_no_group, .metric_list = &list, .metric = metric, .metric_no_group = metric_no_group, - .m = &m, .ids = &ids, .has_match = &has_match, .ret = &ret, -- 2.26.2

4 15

[PATCH] dma-mapping: benchmark: pretend DMA is transmitting
by Barry Song 05 Feb '21

05 Feb '21

In a real dma mapping user case, after dma_map is done, data will be transmit. Thus, in multi-threaded user scenario, IOMMU contention should not be that severe. For example, if users enable multiple threads to send network packets through 1G/10G/100Gbps NIC, usually the steps will be: map -> transmission -> unmap. Transmission delay reduces the contention of IOMMU. Here a delay is added to simulate the transmission for TX case so that the tested result could be more accurate. RX case would be much more tricky. It is not supported yet. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/dma/map_benchmark.c | 11 +++++++++++ tools/testing/selftests/dma/dma_map_benchmark.c | 17 +++++++++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index 1b1b8ff875cb..1976db7e34e4 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -21,6 +21,7 @@ #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * 1000 * 1000) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -36,6 +37,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* time for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -87,6 +89,10 @@ static int map_benchmark_thread(void *data) map_etime = ktime_get(); map_delta = ktime_sub(map_etime, map_stime); + /* Pretend DMA is transmitting */ + if (map->dir != DMA_FROM_DEVICE) + ndelay(map->bparam.dma_trans_ns); + unmap_stime = ktime_get(); dma_unmap_single(map->dev, dma_addr, PAGE_SIZE, map->dir); unmap_etime = ktime_get(); @@ -218,6 +224,11 @@ static long map_benchmark_ioctl(struct file *file, unsigned int cmd, return -EINVAL; } + if (map->bparam.dma_trans_ns > DMA_MAP_MAX_TRANS_DELAY) { + pr_err("invalid transmission delay\n"); + return -EINVAL; + } + if (map->bparam.node != NUMA_NO_NODE && !node_possible(map->bparam.node)) { pr_err("invalid numa node\n"); diff --git a/tools/testing/selftests/dma/dma_map_benchmark.c b/tools/testing/selftests/dma/dma_map_benchmark.c index 7065163a8388..dbf426e2fb7f 100644 --- a/tools/testing/selftests/dma/dma_map_benchmark.c +++ b/tools/testing/selftests/dma/dma_map_benchmark.c @@ -14,6 +14,7 @@ #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * 1000 * 1000) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -35,6 +36,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* delay for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -45,12 +47,12 @@ int main(int argc, char **argv) /* default single thread, run 20 seconds on NUMA_NO_NODE */ int threads = 1, seconds = 20, node = -1; /* default dma mask 32bit, bidirectional DMA */ - int bits = 32, dir = DMA_MAP_BIDIRECTIONAL; + int bits = 32, xdelay = 0, dir = DMA_MAP_BIDIRECTIONAL; int cmd = DMA_MAP_BENCHMARK; char *p; - while ((opt = getopt(argc, argv, "t:s:n:b:d:")) != -1) { + while ((opt = getopt(argc, argv, "t:s:n:b:d:x:")) != -1) { switch (opt) { case 't': threads = atoi(optarg); @@ -67,6 +69,9 @@ int main(int argc, char **argv) case 'd': dir = atoi(optarg); break; + case 'x': + xdelay = atoi(optarg); + break; default: return -1; } @@ -84,6 +89,12 @@ int main(int argc, char **argv) exit(1); } + if (xdelay < 0 || xdelay > DMA_MAP_MAX_TRANS_DELAY) { + fprintf(stderr, "invalid transmit delay, must be in 0-%d\n", + DMA_MAP_MAX_TRANS_DELAY); + exit(1); + } + /* suppose the mininum DMA zone is 1MB in the world */ if (bits < 20 || bits > 64) { fprintf(stderr, "invalid dma mask bit, must be in 20-64\n"); @@ -107,6 +118,8 @@ int main(int argc, char **argv) map.node = node; map.dma_bits = bits; map.dma_dir = dir; + map.dma_trans_ns = xdelay; + if (ioctl(fd, cmd, &map)) { perror("ioctl"); exit(1); -- 2.25.1

3 2

[PATCH] spi: clps711xx: remove redundant white-space
by Yicong Yang 05 Feb '21

05 Feb '21

From: Junhao He <hejunhao2(a)hisilicon.com> Remove redundant white-space, no functional change. Signed-off-by: Junhao He <hejunhao2(a)hisilicon.com> Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> --- drivers/spi/spi-clps711x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c index 5e900f2..0bef5ce 100644 --- a/drivers/spi/spi-clps711x.c +++ b/drivers/spi/spi-clps711x.c @@ -104,7 +104,7 @@ static int spi_clps711x_probe(struct platform_device *pdev) master->use_gpio_descriptors = true; master->bus_num = -1; master->mode_bits = SPI_CPHA | SPI_CS_HIGH; - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8); + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8); master->dev.of_node = pdev->dev.of_node; master->prepare_message = spi_clps711x_prepare_message; master->transfer_one = spi_clps711x_transfer_one; -- 2.8.1

2 1

[PATCH 00/11] critical bugfixes for hns3
by Lijun Ou 04 Feb '21

04 Feb '21

Based on some suggestions, we reorganize the fixes and resend the only fixes. Chengchang Tang (4): net/hns3: fix stats flip overflow net/hns3: replace all atomic type with C11 atomic builtins net/hns3: fix cmdq cleared during firmware process net/hns3: fix VF reset after MBX failed Chengwen Feng (3): net/hns3: constraint TM peak rate net/hns3: remove MPLS type from supported flow items net/hns3: fix FD rule residue in hardware when malloc fail Huisong Li (3): net/hns3: fix query order of link status and link info net/hns3: fix link status change from firmware net/hns3: add check for max pkt length of Rx Lijun Ou (1): net/hns3: fix RSS indirection table size drivers/net/hns3/hns3_cmd.c | 36 ++++++++++-- drivers/net/hns3/hns3_cmd.h | 18 +++++- drivers/net/hns3/hns3_dcb.c | 2 +- drivers/net/hns3/hns3_ethdev.c | 116 ++++++++++++++++++++++++++++++-------- drivers/net/hns3/hns3_ethdev.h | 4 +- drivers/net/hns3/hns3_ethdev_vf.c | 62 ++++++++++++++------ drivers/net/hns3/hns3_flow.c | 36 ++++++------ drivers/net/hns3/hns3_intr.c | 22 +++++--- drivers/net/hns3/hns3_mbx.c | 4 +- drivers/net/hns3/hns3_rss.c | 28 ++++----- drivers/net/hns3/hns3_rss.h | 5 +- drivers/net/hns3/hns3_stats.c | 21 +++++-- drivers/net/hns3/hns3_tm.c | 6 ++ 13 files changed, 258 insertions(+), 102 deletions(-) -- 2.7.4

2 12

[PATCH net-next 0/7] net: hns3: updates for -next
by Huazhong Tan 04 Feb '21

04 Feb '21

This series includes some updates for the HNS3 ethernet driver. #1~#6 add some code optimizations and compatibility handlings. #7 fixes a clang warning. Guangbin Huang (3): net: hns3: RSS indirection table and key use device specifications net: hns3: debugfs add max tm rate specification print net: hns3: replace macro of max qset number with specification GuoJia Liao (1): net: hns3: optimize the code when update the tc info Huazhong Tan (1): net: hns3: remove unnecessary check in hns3_dbg_read() Jian Shen (1): net: hns3: add api capability bits for firmware Yufeng Mo (1): net: hns3: add support for obtaining the maximum frame length drivers/net/ethernet/hisilicon/hns3/hnae3.h | 8 +--- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 5 +- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 12 ++--- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 10 ++++ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 9 +++- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 8 ++-- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 53 ++++++++++++---------- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 14 ++++-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 15 ++++-- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 10 ++++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 6 ++- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 44 ++++++++---------- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 11 +++-- 13 files changed, 115 insertions(+), 90 deletions(-) -- 2.7.4

2 11

[PATCH hulk-4.19-next for SDI] net: hns3: adds support for setting pf max tx rate via sysfs
by Yonglong Liu 04 Feb '21

04 Feb '21

driver inclusion category: feature bugzilla: NA CVE: NA DTS:SR20210201768145 ---------------------------- This patch adds support for setting/getting pf max tx rate via sysfs: echo <rate Mbit/s> > /sys/class/net/<eth name>/kunpeng/pf/max_tx_rate cat /sys/class/net/<eth name>/kunpeng/pf/max_tx_rate Signed-off-by: Yonglong Liu <liuyonglong(a)huawei.com> --- drivers/net/ethernet/hisilicon/hns3/Makefile | 3 +- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 6 + .../hns3/hns3_extension/hns3pf/hclge_main_it.c | 33 +++++ .../hns3/hns3_extension/hns3pf/hclge_sysfs.c | 140 +++++++++++++++++++++ .../hns3/hns3_extension/hns3pf/hclge_sysfs.h | 14 +++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 17 +++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 3 + 7 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile index bd607c0..5efa685 100644 --- a/drivers/net/ethernet/hisilicon/hns3/Makefile +++ b/drivers/net/ethernet/hisilicon/hns3/Makefile @@ -38,7 +38,8 @@ HCLGE_OBJ = hns3pf/hclge_main.o \ hns3pf/hclge_err.o -HCLGE_OBJ_IT_MAIN = hns3_extension/hns3pf/hclge_main_it.o +HCLGE_OBJ_IT_MAIN = hns3_extension/hns3pf/hclge_main_it.o \ + hns3_extension/hns3pf/hclge_sysfs.o obj-$(CONFIG_HNS3_HCLGE) += hclge.o hclge-objs := $(HCLGE_OBJ) $(HCLGE_OBJ_IT_MAIN) hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index 3c56cbc..ac8a7c1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -578,6 +578,9 @@ struct hnae3_ae_ops { int (*ecc_handle)(struct hnae3_ae_dev *ae_dev); int (*priv_ops)(struct hnae3_handle *handle, int opcode, void *data, int length); + void (*ext_init)(struct hnae3_handle *handle); + void (*ext_uninit)(struct hnae3_handle *handle); + void (*ext_reset_done)(struct hnae3_handle *handle); #endif }; @@ -713,6 +716,9 @@ struct hnae3_handle { /* Network interface message level enabled bits */ u32 msg_enable; + + /* for sysfs */ + struct kobject *kobj; }; #define hnae3_set_field(origin, mask, shift, val) \ diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c index 01f0e19..59e2878 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c @@ -18,6 +18,9 @@ #include "hclge_main.h" #include "hnae3.h" #include "hclge_main_it.h" +#ifdef CONFIG_HNS3_TEST +#include "hclge_sysfs.h" +#endif #ifdef CONFIG_IT_VALIDATION #define HCLGE_RESET_MAX_FAIL_CNT 1 @@ -174,8 +177,38 @@ bool hclge_reset_done_it(struct hnae3_handle *handle, bool done) return done; } +#ifdef CONFIG_HNS3_TEST +void hclge_ext_init(struct hnae3_handle *handle) +{ + hclge_sysfs_init(handle); +} + +void hclge_ext_uninit(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + hclge_reset_pf_rate(hdev); + hclge_sysfs_uninit(handle); +} + +void hclge_ext_reset_done(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + hclge_resume_pf_rate(hdev); +} +#endif + int hclge_init_it(void) { +#ifdef CONFIG_HNS3_TEST + hclge_ops.ext_init = hclge_ext_init; + hclge_ops.ext_uninit = hclge_ext_uninit; + hclge_ops.ext_reset_done = hclge_ext_reset_done; +#endif + hclge_ops.reset_event = hclge_reset_event_it; hclge_ops.reset_done = hclge_reset_done_it; hclge_ops.handle_imp_error = hclge_handle_imp_error_it; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c new file mode 100644 index 00000000..86e6093 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2018-2021 Hisilicon Limited. */ + +#include <linux/device.h> +#include "hnae3.h" +#include "hclge_main.h" +#include "hclge_tm.h" +#include "hclge_sysfs.h" + +void hclge_reset_pf_rate(struct hclge_dev *hdev) +{ + struct hclge_vport *vport = &hdev->vport[0]; + int ret; + + /* zero means max rate, if max_tx_rate is zero, just return */ + if (!vport->vf_info.max_tx_rate) + return; + + vport->vf_info.max_tx_rate = 0; + + ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); + if (ret) + dev_err(&hdev->pdev->dev, + "failed to reset pf tx rate to default, ret = %d.\n", + ret); +} + +int hclge_resume_pf_rate(struct hclge_dev *hdev) +{ + struct hclge_vport *vport = &hdev->vport[0]; + int ret; + + /* zero means max rate, after reset, firmware already set it to + * max rate, so just continue. + */ + if (!vport->vf_info.max_tx_rate) + return 0; + + ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to resume pf tx rate:%u, ret = %d.\n", + vport->vf_info.max_tx_rate, ret); + return ret; + } + + return 0; +} + +static ssize_t hclge_max_tx_rate_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + struct hclge_vport *vport = + container_of(kobj, struct hclge_vport, kobj); + + return sprintf(buf, "%d Mbit/s (0 means no limit)\n", + vport->vf_info.max_tx_rate); +} + +static ssize_t hclge_max_tx_rate_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t size) +{ + struct hclge_vport *vport = + container_of(kobj, struct hclge_vport, kobj); + struct hclge_dev *hdev = vport->back; + int max_tx_rate; + int ret; + + ret = kstrtoint(buf, 0, &max_tx_rate); + if (ret) + return -EINVAL; + + if (max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { + dev_err(&hdev->pdev->dev, + "invalid max_tx_rate:%d [0, %u]\n", + max_tx_rate, hdev->hw.mac.max_speed); + return -EINVAL; + } + + ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); + if (ret) + return ret; + + vport->vf_info.max_tx_rate = max_tx_rate; + + return ret ? (ssize_t)ret : size; +} + +static struct kobj_attribute hclge_attr_max_tx_rate = { + .attr = {.name = "max_tx_rate", + .mode = 0644 }, + .show = hclge_max_tx_rate_show, + .store = hclge_max_tx_rate_store, +}; + +static struct attribute *hclge_sysfs_attrs[] = { + &hclge_attr_max_tx_rate.attr, + NULL, +}; + +static struct kobj_type hclge_sysfs_type = { + .sysfs_ops = &kobj_sysfs_ops, + .default_attrs = hclge_sysfs_attrs, +}; + +void hclge_sysfs_init(struct hnae3_handle *handle) +{ + struct net_device *netdev = handle->netdev; + struct hclge_vport *vport = hclge_get_vport(handle); + int ret; + + handle->kobj = kobject_create_and_add("kunpeng", &netdev->dev.kobj); + if (!handle->kobj) { + netdev_err(netdev, "failed to create kobj, ret = %d\n", ret); + return; + } + + ret = kobject_init_and_add(&vport->kobj, &hclge_sysfs_type, + handle->kobj, "pf"); + if (ret) { + netdev_err(netdev, "failed to init kobj, ret = %d\n", ret); + kobject_put(handle->kobj); + handle->kobj = NULL; + } +} + +void hclge_sysfs_uninit(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + + if (!handle->kobj) + return; + + kobject_put(&vport->kobj); + kobject_put(handle->kobj); + handle->kobj = NULL; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h new file mode 100644 index 00000000..8eb3335 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * Copyright (c) 2018-2021 Hisilicon Limited. + */ + +#ifndef __HCLGE_SYSFS_H +#define __HCLGE_SYSFS_H + +void hclge_reset_pf_rate(struct hclge_dev *hdev); +int hclge_resume_pf_rate(struct hclge_dev *hdev); + +void hclge_sysfs_init(struct hnae3_handle *handle); +void hclge_sysfs_uninit(struct hnae3_handle *handle); + +#endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index b40cf43..7b6d7c1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -9946,6 +9946,11 @@ static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, if (ret) return ret; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_init) + ae_dev->ops->ext_init(&vport->nic); +#endif + set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || rst_cnt != hdev->rst_stats.reset_cnt) { @@ -10087,6 +10092,13 @@ static void hclge_uninit_client_instance(struct hnae3_client *client, struct hclge_vport *vport; int i; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_uninit) { + vport = &hdev->vport[0]; + ae_dev->ops->ext_uninit(&vport->nic); + } +#endif + for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { vport = &hdev->vport[i]; if (hdev->roce_client) { @@ -10817,6 +10829,11 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) if (ret) return ret; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_reset_done) + ae_dev->ops->ext_reset_done(&hdev->vport->nic); +#endif + dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", HCLGE_DRIVER_NAME); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index 08d17ba..a0d2b4d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -970,6 +970,9 @@ struct hclge_vport { struct list_head uc_mac_list; /* Store VF unicast table */ struct list_head mc_mac_list; /* Store VF multicast table */ struct list_head vlan_list; /* Store VF vlan table */ + + /* for sysfs */ + struct kobject kobj; }; int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, -- 2.7.4

1 0

[RFC PATCH 0/4] hw/cxl/ + /hw/pci/: PCI DOE + CXL CDAT emulation
by Jonathan Cameron 04 Feb '21

04 Feb '21

Whilst I know others are working on an implementation of at least some of this, a desire to work on the kernel user of this required an implementation so I threw this together in the meantime and am sending it out on the basis that it may be of use to others. As it is an RFC I have been lazy on some cleanup and error handling. Will fix that in a future version if we decide to take this forwards. Based on Ben's cxl-2.0v3 branch from https://gitlab.com/bwidawsk/qemu Possible I've picked an unstable branch so this may or may not currently apply :) I'll rebase on Ben's next version when avaialble. Jonathan Cameron (4): include/standard-headers/linux/pci_regs: temp hack to add necessary DOE definitions. hw/pci/pcie_doe: Introduce utility functions for PCIe DOE hw/cxl/cxl-cdat: Initial CDAT implementation for use by CXL devices hw/mem/cxl_type3: Enabled DOE mailbox for access to CDAT hw/cxl/cxl-cdat.c | 252 +++++++++++++++++++++ hw/cxl/meson.build | 1 + hw/mem/cxl_type3.c | 49 ++++- hw/pci/meson.build | 2 +- hw/pci/pcie_doe.c | 257 ++++++++++++++++++++++ include/hw/cxl/cxl.h | 1 + include/hw/cxl/cxl_cdat.h | 101 +++++++++ include/hw/pci/doe.h | 40 ++++ include/hw/pci/pci_ids.h | 2 + include/standard-headers/linux/pci_regs.h | 33 ++- 10 files changed, 734 insertions(+), 4 deletions(-) create mode 100644 hw/cxl/cxl-cdat.c create mode 100644 hw/pci/pcie_doe.c create mode 100644 include/hw/cxl/cxl_cdat.h create mode 100644 include/hw/pci/doe.h -- 2.19.1

4 11

[RFC PATCH 0/3] hw/arm/virt: CXL enablement including gpex-acpi
by Jonathan Cameron 04 Feb '21

04 Feb '21

Very basic initial enablement of CXL on arm virt with relevant ACPI table construction. Includes changes in gpex-acpi to ensure correct DSDT for any pci_expand_bridge/pxb-cxl bridges. Note not looking to do the primary root bridge yet. Based on Ben's tree cxl-2.0v3 at https://gitlab.com/bwidawsk/qemu To actually get the memory appropriately exposed to the OS a few additional changes are needed as discussed in thread https://lore.kernel.org/qemu-devel/20210128174009.00007536@Huawei.com/ I will rebase this on future versions of Ben's series as needed. Jonathan Cameron (3): hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl hw/cxl/cxl-device-utils: Allow incorrect read lengths hw/arm/Kconfig | 1 + hw/arm/virt-acpi-build.c | 27 +++++++++++++++++++++++++++ hw/arm/virt.c | 3 ++- hw/cxl/cxl-device-utils.c | 4 ++-- hw/pci-host/gpex-acpi.c | 22 +++++++++++++++++++--- 5 files changed, 51 insertions(+), 6 deletions(-) -- 2.19.1

3 5

[PATCH] PCI/DPC: Check host->native_dpc before enable dpc service
by Yicong Yang 03 Feb '21

03 Feb '21

Per PCI Firmware Specification Rev. 3.2 Table 4-6, Interpretation of _OSC Control Field Returned Value, for bit 7 of _OSC control return value: "Firmware sets this bit to 1 to grant the OS control over PCI Express Downstream Port Containment configuration." "If control of this feature was requested and denied, or was not requested, the firmware returns this bit set to 0." We store bit 7 of _OSC control return value in host->native_dpc, check it before enable the dpc service as the firmware may not grant the control. Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> --- drivers/pci/pcie/portdrv_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e1fed664..7445d03 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -253,7 +253,8 @@ static int get_port_device_capability(struct pci_dev *dev) */ if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) && pci_aer_available() && - (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER))) + (pcie_ports_dpc_native || + ((services & PCIE_PORT_SERVICE_AER) && host->native_dpc))) services |= PCIE_PORT_SERVICE_DPC; if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM || -- 2.8.1

1 1

[PATCH 00/17] bugfixes and small functionality for hns3
by Lijun Ou 03 Feb '21

03 Feb '21

This patch series add some bugfixes and some small functions. In order to fix some bugfixes, we had to do some code rework, for example patch[13/17]. Chengchang Tang (6): net/hns3: support module EEPROM dump net/hns3: add more registers to dump net/hns3: fix stats flip overflow net/hns3: replace all atomic type with C11 atomic builtins net/hns3: fix cmdq cleared during firmware process net/hns3: fix VF reset after MBX failed Chengwen Feng (4): net/hns3: implement cleanup for Tx done net/hns3: constraint TM peak rate net/hns3: remove MPLS type from supported flow items net/hns3: fix FD rule residue in hardware when malloc fail Huisong Li (5): net/hns3: fix query order of link status and link info net/hns3: fix link status change from firmware net/hns3: encapsulate a port shaping interface net/hns3: support PF on electrical net device net/hns3: add check for max pkt length of Rx Lijun Ou (1): net/hns3: fix RSS indirection table size Min Hu (Connor) (1): net/hns3: add enhance stats function doc/guides/nics/features/hns3.ini | 2 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_02.rst | 1 + drivers/net/hns3/hns3_cmd.c | 36 ++- drivers/net/hns3/hns3_cmd.h | 91 +++++++- drivers/net/hns3/hns3_dcb.c | 24 +- drivers/net/hns3/hns3_dcb.h | 2 +- drivers/net/hns3/hns3_ethdev.c | 406 ++++++++++++++++++++++++++++++--- drivers/net/hns3/hns3_ethdev.h | 10 +- drivers/net/hns3/hns3_ethdev_vf.c | 63 +++-- drivers/net/hns3/hns3_flow.c | 36 ++- drivers/net/hns3/hns3_intr.c | 22 +- drivers/net/hns3/hns3_mbx.c | 4 +- drivers/net/hns3/hns3_regs.c | 171 +++++++++++++- drivers/net/hns3/hns3_rss.c | 28 +-- drivers/net/hns3/hns3_rss.h | 5 +- drivers/net/hns3/hns3_rxtx.c | 83 +++++++ drivers/net/hns3/hns3_rxtx.h | 1 + drivers/net/hns3/hns3_rxtx_vec_neon.h | 15 ++ drivers/net/hns3/hns3_rxtx_vec_sve.c | 11 + drivers/net/hns3/hns3_stats.c | 156 ++++++++++++- drivers/net/hns3/hns3_stats.h | 8 + drivers/net/hns3/hns3_tm.c | 6 + 23 files changed, 1050 insertions(+), 132 deletions(-) -- 2.7.4

3 21

[PATCH] sched/topology: fix the issue groups don't span domain->span for NUMA diameter > 2
by Barry Song 03 Feb '21

03 Feb '21

As long as NUMA diameter > 2, building sched_domain by sibling's child domain will definitely create a sched_domain with sched_group which will span out of the sched_domain: +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 node2 node3 domain1 node0+1 node0+1 node2+3 node2+3 + domain2 node0+1+2 | group: node0+1 | group:node2+3 <-------------------+ when node2 is added into the domain2 of node0, kernel is using the child domain of node2's domain2, which is domain1(node2+3). Node 3 is outside the span of the domain including node0+1+2. This will make load_balance() run based on the avg_load in the sched_group spanning out of the sched_domain, and it also makes select_task_rq_fair() pick an idle CPU out of the sched_domain. Real servers which suffer from this problem include Kunpeng920 and 8-node Sun Fire X4600-M2, at least. Here we move to use the *child* domain of the *child* domain of node2's domain2 to build the sched_group. +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 +- node2 node3 | domain1 node0+1 node0+1 | node2+3 node2+3 | domain2 node0+1+2 | group: node0+1 | group:node2 <-------------------+ A tricky thing is that we shouldn't use the sgc of the 1st CPU of node2 for the sched_group generated by grandchild, otherwise, when this cpu becomes the balance_cpu of another sched_group of cpus other than node0, our sched_group generated by grandchild will access the same sgc with the sched_group generated by child of another CPU. So in init_overlap_sched_group(), sgc's capacity be overwritten: build_balance_mask(sd, sg, mask); cpu = cpumask_first_and(sched_group_span(sg), mask); sg->sgc = *per_cpu_ptr(sdd->sgc, cpu); And WARN_ON_ONCE(!cpumask_equal(group_balance_mask(sg), mask)) will also be triggered: static void init_overlap_sched_group(struct sched_domain *sd, struct sched_group *sg) { if (atomic_inc_return(&sg->sgc->ref) == 1) cpumask_copy(group_balance_mask(sg), mask); else WARN_ON_ONCE(!cpumask_equal(group_balance_mask(sg), mask)); } So here move to use the sgc of the 2nd cpu. For the corner case, if NUMA has only one CPU, we will still trigger this WARN_ON_ONCE. But It is really unlikely to be a real case for one NUMA to have one CPU only. Tested by the below topology: qemu-system-aarch64 -M virt -nographic \ -smp cpus=8 \ -numa node,cpus=0-1,nodeid=0 \ -numa node,cpus=2-3,nodeid=1 \ -numa node,cpus=4-5,nodeid=2 \ -numa node,cpus=6-7,nodeid=3 \ -numa dist,src=0,dst=1,val=12 \ -numa dist,src=0,dst=2,val=20 \ -numa dist,src=0,dst=3,val=22 \ -numa dist,src=1,dst=2,val=22 \ -numa dist,src=2,dst=3,val=12 \ -numa dist,src=1,dst=3,val=24 \ -m 4G -cpu cortex-a57 -kernel arch/arm64/boot/Image w/o patch, we get lots of "groups don't span domain->span": [ 0.802139] CPU0 attaching sched-domain(s): [ 0.802193] domain-0: span=0-1 level=MC [ 0.802443] groups: 0:{ span=0 cap=1013 }, 1:{ span=1 cap=979 } [ 0.802693] domain-1: span=0-3 level=NUMA [ 0.802731] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.802811] domain-2: span=0-5 level=NUMA [ 0.802829] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.802881] ERROR: groups don't span domain->span [ 0.803058] domain-3: span=0-7 level=NUMA [ 0.803080] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804055] CPU1 attaching sched-domain(s): [ 0.804072] domain-0: span=0-1 level=MC [ 0.804096] groups: 1:{ span=1 cap=979 }, 0:{ span=0 cap=1013 } [ 0.804152] domain-1: span=0-3 level=NUMA [ 0.804170] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.804219] domain-2: span=0-5 level=NUMA [ 0.804236] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.804302] ERROR: groups don't span domain->span [ 0.804520] domain-3: span=0-7 level=NUMA [ 0.804546] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804677] CPU2 attaching sched-domain(s): [ 0.804687] domain-0: span=2-3 level=MC [ 0.804705] groups: 2:{ span=2 cap=934 }, 3:{ span=3 cap=1009 } [ 0.804754] domain-1: span=0-3 level=NUMA [ 0.804772] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.804820] domain-2: span=0-5 level=NUMA [ 0.804836] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.804944] ERROR: groups don't span domain->span [ 0.805108] domain-3: span=0-7 level=NUMA [ 0.805134] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805223] CPU3 attaching sched-domain(s): [ 0.805232] domain-0: span=2-3 level=MC [ 0.805249] groups: 3:{ span=3 cap=1009 }, 2:{ span=2 cap=934 } [ 0.805319] domain-1: span=0-3 level=NUMA [ 0.805336] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.805383] domain-2: span=0-5 level=NUMA [ 0.805399] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.805458] ERROR: groups don't span domain->span [ 0.805605] domain-3: span=0-7 level=NUMA [ 0.805626] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805712] CPU4 attaching sched-domain(s): [ 0.805721] domain-0: span=4-5 level=MC [ 0.805738] groups: 4:{ span=4 cap=984 }, 5:{ span=5 cap=924 } [ 0.805787] domain-1: span=4-7 level=NUMA [ 0.805803] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.805851] domain-2: span=0-1,4-7 level=NUMA [ 0.805867] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.805915] ERROR: groups don't span domain->span [ 0.806108] domain-3: span=0-7 level=NUMA [ 0.806130] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.806214] CPU5 attaching sched-domain(s): [ 0.806222] domain-0: span=4-5 level=MC [ 0.806240] groups: 5:{ span=5 cap=924 }, 4:{ span=4 cap=984 } [ 0.806841] domain-1: span=4-7 level=NUMA [ 0.806866] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.806934] domain-2: span=0-1,4-7 level=NUMA [ 0.806953] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.807004] ERROR: groups don't span domain->span [ 0.807312] domain-3: span=0-7 level=NUMA [ 0.807386] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.807686] CPU6 attaching sched-domain(s): [ 0.807710] domain-0: span=6-7 level=MC [ 0.807750] groups: 6:{ span=6 cap=1017 }, 7:{ span=7 cap=1012 } [ 0.807840] domain-1: span=4-7 level=NUMA [ 0.807870] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.807952] domain-2: span=0-1,4-7 level=NUMA [ 0.807985] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.808045] ERROR: groups don't span domain->span [ 0.808257] domain-3: span=0-7 level=NUMA [ 0.808571] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6125 }, 2:{ span=0-5 mask=2-3 cap=5899 } [ 0.808848] CPU7 attaching sched-domain(s): [ 0.808860] domain-0: span=6-7 level=MC [ 0.808880] groups: 7:{ span=7 cap=1012 }, 6:{ span=6 cap=1017 } [ 0.808953] domain-1: span=4-7 level=NUMA [ 0.808974] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.809034] domain-2: span=0-1,4-7 level=NUMA [ 0.809055] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.809128] ERROR: groups don't span domain->span [ 0.810361] domain-3: span=0-7 level=NUMA [ 0.810400] groups: 6:{ span=0-1,4-7 mask=6-7 cap=5961 }, 2:{ span=0-5 mask=2-3 cap=5903 } w/ patch, we don't get "groups don't span domain->span" any more: [ 0.868907] CPU0 attaching sched-domain(s): [ 0.868962] domain-0: span=0-1 level=MC [ 0.869179] groups: 0:{ span=0 cap=1013 }, 1:{ span=1 cap=983 } [ 0.869405] domain-1: span=0-3 level=NUMA [ 0.869438] groups: 0:{ span=0-1 cap=1996 }, 2:{ span=2-3 cap=2006 } [ 0.869542] domain-2: span=0-5 level=NUMA [ 0.869559] groups: 0:{ span=0-3 cap=4002 }, 5:{ span=4-5 cap=2048 } [ 0.869603] domain-3: span=0-7 level=NUMA [ 0.869618] groups: 0:{ span=0-5 mask=0-1 cap=5980 }, 6:{ span=4-7 mask=6-7 cap=4016 } [ 0.870303] CPU1 attaching sched-domain(s): [ 0.870314] domain-0: span=0-1 level=MC [ 0.870334] groups: 1:{ span=1 cap=983 }, 0:{ span=0 cap=1013 } [ 0.870381] domain-1: span=0-3 level=NUMA [ 0.870396] groups: 0:{ span=0-1 cap=1996 }, 2:{ span=2-3 cap=2006 } [ 0.870440] domain-2: span=0-5 level=NUMA [ 0.870454] groups: 0:{ span=0-3 cap=4002 }, 5:{ span=4-5 cap=2048 } [ 0.870507] domain-3: span=0-7 level=NUMA [ 0.870530] groups: 0:{ span=0-5 mask=0-1 cap=5980 }, 6:{ span=4-7 mask=6-7 cap=4016 } [ 0.870611] CPU2 attaching sched-domain(s): [ 0.870619] domain-0: span=2-3 level=MC [ 0.870634] groups: 2:{ span=2 cap=1007 }, 3:{ span=3 cap=999 } [ 0.870677] domain-1: span=0-3 level=NUMA [ 0.870691] groups: 2:{ span=2-3 cap=2006 }, 0:{ span=0-1 cap=1996 } [ 0.870734] domain-2: span=0-5 level=NUMA [ 0.870748] groups: 2:{ span=0-3 mask=2-3 cap=4054 }, 5:{ span=4-5 cap=2048 } [ 0.870795] domain-3: span=0-7 level=NUMA [ 0.870809] groups: 2:{ span=0-5 mask=2-3 cap=6032 }, 6:{ span=0-1,4-7 mask=6-7 cap=6064 } [ 0.870913] CPU3 attaching sched-domain(s): [ 0.870921] domain-0: span=2-3 level=MC [ 0.870936] groups: 3:{ span=3 cap=999 }, 2:{ span=2 cap=1007 } [ 0.870979] domain-1: span=0-3 level=NUMA [ 0.870993] groups: 2:{ span=2-3 cap=2006 }, 0:{ span=0-1 cap=1996 } [ 0.871035] domain-2: span=0-5 level=NUMA [ 0.871049] groups: 2:{ span=0-3 mask=2-3 cap=4054 }, 5:{ span=4-5 cap=2048 } [ 0.871096] domain-3: span=0-7 level=NUMA [ 0.871110] groups: 2:{ span=0-5 mask=2-3 cap=6032 }, 6:{ span=0-1,4-7 mask=6-7 cap=6064 } [ 0.871177] CPU4 attaching sched-domain(s): [ 0.871185] domain-0: span=4-5 level=MC [ 0.871200] groups: 4:{ span=4 cap=977 }, 5:{ span=5 cap=1001 } [ 0.871243] domain-1: span=4-7 level=NUMA [ 0.871257] groups: 4:{ span=4-5 cap=1978 }, 6:{ span=6-7 cap=1968 } [ 0.871300] domain-2: span=0-1,4-7 level=NUMA [ 0.871314] groups: 4:{ span=4-7 cap=3946 }, 1:{ span=0-1 cap=2048 } [ 0.871356] domain-3: span=0-7 level=NUMA [ 0.871370] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5994 }, 2:{ span=0-3 mask=2-3 cap=4054 } [ 0.871436] CPU5 attaching sched-domain(s): [ 0.871443] domain-0: span=4-5 level=MC [ 0.871457] groups: 5:{ span=5 cap=1001 }, 4:{ span=4 cap=977 } [ 0.871512] domain-1: span=4-7 level=NUMA [ 0.871893] groups: 4:{ span=4-5 cap=1978 }, 6:{ span=6-7 cap=1968 } [ 0.871949] domain-2: span=0-1,4-7 level=NUMA [ 0.871966] groups: 4:{ span=4-7 cap=3946 }, 1:{ span=0-1 cap=2048 } [ 0.872010] domain-3: span=0-7 level=NUMA [ 0.872025] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5994 }, 2:{ span=0-3 mask=2-3 cap=4054 } [ 0.872115] CPU6 attaching sched-domain(s): [ 0.872123] domain-0: span=6-7 level=MC [ 0.872139] groups: 6:{ span=6 cap=993 }, 7:{ span=7 cap=975 } [ 0.872186] domain-1: span=4-7 level=NUMA [ 0.872202] groups: 6:{ span=6-7 cap=1968 }, 4:{ span=4-5 cap=1978 } [ 0.872246] domain-2: span=0-1,4-7 level=NUMA [ 0.872260] groups: 6:{ span=4-7 mask=6-7 cap=4016 }, 1:{ span=0-1 cap=2048 } [ 0.872309] domain-3: span=0-7 level=NUMA [ 0.872323] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6064 }, 2:{ span=0-5 mask=2-3 cap=6032 } [ 0.872392] CPU7 attaching sched-domain(s): [ 0.872399] domain-0: span=6-7 level=MC [ 0.872414] groups: 7:{ span=7 cap=975 }, 6:{ span=6 cap=993 } [ 0.872458] domain-1: span=4-7 level=NUMA [ 0.872472] groups: 6:{ span=6-7 cap=1968 }, 4:{ span=4-5 cap=1978 } [ 0.872662] domain-2: span=0-1,4-7 level=NUMA [ 0.872685] groups: 6:{ span=4-7 mask=6-7 cap=4016 }, 1:{ span=0-1 cap=2048 } [ 0.872737] domain-3: span=0-7 level=NUMA [ 0.872752] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6064 }, 2:{ span=0-5 mask=2-3 cap=6032 } Reported-by: Valentin Schneider <valentin.schneider(a)arm.com> Tested-by: Meelis Roos <mroos(a)linux.ee> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- Differences with RFC v2 * added tested-by Meelis Roos for the fixed "8-node Sun Fire X4600-M2" * removed the hacking code in balance_mask and should_we_balance() * removed the redundant "from_grandchild" field from sched_group The patch is based on 5.11-rc6; kernel/sched/topology.c | 83 ++++++++++++++++++++++++++--------------- 1 file changed, 52 insertions(+), 31 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 5d3675c7a76b..100feb2fd8a0 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -723,35 +723,6 @@ cpu_attach_domain(struct sched_domain *sd, struct root_domain *rd, int cpu) for (tmp = sd; tmp; tmp = tmp->parent) numa_distance += !!(tmp->flags & SD_NUMA); - /* - * FIXME: Diameter >=3 is misrepresented. - * - * Smallest diameter=3 topology is: - * - * node 0 1 2 3 - * 0: 10 20 30 40 - * 1: 20 10 20 30 - * 2: 30 20 10 20 - * 3: 40 30 20 10 - * - * 0 --- 1 --- 2 --- 3 - * - * NUMA-3 0-3 N/A N/A 0-3 - * groups: {0-2},{1-3} {1-3},{0-2} - * - * NUMA-2 0-2 0-3 0-3 1-3 - * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} - * - * NUMA-1 0-1 0-2 1-3 2-3 - * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} - * - * NUMA-0 0 1 2 3 - * - * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the - * group span isn't a subset of the domain span. - */ - WARN_ONCE(numa_distance > 2, "Shortest NUMA path spans too many nodes\n"); - sched_domain_debug(sd, cpu); rq_attach_root(rq, rd); @@ -916,6 +887,11 @@ build_balance_mask(struct sched_domain *sd, struct sched_group *sg, struct cpuma if (!sibling->child) continue; + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + sched_domain_span(sd))) + sibling = sibling->child; + /* If we would not end up here, we can't continue from here */ if (!cpumask_equal(sg_span, sched_domain_span(sibling->child))) continue; @@ -955,7 +931,8 @@ build_group_from_child_sched_domain(struct sched_domain *sd, int cpu) } static void init_overlap_sched_group(struct sched_domain *sd, - struct sched_group *sg) + struct sched_group *sg, + int from_grandchild) { struct cpumask *mask = sched_domains_tmpmask2; struct sd_data *sdd = sd->private; @@ -964,6 +941,12 @@ static void init_overlap_sched_group(struct sched_domain *sd, build_balance_mask(sd, sg, mask); cpu = cpumask_first_and(sched_group_span(sg), mask); + /* + * for the group generated by grandchild, use the sgc of 2nd cpu + * because the 1st cpu might be used by another sched_group + */ + if (from_grandchild && cpumask_weight(mask) > 1) + cpu = cpumask_next_and(cpu, sched_group_span(sg), mask); sg->sgc = *per_cpu_ptr(sdd->sgc, cpu); if (atomic_inc_return(&sg->sgc->ref) == 1) @@ -996,6 +979,7 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) for_each_cpu_wrap(i, span, cpu) { struct cpumask *sg_span; + int from_grandchild = 0; if (cpumask_test_cpu(i, covered)) continue; @@ -1015,6 +999,43 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) if (!cpumask_test_cpu(i, sched_domain_span(sibling))) continue; + /* + * for NUMA diameter >= 3, building sched_domain by sibling's + * child's child domain to prevent sched_group from spanning + * out of sched_domain + * if we don't do this, Diameter >=3 is misrepresented: + * + * Smallest diameter=3 topology is: + * + * node 0 1 2 3 + * 0: 10 20 30 40 + * 1: 20 10 20 30 + * 2: 30 20 10 20 + * 3: 40 30 20 10 + * + * 0 --- 1 --- 2 --- 3 + * + * NUMA-3 0-3 N/A N/A 0-3 + * groups: {0-2},{1-3} {1-3},{0-2} + * + * NUMA-2 0-2 0-3 0-3 1-3 + * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} + * + * NUMA-1 0-1 0-2 1-3 2-3 + * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} + * + * NUMA-0 0 1 2 3 + * + * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the + * group span isn't a subset of the domain span. + */ + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + span)) { + sibling = sibling->child; + from_grandchild = 1; + } + sg = build_group_from_child_sched_domain(sibling, cpu); if (!sg) goto fail; @@ -1022,7 +1043,7 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) sg_span = sched_group_span(sg); cpumask_or(covered, covered, sg_span); - init_overlap_sched_group(sd, sg); + init_overlap_sched_group(sd, sg, from_grandchild); if (!first) first = sg; -- 2.25.1

4 8

[PATCH 0/3] update doc for hns3
by Lijun Ou 03 Feb '21

03 Feb '21

Here series add some updates for hns3 rst and TM feature note for hns3 as well as FEC feature notes. Lijun Ou (2): doc: update release notes for hns3 doc: fix hns3 rst Min Hu (Connor) (1): doc: add FEC in NIC features doc/guides/nics/features.rst | 14 ++++++++++++++ doc/guides/nics/features/default.ini | 1 + doc/guides/nics/hns3.rst | 2 +- doc/guides/rel_notes/release_21_02.rst | 4 ++++ 4 files changed, 20 insertions(+), 1 deletion(-) -- 2.7.4

4 28

[PATCH] perf test: Add parse-metric memory bandwidth testcase
by John Garry 03 Feb '21

03 Feb '21

Event duration_time in a metric expression requires special handling. Improve test coverage by including a metric whose expression includes duration_time. The actual metric is a copied from the L1D_Cache_Fill_BW metric on my broadwell machine. Signed-off-by: John Garry <john.garry(a)huawei.com> --- Based on acme perf/core + "perf metricgroup: Fix for metrics containing duration_time" diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index ce7be37f0d88..6dc1db1626ad 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -69,6 +69,10 @@ static struct pmu_event pme_test[] = { .metric_expr = "1/m3", .metric_name = "M3", }, +{ + .metric_expr = "64 * l1d.replacement / 1000000000 / duration_time", + .metric_name = "L1D_Cache_Fill_BW", +}, { .name = NULL, } @@ -107,6 +111,8 @@ static void load_runtime_stat(struct runtime_stat *st, struct evlist *evlist, evlist__for_each_entry(evlist, evsel) { count = find_value(evsel->name, vals); perf_stat__update_shadow_stats(evsel, count, 0, st); + if (!strcmp(evsel->name, "duration_time")) + update_stats(&walltime_nsecs_stats, count); } } @@ -321,6 +327,23 @@ static int test_recursion_fail(void) return 0; } +static int test_memory_bandwidth(void) +{ + double ratio; + struct value vals[] = { + { .event = "l1d.replacement", .val = 4000000 }, + { .event = "duration_time", .val = 200000000 }, + { .event = NULL, }, + }; + + TEST_ASSERT_VAL("failed to compute metric", + compute_metric("L1D_Cache_Fill_BW", vals, &ratio) == 0); + TEST_ASSERT_VAL("L1D_Cache_Fill_BW, wrong ratio", + 1.28 == ratio); + + return 0; +} + static int test_metric_group(void) { double ratio1, ratio2; @@ -353,5 +376,6 @@ int test__parse_metric(struct test *test __maybe_unused, int subtest __maybe_unu TEST_ASSERT_VAL("DCache_L2 failed", test_dcache_l2() == 0); TEST_ASSERT_VAL("recursion fail failed", test_recursion_fail() == 0); TEST_ASSERT_VAL("test metric group", test_metric_group() == 0); + TEST_ASSERT_VAL("Memory bandwidth", test_memory_bandwidth() == 0); return 0; } -- 2.26.2

3 2

[PATCH] drivers/perf: Prevent forced unbinding of ARM_DMC620_PMU drivers
by Qi Liu 03 Feb '21

03 Feb '21

Set "suppress_bind_attrs" to true, so that bind/unbind can be disabled via sysfs and prevent unbinding ARM_DMC620_PMU drivers during perf sampling. Signed-off-by: Qi Liu <liuqi115(a)huawei.com> --- drivers/perf/arm_dmc620_pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/perf/arm_dmc620_pmu.c b/drivers/perf/arm_dmc620_pmu.c index 27f54c0..66ad5b3 100644 --- a/drivers/perf/arm_dmc620_pmu.c +++ b/drivers/perf/arm_dmc620_pmu.c @@ -717,6 +717,7 @@ static struct platform_driver dmc620_pmu_driver = { .driver = { .name = DMC620_DRVNAME, .acpi_match_table = dmc620_acpi_match, + .suppress_bind_attrs = true, }, .probe = dmc620_pmu_device_probe, .remove = dmc620_pmu_device_remove, -- 2.8.1

2 1

[PATCH v2] mtd: spi-nor: check 4-byte address support when parsing 4bait
by Yicong Yang 02 Feb '21

02 Feb '21

The spi-nor core will convert the address mode to 4-btye, without checking whether 4-byte address is supported or not. For example, the 16M s25fs128s1 can work under both 3-byte and 4-byte address and provides a 4bait table. The spi-nor will drive the flash under 4-byte address mode after parsing the 4bait and will cause it unusable on platforms doesn't support 4-byte. Add checking of 4-byte address support when parsing the 4bait table, stop converting the address mode if it's not supported. The issue maybe addressed by moving the address mode set and 4-byte operation check out of paring 4bait table[1], but fix this with this patch to make the flash work properly on some platform first. [1] https://lore.kernel.org/linux-mtd/20210129111649.jypytpp7dkywthwh@ti.com/ Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> --- Change since v1: - address the comments from Pratyush Link: https://lore.kernel.org/linux-mtd/20210129111649.jypytpp7dkywthwh@ti.com/ drivers/mtd/spi-nor/sfdp.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 6ee7719..46ce389 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -940,6 +940,25 @@ static int spi_nor_parse_smpt(struct spi_nor *nor, return ret; } +static int spi_nor_spimem_check_4byte_addr(struct spi_nor *nor, + const struct spi_nor_read_command *read) +{ + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), + SPI_MEM_OP_ADDR(4, 0, 1), + SPI_MEM_OP_DUMMY(0, 1), + SPI_MEM_OP_DATA_IN(0, NULL, 1)); + + spi_nor_spimem_setup_op(nor, &op, read->proto); + + op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * + op.dummy.buswidth / 8; + + if (!spi_mem_supports_op(nor->spimem, &op)) + return -EOPNOTSUPP; + + return 0; +} + /** * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table * @nor: pointer to a 'struct spi_nor'. @@ -1061,6 +1080,33 @@ static int spi_nor_parse_4bait(struct spi_nor *nor, goto out; /* + * Check whether the 4-byte address is supported before converting + * the instruction set to 4-byte. + */ + if (nor->spimem) { + bool support = false; + + for (i = 0; i < SNOR_CMD_READ_MAX; i++) { + struct spi_nor_read_command read_cmd; + + memcpy(&read_cmd, &params->reads[i], sizeof(read_cmd)); + + read_cmd.opcode = spi_nor_convert_3to4_read(read_cmd.opcode); + if (!spi_nor_spimem_check_4byte_addr(nor, &read_cmd)) { + support = true; + break; + } + } + + /* + * No supported 4-byte instruction is found, stop parsing the + * 4bait table. + */ + if (!support) + goto out; + } + + /* * Discard all operations from the 4-byte instruction set which are * not supported by this memory. */ -- 2.8.1

1 0

[PATCH 00/14] Misc updates for hns3
by Lijun Ou 02 Feb '21

02 Feb '21

This series add a new feature LSC event report and two bugfixes as well as some cleanup patches. Chengchang Tang (2): net/hns3: reconstruct the Rx interrupt map net/hns3: fix interrupt resources in Rx interrupt mode Chengwen Feng (1): net/hns3: support LSC event report Huisong Li (2): net/hns3: encapsulate dfx stats in Rx/Tx datapatch net/hns3: move queue stats to xstats Lijun Ou (9): net/hns3: use array instead of switch-case net/hns3: move judgment conditions to separated functions net/hns3: extract common judgments for all FDIR type net/hns3: refactor reset event report function net/hns3: fix memory leak with secondary process exit net/hns3: rename RSS functions net/hns3: adjust some comments net/hns3: remove unnecessary parentheses net/hns3: use %d instead of %u for enum variable drivers/net/hns3/hns3_cmd.c | 54 ++-- drivers/net/hns3/hns3_cmd.h | 9 +- drivers/net/hns3/hns3_ethdev.c | 208 ++++++++++------ drivers/net/hns3/hns3_ethdev.h | 4 +- drivers/net/hns3/hns3_ethdev_vf.c | 111 ++++++--- drivers/net/hns3/hns3_flow.c | 180 ++++++-------- drivers/net/hns3/hns3_mbx.c | 14 +- drivers/net/hns3/hns3_regs.c | 2 +- drivers/net/hns3/hns3_regs.h | 24 +- drivers/net/hns3/hns3_rss.c | 12 +- drivers/net/hns3/hns3_rss.h | 4 +- drivers/net/hns3/hns3_rxtx.c | 60 +++-- drivers/net/hns3/hns3_rxtx.h | 148 ++++++----- drivers/net/hns3/hns3_rxtx_vec_neon.h | 2 +- drivers/net/hns3/hns3_stats.c | 450 ++++++++++++++++++++++++++-------- drivers/net/hns3/hns3_stats.h | 15 +- 16 files changed, 840 insertions(+), 457 deletions(-) -- 2.7.4

4 20

[PATCH] coresight: Remove duplicate header files of coresight drivers
by Qi Liu 02 Feb '21

02 Feb '21

Remove duplicate included header files, as coresight-priv.h is included in these coresight drivers. Signed-off-by: Qi Liu <liuqi115(a)huawei.com> --- drivers/hwtracing/coresight/coresight-catu.c | 2 -- drivers/hwtracing/coresight/coresight-core.c | 3 --- drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 --- drivers/hwtracing/coresight/coresight-cti-core.c | 3 --- drivers/hwtracing/coresight/coresight-cti-platform.c | 1 - drivers/hwtracing/coresight/coresight-cti.h | 1 - drivers/hwtracing/coresight/coresight-etb10.c | 4 ---- drivers/hwtracing/coresight/coresight-etm-perf.c | 1 - drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 1 - drivers/hwtracing/coresight/coresight-etm4x-core.c | 5 ----- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 1 - drivers/hwtracing/coresight/coresight-funnel.c | 3 --- drivers/hwtracing/coresight/coresight-platform.c | 2 -- drivers/hwtracing/coresight/coresight-replicator.c | 3 --- drivers/hwtracing/coresight/coresight-stm.c | 3 --- drivers/hwtracing/coresight/coresight-tmc-core.c | 3 --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 1 - drivers/hwtracing/coresight/coresight-tmc-etr.c | 1 - drivers/hwtracing/coresight/coresight-tpiu.c | 4 ---- 19 files changed, 45 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index a61313f..fcc0367 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -7,10 +7,8 @@ * Author: Suzuki K Poulose <suzuki.poulose(a)arm.com> */ -#include <linux/amba/bus.h> #include <linux/device.h> #include <linux/dma-mapping.h> -#include <linux/io.h> #include <linux/kernel.h> #include <linux/slab.h> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 4ba801d..5fb8b12 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -7,17 +7,14 @@ #include <linux/init.h> #include <linux/types.h> #include <linux/device.h> -#include <linux/io.h> #include <linux/err.h> #include <linux/export.h> #include <linux/slab.h> #include <linux/stringhash.h> #include <linux/mutex.h> #include <linux/clk.h> -#include <linux/coresight.h> #include <linux/of_platform.h> #include <linux/delay.h> -#include <linux/pm_runtime.h> #include "coresight-etm-perf.h" #include "coresight-priv.h" diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index e1d2324..f8df512 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -4,15 +4,12 @@ * * Author: Leo Yan <leo.yan(a)linaro.org> */ -#include <linux/amba/bus.h> -#include <linux/coresight.h> #include <linux/cpu.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> #include <linux/init.h> -#include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/module.h> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index 61dbc1a..ed7ab82 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -4,18 +4,15 @@ * Author: Mike Leach <mike.leach(a)linaro.org> */ -#include <linux/amba/bus.h> #include <linux/atomic.h> #include <linux/bits.h> #include <linux/coresight.h> #include <linux/cpu_pm.h> #include <linux/cpuhotplug.h> #include <linux/device.h> -#include <linux/io.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/mutex.h> -#include <linux/pm_runtime.h> #include <linux/property.h> #include <linux/spinlock.h> diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c index ccef04f..60b0580 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2019, The Linaro Limited. All rights reserved. */ -#include <linux/coresight.h> #include <linux/device.h> #include <linux/err.h> #include <linux/of.h> diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index acf7b54..0a3b313 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -7,7 +7,6 @@ #ifndef _CORESIGHT_CORESIGHT_CTI_H #define _CORESIGHT_CORESIGHT_CTI_H -#include <linux/coresight.h> #include <linux/device.h> #include <linux/fwnode.h> #include <linux/list.h> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 0cf6f0b..8d5bc04 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -10,17 +10,13 @@ #include <linux/init.h> #include <linux/types.h> #include <linux/device.h> -#include <linux/io.h> #include <linux/err.h> #include <linux/fs.h> #include <linux/miscdevice.h> #include <linux/uaccess.h> #include <linux/slab.h> #include <linux/spinlock.h> -#include <linux/pm_runtime.h> #include <linux/seq_file.h> -#include <linux/coresight.h> -#include <linux/amba/bus.h> #include <linux/clk.h> #include <linux/circ_buf.h> #include <linux/mm.h> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bdc34ca..01aba63 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -4,7 +4,6 @@ * Author: Mathieu Poirier <mathieu.poirier(a)linaro.org> */ -#include <linux/coresight.h> #include <linux/coresight-pmu.h> #include <linux/cpumask.h> #include <linux/device.h> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index e8c7649..5cf6660 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -5,7 +5,6 @@ */ #include <linux/pid_namespace.h> -#include <linux/pm_runtime.h> #include <linux/sysfs.h> #include "coresight-etm.h" #include "coresight-priv.h" diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b20b6ff..0438ef7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -3,13 +3,11 @@ * Copyright (c) 2014, The Linux Foundation. All rights reserved. */ -#include <linux/bitops.h> #include <linux/kernel.h> #include <linux/moduleparam.h> #include <linux/init.h> #include <linux/types.h> #include <linux/device.h> -#include <linux/io.h> #include <linux/err.h> #include <linux/fs.h> #include <linux/slab.h> @@ -20,14 +18,11 @@ #include <linux/clk.h> #include <linux/cpu.h> #include <linux/cpu_pm.h> -#include <linux/coresight.h> #include <linux/coresight-pmu.h> #include <linux/pm_wakeup.h> -#include <linux/amba/bus.h> #include <linux/seq_file.h> #include <linux/uaccess.h> #include <linux/perf_event.h> -#include <linux/pm_runtime.h> #include <linux/property.h> #include <asm/sections.h> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 989ce7b..347ccb7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -5,7 +5,6 @@ */ #include <linux/pid_namespace.h> -#include <linux/pm_runtime.h> #include <linux/sysfs.h> #include "coresight-etm4x.h" #include "coresight-priv.h" diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 071c723..c79ded9 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -15,9 +15,6 @@ #include <linux/slab.h> #include <linux/of.h> #include <linux/platform_device.h> -#include <linux/pm_runtime.h> -#include <linux/coresight.h> -#include <linux/amba/bus.h> #include <linux/clk.h> #include "coresight-priv.h" diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 3629b78..ca22409 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -13,8 +13,6 @@ #include <linux/of_graph.h> #include <linux/of_platform.h> #include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <linux/coresight.h> #include <linux/cpumask.h> #include <asm/smp_plat.h> diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 7e2a2b7..36788de 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -6,14 +6,11 @@ */ #include <linux/acpi.h> -#include <linux/amba/bus.h> #include <linux/kernel.h> #include <linux/device.h> #include <linux/platform_device.h> -#include <linux/io.h> #include <linux/err.h> #include <linux/slab.h> -#include <linux/pm_runtime.h> #include <linux/property.h> #include <linux/clk.h> #include <linux/of.h> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 9979177..75f0bd8 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -17,17 +17,14 @@ */ #include <asm/local.h> #include <linux/acpi.h> -#include <linux/amba/bus.h> #include <linux/bitmap.h> #include <linux/clk.h> -#include <linux/coresight.h> #include <linux/coresight-stm.h> #include <linux/err.h> #include <linux/kernel.h> #include <linux/moduleparam.h> #include <linux/of_address.h> #include <linux/perf_event.h> -#include <linux/pm_runtime.h> #include <linux/stm.h> #include "coresight-priv.h" diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 8169dff..4fff281 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -9,7 +9,6 @@ #include <linux/types.h> #include <linux/device.h> #include <linux/idr.h> -#include <linux/io.h> #include <linux/err.h> #include <linux/fs.h> #include <linux/miscdevice.h> @@ -21,8 +20,6 @@ #include <linux/spinlock.h> #include <linux/pm_runtime.h> #include <linux/of.h> -#include <linux/coresight.h> -#include <linux/amba/bus.h> #include "coresight-priv.h" #include "coresight-tmc.h" diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 989d965..b263f75 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -6,7 +6,6 @@ #include <linux/atomic.h> #include <linux/circ_buf.h> -#include <linux/coresight.h> #include <linux/perf_event.h> #include <linux/slab.h> #include "coresight-priv.h" diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index bf5230e..1ab0b28 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -5,7 +5,6 @@ */ #include <linux/atomic.h> -#include <linux/coresight.h> #include <linux/dma-mapping.h> #include <linux/iommu.h> #include <linux/idr.h> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index d5dfee9..c5675f9 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -9,12 +9,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/device.h> -#include <linux/io.h> #include <linux/err.h> #include <linux/slab.h> -#include <linux/pm_runtime.h> -#include <linux/coresight.h> -#include <linux/amba/bus.h> #include <linux/clk.h> #include "coresight-priv.h" -- 2.8.1

3 2

[PATCH V2 net-next 0/2] net: hns3: updates for -next
by Huazhong Tan 02 Feb '21

02 Feb '21

This patchset adds dump tm info of nodes, priority and qset in debugfs. Three debugfs files tm_nodes, tm_priority and tm_qset are created in new tm directory, and use cat command to dump their info, for examples: $ cat tm_nodes BASE_ID MAX_NUM PG 0 8 PRI 0 8 QSET 0 8 QUEUE 0 1024 $ cat tm_priority ID MODE DWRR C_IR_B C_IR_U C_IR_S C_BS_B C_BS_S C_FLAG C_RATE(Mbps) P_IR_B P_IR_U P_IR_S P_BS_B P_BS_S P_FLAG P_RATE(Mbps) 0000 dwrr 100 0 0 0 5 20 0 0 150 7 0 5 20 0 0 0001 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0002 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0003 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0004 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0005 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0006 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0007 sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $ cat tm_qset ID MAP_PRI LINK_VLD MODE DWRR 0000 0 1 dwrr 100 0001 0 0 sp 0 0002 0 0 sp 0 0003 0 0 sp 0 0004 0 0 sp 0 0005 0 0 sp 0 0006 0 0 sp 0 change log: V2: add readonly files for dump all nodes, priority and qset info suggested by Jakub Kicinski. previous version: V1: https://patchwork.kernel.org/project/netdevbpf/patch/1610694569-43099-1-git… Guangbin Huang (2): net: hns3: add interfaces to query information of tm priority/qset net: hns3: add debugfs support for tm nodes, priority and qset info drivers/net/ethernet/hisilicon/hns3/hnae3.h | 8 + drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 55 +++++- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 1 + .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 153 +++++++++++++++++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 1 + .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 186 +++++++++++++++++++++ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 48 +++++- 8 files changed, 452 insertions(+), 2 deletions(-) -- 2.7.4

3 5

[PATCH 0/2] Add check of 4-byte when parsing SFDP 4bait table
by Yicong Yang 01 Feb '21

01 Feb '21

Add check of 4-byte address mode support when parsing SFDP 4bait. Some flash will provide a 4bait table and the spi-nor core will convert the address mode to 4-byte without checking whether it's actually supported or not by the controller. For example, the 16M s25fs128s1 provides the 4bait and will be convert to 4-byte address mode, which makes it unusable on hisi-sfc-v3xx on hip08 platform. Add the check before convert the address mode when parsing the 4bait will solve this issue. Yicong Yang (2): mtd: spi-nor: check 4-byte address support when parsing 4bait spi: hisi-sfc-v3xx: add address mode check drivers/mtd/spi-nor/sfdp.c | 48 +++++++++++++++++++++++++++++++++++++++++ drivers/spi/spi-hisi-sfc-v3xx.c | 25 ++++++++++++++++++++- 2 files changed, 72 insertions(+), 1 deletion(-) -- 2.8.1

3 5

[PATCH v2] iommu: Check dev->iommu in iommu_dev_xxx functions
by Shameer Kolothum 01 Feb '21

01 Feb '21

The device iommu probe/attach might have failed leaving dev->iommu to NULL and device drivers may still invoke these functions resulting in a crash in iommu vendor driver code. Hence make sure we check that. Also added iommu_ops to the "struct dev_iommu" and set it if the dev is successfully associated with an iommu. Fixes: a3a195929d40 ("iommu: Add APIs for multiple domains per device") Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi(a)huawei.com> --- v1 --> v2: -Added iommu_ops to struct dev_iommu based on the discussion with Robin. -Rebased against iommu-tree core branch. --- drivers/iommu/iommu.c | 19 +++++++------------ include/linux/iommu.h | 2 ++ 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index fd76e2f579fe..6023d0b7c542 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -217,6 +217,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list } dev->iommu->iommu_dev = iommu_dev; + dev->iommu->ops = iommu_dev->ops; group = iommu_group_get_for_dev(dev); if (IS_ERR(group)) { @@ -2865,10 +2866,8 @@ EXPORT_SYMBOL_GPL(iommu_fwspec_add_ids); */ int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat) { - const struct iommu_ops *ops = dev->bus->iommu_ops; - - if (ops && ops->dev_enable_feat) - return ops->dev_enable_feat(dev, feat); + if (dev->iommu && dev->iommu->ops->dev_enable_feat) + return dev->iommu->ops->dev_enable_feat(dev, feat); return -ENODEV; } @@ -2881,10 +2880,8 @@ EXPORT_SYMBOL_GPL(iommu_dev_enable_feature); */ int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat) { - const struct iommu_ops *ops = dev->bus->iommu_ops; - - if (ops && ops->dev_disable_feat) - return ops->dev_disable_feat(dev, feat); + if (dev->iommu && dev->iommu->ops->dev_disable_feat) + return dev->iommu->ops->dev_disable_feat(dev, feat); return -EBUSY; } @@ -2892,10 +2889,8 @@ EXPORT_SYMBOL_GPL(iommu_dev_disable_feature); bool iommu_dev_feature_enabled(struct device *dev, enum iommu_dev_features feat) { - const struct iommu_ops *ops = dev->bus->iommu_ops; - - if (ops && ops->dev_feat_enabled) - return ops->dev_feat_enabled(dev, feat); + if (dev->iommu && dev->iommu->ops->dev_feat_enabled) + return dev->iommu->ops->dev_feat_enabled(dev, feat); return false; } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 524ffc2ff64f..ff0c76bdfb67 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -354,6 +354,7 @@ struct iommu_fault_param { * @fault_param: IOMMU detected device fault reporting data * @fwspec: IOMMU fwspec data * @iommu_dev: IOMMU device this device is linked to + * @ops: iommu-ops for talking to the iommu_dev * @priv: IOMMU Driver private data * * TODO: migrate other per device data pointers under iommu_dev_data, e.g. @@ -364,6 +365,7 @@ struct dev_iommu { struct iommu_fault_param *fault_param; struct iommu_fwspec *fwspec; struct iommu_device *iommu_dev; + const struct iommu_ops *ops; void *priv; }; -- 2.17.1

1 0

[PATCH v3 00/12] add IRQF_NO_AUTOEN for request_irq
by Barry Song 01 Feb '21

01 Feb '21

This patchset added IRQF_NO_AUTOEN for request_irq() and converted drivers/input to this new API. Other drivers will be handled afterwards. -v3: added examples with respect to Greg's comment Barry Song (12): genirq: add IRQF_NO_AUTOEN for request_irq Input: ar1021 - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: atmel_mxt_ts - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: melfas_mip4 - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: bu21029_ts - request_irq by IRQF_NO_AUTOEN and remove irq_set_status_flags Input: stmfts - request_irq by IRQF_NO_AUTOEN and remove irq_set_status_flags Input: zinitix - request_irq by IRQF_NO_AUTOEN and remove irq_set_status_flags Input: mms114 - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: wm831x-ts - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: cyttsp - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: tegra-kbc - request_irq by IRQF_NO_AUTOEN and remove disable_irq Input: tca6416-keypad - request_irq by IRQF_NO_AUTOEN and remove disable_irq drivers/input/keyboard/tca6416-keypad.c | 3 +-- drivers/input/keyboard/tegra-kbc.c | 5 ++--- drivers/input/touchscreen/ar1021_i2c.c | 5 +---- drivers/input/touchscreen/atmel_mxt_ts.c | 5 ++--- drivers/input/touchscreen/bu21029_ts.c | 4 ++-- drivers/input/touchscreen/cyttsp_core.c | 5 ++--- drivers/input/touchscreen/melfas_mip4.c | 5 ++--- drivers/input/touchscreen/mms114.c | 4 ++-- drivers/input/touchscreen/stmfts.c | 3 +-- drivers/input/touchscreen/wm831x-ts.c | 3 +-- drivers/input/touchscreen/zinitix.c | 4 ++-- include/linux/interrupt.h | 3 +++ kernel/irq/manage.c | 8 ++++++++ kernel/irq/settings.h | 10 ++++++++++ 14 files changed, 39 insertions(+), 28 deletions(-) -- 2.25.1

6 19

[GIT PULL v2] arm64: dts: hisilicon dts updates for v5.12
by Wei Xu 30 Jan '21

30 Jan '21

Hi ARM-SoC team, Please consider to pull the following changes. Thanks! Best Regards, Wei --- The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e: Linux 5.11-rc1 (2020-12-27 15:30:22 -0800) are available in the git repository at: git://github.com/hisilicon/linux-hisi.git tags/hisi-arm64-dt-for-5.12v2 for you to fetch changes up to b6e141eec86b730dfeddb888af7d3e0247530ef1: arm64: dts: hisilicon: hi3670.dtsi: add I2C settings (2021-01-29 16:40:07 +0800) ---------------------------------------------------------------- ARM64: DT: Hisilicon ARM64 DT updates for 5.12 - Further cleanups of the hisilicon DTS to align with the dtschema - Add or update the I2C, pinctrl and reset nodes for Hikey970 ---------------------------------------------------------------- Mauro Carvalho Chehab (3): arm64: dts: hisilicon: hi3670.dtsi: add iomcu_rst arm64: dts: hisilicon: hikey970-pinctrl.dtsi: add missing pinctrl settings arm64: dts: hisilicon: hi3670.dtsi: add I2C settings Zhen Lei (6): arm64: dts: hisilicon: separate each group of data in the property "ranges" arm64: dts: hisilicon: place clock-names "bus" before "core" arm64: dts: hisilicon: normalize the node name of the module thermal arm64: dts: hisilicon: normalize the node name of the localbus arm64: dts: hisilicon: avoid irrelevant nodes being mistakenly identified as PHY nodes arm64: dts: hisilicon: delete unused property smmu-cb-memtype arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 6 +- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 77 +++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 +- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 8 +- .../arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi | 632 ++++++++++++++++++++- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 6 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 9 +- 8 files changed, 714 insertions(+), 34 deletions(-)

2 1

question about bonding mode 4
by moyufeng 30 Jan '21

30 Jan '21

Hi Team, I have a question about bonding. During testing bonding mode 4 scenarios, I find that there is a very low probability that the pointer is null. The following information is displayed: [99359.795934] bond0: (slave eth13.2001): Port 2 did not find a suitable aggregator [99359.796960] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000020 [99359.798127] Mem abort info: [99359.798526] ESR = 0x96000004 [99359.798938] EC = 0x25: DABT (current EL), IL = 32 bits [99359.799673] SET = 0, FnV = 0 [99359.800106] EA = 0, S1PTW = 0 [99359.800554] Data abort info: [99359.800952] ISV = 0, ISS = 0x00000004 [99359.801522] CM = 0, WnR = 0 [99359.801970] user pgtable: 4k pages, 48-bit VAs, pgdp=00000000c64e6000 [99359.802876] [0000000000000020] pgd=0000000000000000 [99359.803555] Internal error: Oops: 96000004 [#1] PREEMPT SMP [99359.804369] Modules linked in: bonding hns3(-) hclgevf hnae3 [last unloaded: bonding] [99359.805494] CPU: 1 PID: 951 Comm: kworker/u10:2 Not tainted 5.7.0-rc4+ #1 [99359.806455] Hardware name: linux,dummy-virt (DT) [99359.807107] Workqueue: bond0 bond_3ad_state_machine_handler [bonding] [99359.808056] pstate: 60c00005 (nZCv daif +PAN +UAO) [99359.808722] pc : bond_3ad_state_machine_handler+0x7fc/0xdb8 [bonding] [99359.809652] lr : bond_3ad_state_machine_handler+0x7f4/0xdb8 [bonding] [99359.810535] sp : ffff80001882bd20 [99359.811012] x29: ffff80001882bd20 x28: ffff000085939a38 [99359.811791] x27: ffff00008649bb68 x26: 00000000aaaaaaab [99359.812871] x25: ffff800009401000 x24: ffff800009408de4 [99359.814049] x23: ffff80001882bd98 x22: ffff00008649b880 [99359.815210] x21: 0000000000000000 x20: ffff000085939a00 [99359.816401] x19: ffff00008649b880 x18: ffff800012572988 [99359.817637] x17: 0000000000000000 x16: 0000000000000000 [99359.818870] x15: ffff80009882b987 x14: 726f746167657267 [99359.820090] x13: 676120656c626174 x12: 697573206120646e [99359.821374] x11: 696620746f6e2064 x10: 696420322074726f [99359.822659] x9 : 50203a2931303032 x8 : 0000000000081391 [99359.823891] x7 : ffff8000108e3ad0 x6 : ffff8000128858bb [99359.825109] x5 : 0000000000000000 x4 : 0000000000000000 [99359.826262] x3 : 00000000ffffffff x2 : 906b329bb5362a00 [99359.827394] x1 : 906b329bb5362a00 x0 : 0000000000000000 [99359.828540] Call trace: [99359.829071] bond_3ad_state_machine_handler+0x7fc/0xdb8 [bonding] [99359.830367] process_one_work+0x15c/0x4a0 [99359.831216] worker_thread+0x50/0x478 [99359.832022] kthread+0x130/0x160 [99359.832716] ret_from_fork+0x10/0x18 [99359.833487] Code: 910c0021 95f704bb f9403f80 b5ffe300 (f9401000) [99359.834742] ---[ end trace c7a8e02914afc4e0 ]--- [99359.835817] Kernel panic - not syncing: Fatal exception in interrupt [99359.837334] SMP: stopping secondary CPUs [99359.838277] Kernel Offset: disabled [99359.839086] CPU features: 0x080002,22208218 [99359.840053] Memory Limit: none [99359.840783] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]--- The test procedure is as follows: 1. Configure bonding and set it to mode 4. echo "4" > /sys/class/net/bond0/bonding/mode ifconfig bond0 up 2. Configure two VLANs and add them to the bonding in step 1. vconfig add eth0 2001 vconfig add eth1 2001 ifenslave bond0 eth0.2001 eth1.2001 3. Unload the network device driver and bonding driver. rmmod hns3 rmmod hclge rmmod hnae3 rmmod bonding.ko 4. Repeat the preceding steps for a long time. By checking the logic in ad_port_selection_logic(), I find that if enter the branch "Port %d did not find a suitable aggregator", the value of port->aggregator will be NULL, causing the problem. So I'd like to ask what circumstances will be involved in this branch, and what should be done in this case? The detailed code analysis is as follows: static void ad_port_selection_logic(struct port *port, bool *update_slave_arr) { [...] /* if the port is connected to other aggregator, detach it */ if (port->aggregator) { /* detach the port from its former aggregator */ temp_aggregator = port->aggregator; for (curr_port = temp_aggregator->lag_ports; curr_port; last_port = curr_port, curr_port = curr_port->next_port_in_aggregator) { if (curr_port == port) { temp_aggregator->num_of_ports--; /* if it is the first port attached to the * aggregator */ if (!last_port) { temp_aggregator->lag_ports = port->next_port_in_aggregator; } else { /* not the first port attached to the * aggregator */ last_port->next_port_in_aggregator = port->next_port_in_aggregator; } /* clear the port's relations to this * aggregator */ port->aggregator = NULL; ----analysis: set port->aggregator NULL at the beginning of ad_port_selection_logic(). port->next_port_in_aggregator = NULL; port->actor_port_aggregator_identifier = 0; slave_dbg(bond->dev, port->slave->dev, "Port %d left LAG %d\n", port->actor_port_number, temp_aggregator->aggregator_identifier); /* if the aggregator is empty, clear its * parameters, and set it ready to be attached */ if (!temp_aggregator->lag_ports) ad_clear_agg(temp_aggregator); break; } } if (!curr_port) { /* meaning: the port was related to an aggregator * but was not on the aggregator port list */ net_warn_ratelimited("%s: (slave %s): Warning: Port %d was related to aggregator %d but was not on its port list\n", port->slave->bond->dev->name, port->slave->dev->name, port->actor_port_number, port->aggregator->aggregator_identifier); } } /* search on all aggregators for a suitable aggregator for this port */ bond_for_each_slave(bond, slave, iter) { aggregator = &(SLAVE_AD_INFO(slave)->aggregator); /* keep a free aggregator for later use(if needed) */ if (!aggregator->lag_ports) { if (!free_aggregator) free_aggregator = aggregator; ----analysis: Save free_aggregator if found a free aggregator. But in this case, no free aggregator is available. continue; } /* check if current aggregator suits us */ if (((aggregator->actor_oper_aggregator_key == port->actor_oper_port_key) && /* if all parameters match AND */ MAC_ADDRESS_EQUAL(&(aggregator->partner_system), &(port->partner_oper.system)) && (aggregator->partner_system_priority == port->partner_oper.system_priority) && (aggregator->partner_oper_aggregator_key == port->partner_oper.key) ) && ((!MAC_ADDRESS_EQUAL(&(port->partner_oper.system), &(null_mac_addr)) && /* partner answers */ !aggregator->is_individual) /* but is not individual OR */ ) ) { /* attach to the founded aggregator */ port->aggregator = aggregator; ----analysis: If a proper aggregator is found, port->aggregator is assigned here. port->actor_port_aggregator_identifier = port->aggregator->aggregator_identifier; port->next_port_in_aggregator = aggregator->lag_ports; port->aggregator->num_of_ports++; aggregator->lag_ports = port; slave_dbg(bond->dev, slave->dev, "Port %d joined LAG %d (existing LAG)\n", port->actor_port_number, port->aggregator->aggregator_identifier); /* mark this port as selected */ port->sm_vars |= AD_PORT_SELECTED; found = 1; ----analysis: Set found to 1 if port->aggregator is assigned. break; } } /* the port couldn't find an aggregator - attach it to a new * aggregator */ if (!found) { if (free_aggregator) { /* assign port a new aggregator */ port->aggregator = free_aggregator; ----analysis: No proper free_aggregator is found. Therefore, port->aggregator cannot be assigned here. port->actor_port_aggregator_identifier = port->aggregator->aggregator_identifier; /* update the new aggregator's parameters * if port was responsed from the end-user */ if (port->actor_oper_port_key & AD_DUPLEX_KEY_MASKS) /* if port is full duplex */ port->aggregator->is_individual = false; else port->aggregator->is_individual = true; port->aggregator->actor_admin_aggregator_key = port->actor_admin_port_key; port->aggregator->actor_oper_aggregator_key = port->actor_oper_port_key; port->aggregator->partner_system = port->partner_oper.system; port->aggregator->partner_system_priority = port->partner_oper.system_priority; port->aggregator->partner_oper_aggregator_key = port->partner_oper.key; port->aggregator->receive_state = 1; port->aggregator->transmit_state = 1; port->aggregator->lag_ports = port; port->aggregator->num_of_ports++; /* mark this port as selected */ port->sm_vars |= AD_PORT_SELECTED; slave_dbg(bond->dev, port->slave->dev, "Port %d joined LAG %d (new LAG)\n", port->actor_port_number, port->aggregator->aggregator_identifier); } else { slave_err(bond->dev, port->slave->dev, "Port %d did not find a suitable aggregator\n", port->actor_port_number); ----analysis: The fault scenario goes to this branch, and port->aggregator remains NULL. } } /* if all aggregator's ports are READY_N == TRUE, set ready=TRUE * in all aggregator's ports, else set ready=FALSE in all * aggregator's ports */ __set_agg_ports_ready(port->aggregator, __agg_ports_are_ready(port->aggregator)); ----analysis: port->aggregator is still NULL, which causes problem. aggregator = __get_first_agg(port); ad_agg_selection_logic(aggregator, update_slave_arr); if (!port->aggregator->is_active) port->actor_oper_port_state &= ~LACP_STATE_SYNCHRONIZATION; } Thanks.

2 3

[PATCH for-next] RDMA/hns: Add support of direct wqe
by Weihang Li 30 Jan '21

30 Jan '21

From: Yixing Liu <liuyixing1(a)huawei.com> Direct wqe is a mechanism to fill wqe directly into the hardware. In the case of light load, the wqe will be filled into pcie bar space of the hardware, this will reduce one memory access operation and therefore reduce the latency. Signed-off-by: Yixing Liu <liuyixing1(a)huawei.com> Signed-off-by: Lang Cheng <chenglang(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_device.h | 6 ++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 44 ++++++++++++++++++++++++++++- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 14 +++++++++ 3 files changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index c46b330..6abf7d8 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -90,6 +90,7 @@ #define HNS_ROCE_MAX_PORTS 6 #define HNS_ROCE_GID_SIZE 16 #define HNS_ROCE_SGE_SIZE 16 +#define HNS_ROCE_DWQE_SIZE 65536 #define HNS_ROCE_HOP_NUM_0 0xff @@ -644,6 +645,10 @@ struct hns_roce_work { u32 queue_num; }; +enum { + HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5), +}; + struct hns_roce_qp { struct ib_qp ibqp; struct hns_roce_wq rq; @@ -986,6 +991,7 @@ struct hns_roce_dev { struct mutex pgdir_mutex; int irq[HNS_ROCE_MAX_IRQ_NUM]; u8 __iomem *reg_base; + void __iomem *mem_base; struct hns_roce_caps caps; struct xarray qp_table_xa; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 4c06889..0d26079 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -503,6 +503,8 @@ static inline int set_ud_wqe(struct hns_roce_qp *qp, if (ret) return ret; + qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; + set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); /* @@ -635,6 +637,8 @@ static inline void update_sq_db(struct hns_roce_dev *hr_dev, V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); + /* indicates data on new BAR, 0 : SQ doorbell, 1 : DWQE */ + roce_set_bit(sq_db.byte_4, V2_DB_FLAG_S, 0); roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, V2_DB_PARAMETER_IDX_S, qp->sq.head); roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, @@ -644,6 +648,38 @@ static inline void update_sq_db(struct hns_roce_dev *hr_dev, } } +static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, + u64 __iomem *dest) +{ +#define HNS_ROCE_WRITE_TIMES 8 + struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; + struct hnae3_handle *handle = priv->handle; + const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + int i; + + if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) + for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) + writeq_relaxed(*(val + i), dest + i); +} + +static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, + void *wqe) +{ + struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; + + /* All kinds of DirectWQE have the same header field layout */ + roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M, + V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M, + V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, + V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); + + hns_roce_write512(hr_dev, wqe, hr_dev->mem_base + + HNS_ROCE_DWQE_SIZE * qp->ibqp.qp_num); +} + static int hns_roce_v2_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) @@ -710,7 +746,12 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, qp->next_sge = sge_idx; /* Memory barrier */ wmb(); - update_sq_db(hr_dev, qp); + + if (nreq == 1 && qp->sq.head == qp->sq.tail + 1 && + (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) + write_dwqe(hr_dev, qp, wqe); + else + update_sq_db(hr_dev, qp); } spin_unlock_irqrestore(&qp->sq.lock, flags); @@ -6286,6 +6327,7 @@ static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, /* Get info from NIC driver. */ hr_dev->reg_base = handle->rinfo.roce_io_base; + hr_dev->mem_base = handle->rinfo.roce_mem_base; hr_dev->caps.num_ports = 1; hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; hr_dev->iboe.phy_port[0] = 0; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index bdaccf8..badc1c9 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -97,6 +97,7 @@ #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 #define HNS_ROCE_INVALID_LKEY 0x100 + #define HNS_ROCE_CMQ_TX_TIMEOUT 30000 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2 #define HNS_ROCE_V2_RSV_QPS 8 @@ -1059,6 +1060,8 @@ struct hns_roce_v2_mpt_entry { #define V2_DB_BYTE_4_CMD_S 24 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) +#define V2_DB_FLAG_S 31 + #define V2_DB_PARAMETER_IDX_S 0 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0) @@ -1155,6 +1158,15 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5 +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5) + +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13 +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13) + +#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15 +#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15) + #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 @@ -1177,6 +1189,8 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23 +#define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31 + #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) -- 2.8.1

2 1

[PATCH 0/5] hisi_sas: More misc patches
by John Garry 30 Jan '21

30 Jan '21

This is a collection of misc patches picked up during the latest dev cycle, targeted at 5.12 . Features include: - Some tidy-up from after recent change to expose HW queues on v2 HW - Add trace FIFO DFX debugfs support - Flush wq for driver removal - Add ability to enable debugfs support as a kernel config option Thanks! John Garry (2): scsi: hisi_sas: Remove deferred probe check in hisi_sas_v2_probe() scsi: hisi_sas: Don't check .nr_hw_queues in hisi_sas_task_prep() Luo Jiaxing (3): scsi: hisi_sas: Enable debugfs support by default scsi: hisi_sas: Flush workqueue in hisi_sas_v3_remove() scsi: hisi_sas: Add trace FIFO debugfs support drivers/scsi/hisi_sas/Kconfig | 6 + drivers/scsi/hisi_sas/hisi_sas.h | 15 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 19 +- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 12 -- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 252 +++++++++++++++++++++++++ 5 files changed, 286 insertions(+), 18 deletions(-) -- 2.26.2

2 7

Question about the mechanism of RoCEv2 VLAN validation
by liweihang 29 Jan '21

29 Jan '21

Hi All, I'm confusing at the VLAN validation mechanism of RoCEv2. Assuming that we have two nodes with an HCA that supports RoCE v2. And we add a VLAN (id = 1) on each nodes, but they are of different network segments. The IP and VLAN configuration are as follows: NODE_A NODE_B +--------+---------------+------+ +--------+---------------+------+ | device | IP | VLAN | | device | IP | VLAN | +--------+---------------+------+ +--------+---------------+------+ | eth0 | 192.168.97.1 | 0 | /----| eth0 | 192.168.100.2 | 0 | +--------+---------------+------+ / +--------+---------------+------+ | eth0.1 | 192.168.100.3 | 1 |---/ | eth0.1 | 192.168.98.2 | 1 | +--------+---------------+------+ +--------+---------------+------+ Now I try to ping eth0 on NODE_B from eth0.1 on NODE_A, of cource it fails becauce these devices are using different VLAN ID. Then I do some tests on RoCE, the first one is a simple RC send test: NODE_A: ib_send_bw -d mlx5_0 -x 5 (the sgid 5 belongs to eth0.1) NODE_B: ib_send_bw -d mlx5_0 -x 3 <server ip> (the sgid 3 belongs to eth0) The result is as expected, the RoCEv2 packet with unmatched VLAN ID was dropped. I think the reason is that for RC service, the VLAN information of a QP is recorded in QPC, and the HCA can check it when receiving a packet. But when I run a simple UD send test: NODE_A: ib_send_bw -d mlx5_0 -x 5 -c UD (the sgid 5 belongs to eth0.1) NODE_B: ib_send_bw -d mlx5_0 -x 3 -c UD <server ip> (the sgid 3 belongs to eth0) The test ends without error successfully. So the question is, RoCEv2 is based on Ethernet, shouldn't a RoCEv2 node check the VLAN ID of every incoming packets? UD is connectionless-oriented, an UD QP won't record VLAN info in it's QPC, so how to achieve the checking mechanism? Or a UD QP should just ignore the unmatched VLAN ID? I didn't find any info from the IB specification, I'd appreciate it if someone could help explain it. Thanks Weihang

2 2

[RFC PATCH v2] sched/topology: fix the issue groups don't span domain->span for NUMA diameter > 2
by Barry Song 29 Jan '21

29 Jan '21

As long as NUMA diameter > 2, building sched_domain by sibling's child domain will definitely create a sched_domain with sched_group which will span out of the sched_domain +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 node2 node3 domain1 node0+1 node0+1 node2+3 node2+3 + domain2 node0+1+2 | group: node0+1 | group:node2+3 <-------------------+ when node2 is added into the domain2 of node0, kernel is using the child domain of node2's domain2, which is domain1(node2+3). Node 3 is outside the span of the domain including node0+1+2. This will make load_balance() and select_task_rq_fair() run on wrong CPU and base on avg load. here we move to use the *child* domain of the *child* domain of node2's domain2 to build the sched_group. +------+ +------+ +-------+ +------+ | node | 12 |node | 20 | node | 12 |node | | 0 +---------+1 +--------+ 2 +-------+3 | +------+ +------+ +-------+ +------+ domain0 node0 node1 +- node2 node3 | domain1 node0+1 node0+1 | node2+3 node2+3 | domain2 node0+1+2 | group: node0+1 | group:node2 <-------------------+ A tricky thing is that we shouldn't use the first cpu of node2 as the unique ID for the sched_group generated by grandchild, otherwise, when this cpu becomes the balance_cpu of another sched_group of cpus other than node0, our sched_group generated by grandchild will have same ID with another sched_group generated by child in init_overlap_sched_group(): build_balance_mask(sd, sg, mask); cpu = cpumask_first_and(sched_group_span(sg), mask); sg->sgc = *per_cpu_ptr(sdd->sgc, cpu); So here we move to use the second cpu. But we can put the cpu back during load_balance by using sched_group_span rather than group_balance_mask. For the corner case, if NUMA has only one CPU, we will get to a warning WARN_ON_ONCE here: static void init_overlap_sched_group(struct sched_domain *sd, struct sched_group *sg) { if (atomic_inc_return(&sg->sgc->ref) == 1) cpumask_copy(group_balance_mask(sg), mask); else WARN_ON_ONCE(!cpumask_equal(group_balance_mask(sg), mask)); } But It is pretty much not a real case. Tested by the below topology: qemu-system-aarch64 -M virt -nographic \ -smp cpus=8 \ -numa node,cpus=0-1,nodeid=0 \ -numa node,cpus=2-3,nodeid=1 \ -numa node,cpus=4-5,nodeid=2 \ -numa node,cpus=6-7,nodeid=3 \ -numa dist,src=0,dst=1,val=12 \ -numa dist,src=0,dst=2,val=20 \ -numa dist,src=0,dst=3,val=22 \ -numa dist,src=1,dst=2,val=22 \ -numa dist,src=2,dst=3,val=12 \ -numa dist,src=1,dst=3,val=24 \ -m 4G -cpu cortex-a57 -kernel arch/arm64/boot/Image w/o patch, we get lots of "groups don't span domain->span": [ 0.802139] CPU0 attaching sched-domain(s): [ 0.802193] domain-0: span=0-1 level=MC [ 0.802443] groups: 0:{ span=0 cap=1013 }, 1:{ span=1 cap=979 } [ 0.802693] domain-1: span=0-3 level=NUMA [ 0.802731] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.802811] domain-2: span=0-5 level=NUMA [ 0.802829] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.802881] ERROR: groups don't span domain->span [ 0.803058] domain-3: span=0-7 level=NUMA [ 0.803080] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804055] CPU1 attaching sched-domain(s): [ 0.804072] domain-0: span=0-1 level=MC [ 0.804096] groups: 1:{ span=1 cap=979 }, 0:{ span=0 cap=1013 } [ 0.804152] domain-1: span=0-3 level=NUMA [ 0.804170] groups: 0:{ span=0-1 cap=1992 }, 2:{ span=2-3 cap=1943 } [ 0.804219] domain-2: span=0-5 level=NUMA [ 0.804236] groups: 0:{ span=0-3 cap=3935 }, 4:{ span=4-7 cap=3937 } [ 0.804302] ERROR: groups don't span domain->span [ 0.804520] domain-3: span=0-7 level=NUMA [ 0.804546] groups: 0:{ span=0-5 mask=0-1 cap=5843 }, 6:{ span=4-7 mask=6-7 cap=4077 } [ 0.804677] CPU2 attaching sched-domain(s): [ 0.804687] domain-0: span=2-3 level=MC [ 0.804705] groups: 2:{ span=2 cap=934 }, 3:{ span=3 cap=1009 } [ 0.804754] domain-1: span=0-3 level=NUMA [ 0.804772] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.804820] domain-2: span=0-5 level=NUMA [ 0.804836] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.804944] ERROR: groups don't span domain->span [ 0.805108] domain-3: span=0-7 level=NUMA [ 0.805134] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805223] CPU3 attaching sched-domain(s): [ 0.805232] domain-0: span=2-3 level=MC [ 0.805249] groups: 3:{ span=3 cap=1009 }, 2:{ span=2 cap=934 } [ 0.805319] domain-1: span=0-3 level=NUMA [ 0.805336] groups: 2:{ span=2-3 cap=1943 }, 0:{ span=0-1 cap=1992 } [ 0.805383] domain-2: span=0-5 level=NUMA [ 0.805399] groups: 2:{ span=0-3 mask=2-3 cap=3991 }, 4:{ span=0-1,4-7 mask=4-5 cap=5985 } [ 0.805458] ERROR: groups don't span domain->span [ 0.805605] domain-3: span=0-7 level=NUMA [ 0.805626] groups: 2:{ span=0-5 mask=2-3 cap=5899 }, 6:{ span=0-1,4-7 mask=6-7 cap=6125 } [ 0.805712] CPU4 attaching sched-domain(s): [ 0.805721] domain-0: span=4-5 level=MC [ 0.805738] groups: 4:{ span=4 cap=984 }, 5:{ span=5 cap=924 } [ 0.805787] domain-1: span=4-7 level=NUMA [ 0.805803] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.805851] domain-2: span=0-1,4-7 level=NUMA [ 0.805867] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.805915] ERROR: groups don't span domain->span [ 0.806108] domain-3: span=0-7 level=NUMA [ 0.806130] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.806214] CPU5 attaching sched-domain(s): [ 0.806222] domain-0: span=4-5 level=MC [ 0.806240] groups: 5:{ span=5 cap=924 }, 4:{ span=4 cap=984 } [ 0.806841] domain-1: span=4-7 level=NUMA [ 0.806866] groups: 4:{ span=4-5 cap=1908 }, 6:{ span=6-7 cap=2029 } [ 0.806934] domain-2: span=0-1,4-7 level=NUMA [ 0.806953] groups: 4:{ span=4-7 cap=3937 }, 0:{ span=0-3 cap=3935 } [ 0.807004] ERROR: groups don't span domain->span [ 0.807312] domain-3: span=0-7 level=NUMA [ 0.807386] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5985 }, 2:{ span=0-3 mask=2-3 cap=3991 } [ 0.807686] CPU6 attaching sched-domain(s): [ 0.807710] domain-0: span=6-7 level=MC [ 0.807750] groups: 6:{ span=6 cap=1017 }, 7:{ span=7 cap=1012 } [ 0.807840] domain-1: span=4-7 level=NUMA [ 0.807870] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.807952] domain-2: span=0-1,4-7 level=NUMA [ 0.807985] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.808045] ERROR: groups don't span domain->span [ 0.808257] domain-3: span=0-7 level=NUMA [ 0.808571] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6125 }, 2:{ span=0-5 mask=2-3 cap=5899 } [ 0.808848] CPU7 attaching sched-domain(s): [ 0.808860] domain-0: span=6-7 level=MC [ 0.808880] groups: 7:{ span=7 cap=1012 }, 6:{ span=6 cap=1017 } [ 0.808953] domain-1: span=4-7 level=NUMA [ 0.808974] groups: 6:{ span=6-7 cap=2029 }, 4:{ span=4-5 cap=1908 } [ 0.809034] domain-2: span=0-1,4-7 level=NUMA [ 0.809055] groups: 6:{ span=4-7 mask=6-7 cap=4077 }, 0:{ span=0-5 mask=0-1 cap=5843 } [ 0.809128] ERROR: groups don't span domain->span [ 0.810361] domain-3: span=0-7 level=NUMA [ 0.810400] groups: 6:{ span=0-1,4-7 mask=6-7 cap=5961 }, 2:{ span=0-5 mask=2-3 cap=5903 } w/ patch, we get no "groups don't span domain->span": [ 0.868907] CPU0 attaching sched-domain(s): [ 0.868962] domain-0: span=0-1 level=MC [ 0.869179] groups: 0:{ span=0 cap=1013 }, 1:{ span=1 cap=983 } [ 0.869405] domain-1: span=0-3 level=NUMA [ 0.869438] groups: 0:{ span=0-1 cap=1996 }, 2:{ span=2-3 cap=2006 } [ 0.869542] domain-2: span=0-5 level=NUMA [ 0.869559] groups: 0:{ span=0-3 cap=4002 }, 5:{ span=4-5 cap=2048 } [ 0.869603] domain-3: span=0-7 level=NUMA [ 0.869618] groups: 0:{ span=0-5 mask=0-1 cap=5980 }, 6:{ span=4-7 mask=6-7 cap=4016 } [ 0.870303] CPU1 attaching sched-domain(s): [ 0.870314] domain-0: span=0-1 level=MC [ 0.870334] groups: 1:{ span=1 cap=983 }, 0:{ span=0 cap=1013 } [ 0.870381] domain-1: span=0-3 level=NUMA [ 0.870396] groups: 0:{ span=0-1 cap=1996 }, 2:{ span=2-3 cap=2006 } [ 0.870440] domain-2: span=0-5 level=NUMA [ 0.870454] groups: 0:{ span=0-3 cap=4002 }, 5:{ span=4-5 cap=2048 } [ 0.870507] domain-3: span=0-7 level=NUMA [ 0.870530] groups: 0:{ span=0-5 mask=0-1 cap=5980 }, 6:{ span=4-7 mask=6-7 cap=4016 } [ 0.870611] CPU2 attaching sched-domain(s): [ 0.870619] domain-0: span=2-3 level=MC [ 0.870634] groups: 2:{ span=2 cap=1007 }, 3:{ span=3 cap=999 } [ 0.870677] domain-1: span=0-3 level=NUMA [ 0.870691] groups: 2:{ span=2-3 cap=2006 }, 0:{ span=0-1 cap=1996 } [ 0.870734] domain-2: span=0-5 level=NUMA [ 0.870748] groups: 2:{ span=0-3 mask=2-3 cap=4054 }, 5:{ span=4-5 cap=2048 } [ 0.870795] domain-3: span=0-7 level=NUMA [ 0.870809] groups: 2:{ span=0-5 mask=2-3 cap=6032 }, 6:{ span=0-1,4-7 mask=6-7 cap=6064 } [ 0.870913] CPU3 attaching sched-domain(s): [ 0.870921] domain-0: span=2-3 level=MC [ 0.870936] groups: 3:{ span=3 cap=999 }, 2:{ span=2 cap=1007 } [ 0.870979] domain-1: span=0-3 level=NUMA [ 0.870993] groups: 2:{ span=2-3 cap=2006 }, 0:{ span=0-1 cap=1996 } [ 0.871035] domain-2: span=0-5 level=NUMA [ 0.871049] groups: 2:{ span=0-3 mask=2-3 cap=4054 }, 5:{ span=4-5 cap=2048 } [ 0.871096] domain-3: span=0-7 level=NUMA [ 0.871110] groups: 2:{ span=0-5 mask=2-3 cap=6032 }, 6:{ span=0-1,4-7 mask=6-7 cap=6064 } [ 0.871177] CPU4 attaching sched-domain(s): [ 0.871185] domain-0: span=4-5 level=MC [ 0.871200] groups: 4:{ span=4 cap=977 }, 5:{ span=5 cap=1001 } [ 0.871243] domain-1: span=4-7 level=NUMA [ 0.871257] groups: 4:{ span=4-5 cap=1978 }, 6:{ span=6-7 cap=1968 } [ 0.871300] domain-2: span=0-1,4-7 level=NUMA [ 0.871314] groups: 4:{ span=4-7 cap=3946 }, 1:{ span=0-1 cap=2048 } [ 0.871356] domain-3: span=0-7 level=NUMA [ 0.871370] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5994 }, 2:{ span=0-3 mask=2-3 cap=4054 } [ 0.871436] CPU5 attaching sched-domain(s): [ 0.871443] domain-0: span=4-5 level=MC [ 0.871457] groups: 5:{ span=5 cap=1001 }, 4:{ span=4 cap=977 } [ 0.871512] domain-1: span=4-7 level=NUMA [ 0.871893] groups: 4:{ span=4-5 cap=1978 }, 6:{ span=6-7 cap=1968 } [ 0.871949] domain-2: span=0-1,4-7 level=NUMA [ 0.871966] groups: 4:{ span=4-7 cap=3946 }, 1:{ span=0-1 cap=2048 } [ 0.872010] domain-3: span=0-7 level=NUMA [ 0.872025] groups: 4:{ span=0-1,4-7 mask=4-5 cap=5994 }, 2:{ span=0-3 mask=2-3 cap=4054 } [ 0.872115] CPU6 attaching sched-domain(s): [ 0.872123] domain-0: span=6-7 level=MC [ 0.872139] groups: 6:{ span=6 cap=993 }, 7:{ span=7 cap=975 } [ 0.872186] domain-1: span=4-7 level=NUMA [ 0.872202] groups: 6:{ span=6-7 cap=1968 }, 4:{ span=4-5 cap=1978 } [ 0.872246] domain-2: span=0-1,4-7 level=NUMA [ 0.872260] groups: 6:{ span=4-7 mask=6-7 cap=4016 }, 1:{ span=0-1 cap=2048 } [ 0.872309] domain-3: span=0-7 level=NUMA [ 0.872323] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6064 }, 2:{ span=0-5 mask=2-3 cap=6032 } [ 0.872392] CPU7 attaching sched-domain(s): [ 0.872399] domain-0: span=6-7 level=MC [ 0.872414] groups: 7:{ span=7 cap=975 }, 6:{ span=6 cap=993 } [ 0.872458] domain-1: span=4-7 level=NUMA [ 0.872472] groups: 6:{ span=6-7 cap=1968 }, 4:{ span=4-5 cap=1978 } [ 0.872662] domain-2: span=0-1,4-7 level=NUMA [ 0.872685] groups: 6:{ span=4-7 mask=6-7 cap=4016 }, 1:{ span=0-1 cap=2048 } [ 0.872737] domain-3: span=0-7 level=NUMA [ 0.872752] groups: 6:{ span=0-1,4-7 mask=6-7 cap=6064 }, 2:{ span=0-5 mask=2-3 cap=6032 } Reported-by: Valentin Schneider <valentin.schneider(a)arm.com> Cc: Meelis Roos <mroos(a)linux.ee> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- -v2: fix the span of sched_group rather than hacking the load balance to compensate the topology problem(thanks for the comments of Vincent and Valentin) v1 link: https://lore.kernel.org/lkml/20210115203632.34396-1-song.bao.hua@hisilicon.… kernel/sched/fair.c | 9 ++++- kernel/sched/sched.h | 1 + kernel/sched/topology.c | 84 ++++++++++++++++++++++++++--------------- 3 files changed, 63 insertions(+), 31 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index f183dba4961e..3ce815045793 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -9538,6 +9538,7 @@ static int should_we_balance(struct lb_env *env) { struct sched_group *sg = env->sd->groups; int cpu; + struct cpumask *mask; /* * Ensure the balancing environment is consistent; can happen @@ -9553,8 +9554,14 @@ static int should_we_balance(struct lb_env *env) if (env->idle == CPU_NEWLY_IDLE) return 1; + /* + * in build_balance_mask(), we removed the first cpu from the + * balance_mask of the sched_group generated by grandchild; + * the first cpu should be able to pull task if it is idle. + */ + mask = sg->from_grandchild ? sched_group_span(sg) : group_balance_mask(sg); /* Try to find first idle CPU */ - for_each_cpu_and(cpu, group_balance_mask(sg), env->cpus) { + for_each_cpu_and(cpu, mask, env->cpus) { if (!idle_cpu(cpu)) continue; diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 12ada79d40f3..3ad282fdc5b1 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1508,6 +1508,7 @@ struct sched_group { unsigned int group_weight; struct sched_group_capacity *sgc; int asym_prefer_cpu; /* CPU of highest priority in group */ + int from_grandchild; /* this sched_group comes from grandchild */ /* * The CPUs this group covers. diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 5d3675c7a76b..23099f6dc034 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -93,7 +93,7 @@ static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level, group->sgc->id, cpumask_pr_args(sched_group_span(group))); - if ((sd->flags & SD_OVERLAP) && + if ((sd->flags & SD_OVERLAP) && !group->from_grandchild && !cpumask_equal(group_balance_mask(group), sched_group_span(group))) { printk(KERN_CONT " mask=%*pbl", cpumask_pr_args(group_balance_mask(group))); @@ -723,35 +723,6 @@ cpu_attach_domain(struct sched_domain *sd, struct root_domain *rd, int cpu) for (tmp = sd; tmp; tmp = tmp->parent) numa_distance += !!(tmp->flags & SD_NUMA); - /* - * FIXME: Diameter >=3 is misrepresented. - * - * Smallest diameter=3 topology is: - * - * node 0 1 2 3 - * 0: 10 20 30 40 - * 1: 20 10 20 30 - * 2: 30 20 10 20 - * 3: 40 30 20 10 - * - * 0 --- 1 --- 2 --- 3 - * - * NUMA-3 0-3 N/A N/A 0-3 - * groups: {0-2},{1-3} {1-3},{0-2} - * - * NUMA-2 0-2 0-3 0-3 1-3 - * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} - * - * NUMA-1 0-1 0-2 1-3 2-3 - * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} - * - * NUMA-0 0 1 2 3 - * - * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the - * group span isn't a subset of the domain span. - */ - WARN_ONCE(numa_distance > 2, "Shortest NUMA path spans too many nodes\n"); - sched_domain_debug(sd, cpu); rq_attach_root(rq, rd); @@ -906,6 +877,7 @@ build_balance_mask(struct sched_domain *sd, struct sched_group *sg, struct cpuma cpumask_clear(mask); for_each_cpu(i, sg_span) { + int from_grandchild = 0; sibling = *per_cpu_ptr(sdd->sd, i); /* @@ -916,10 +888,27 @@ build_balance_mask(struct sched_domain *sd, struct sched_group *sg, struct cpuma if (!sibling->child) continue; + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + sched_domain_span(sd))) { + sibling = sibling->child; + from_grandchild = 1; + } + /* If we would not end up here, we can't continue from here */ if (!cpumask_equal(sg_span, sched_domain_span(sibling->child))) continue; + sg->from_grandchild = from_grandchild; + /* + * use cpu other than the first one as the unique ID of this group + * otherwise, the ID will conflict with another sched_group coming + * from child rather than grandchild + */ + if (from_grandchild && i == cpumask_first(sg_span) && + cpumask_weight(sg_span) > 1) + continue; + cpumask_set_cpu(i, mask); } @@ -1015,6 +1004,41 @@ build_overlap_sched_groups(struct sched_domain *sd, int cpu) if (!cpumask_test_cpu(i, sched_domain_span(sibling))) continue; + /* + * for NUMA diameter >= 3, building sched_domain by sibling's + * child's child domain to prevent sched_group from spanning + * out of sched_domain + * if we don't do this, Diameter >=3 is misrepresented: + * + * Smallest diameter=3 topology is: + * + * node 0 1 2 3 + * 0: 10 20 30 40 + * 1: 20 10 20 30 + * 2: 30 20 10 20 + * 3: 40 30 20 10 + * + * 0 --- 1 --- 2 --- 3 + * + * NUMA-3 0-3 N/A N/A 0-3 + * groups: {0-2},{1-3} {1-3},{0-2} + * + * NUMA-2 0-2 0-3 0-3 1-3 + * groups: {0-1},{1-3} {0-2},{2-3} {1-3},{0-1} {2-3},{0-2} + * + * NUMA-1 0-1 0-2 1-3 2-3 + * groups: {0},{1} {1},{2},{0} {2},{3},{1} {3},{2} + * + * NUMA-0 0 1 2 3 + * + * The NUMA-2 groups for nodes 0 and 3 are obviously buggered, as the + * group span isn't a subset of the domain span. + */ + while (sibling->child && + !cpumask_subset(sched_domain_span(sibling->child), + span)) + sibling = sibling->child; + sg = build_group_from_child_sched_domain(sibling, cpu); if (!sg) goto fail; -- 2.25.1

2 1

[PATCH v2 0/4] perf vendor events arm64: Some tidy-up/refactoring
by John Garry 29 Jan '21

29 Jan '21

There is much event duplication in the common and uarch events for A76 and Ampere eMag support, so factor out into a common JSON. Since the wording for events may differ between CPU datasheet and the architecture reference manual, the current wording is kept. This is unless there are minor differences. In addition, event names are renamed to be same as architecture reference manual, to keep commonality. Also a minor fix is included for the Ampere eMag JSON. Differences to v1: - tidy some ',' misplaced John Garry (4): perf vendor events arm64: Fix Ampere eMag event typo perf vendor events arm64: Add common and uarch event JSON perf vendor events arm64: Reference common and uarch events for Ampere eMag perf vendor events arm64: Reference common and uarch events for A76 .../arch/arm64/ampere/emag/branch.json | 8 +- .../arch/arm64/ampere/emag/bus.json | 5 +- .../arch/arm64/ampere/emag/cache.json | 58 +--- .../arch/arm64/ampere/emag/clock.json | 4 +- .../arch/arm64/ampere/emag/exception.json | 10 +- .../arch/arm64/ampere/emag/instruction.json | 34 +-- .../arch/arm64/ampere/emag/memory.json | 11 +- .../arch/arm64/arm/cortex-a76-n1/branch.json | 12 +- .../arch/arm64/arm/cortex-a76-n1/bus.json | 19 +- .../arch/arm64/arm/cortex-a76-n1/cache.json | 118 +++------ .../arm64/arm/cortex-a76-n1/exception.json | 10 +- .../arm64/arm/cortex-a76-n1/instruction.json | 45 +--- .../arch/arm64/arm/cortex-a76-n1/memory.json | 6 +- .../arch/arm64/arm/cortex-a76-n1/other.json | 4 +- .../arm64/arm/cortex-a76-n1/pipeline.json | 12 +- .../arm64/armv8-common-and-microarch.json | 248 ++++++++++++++++++ 16 files changed, 356 insertions(+), 248 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json -- 2.26.2

2 5

[PATCH v2 for-next 0/3] RDMA/hns: Refactor codes about memory
by Weihang Li 29 Jan '21

29 Jan '21

This series refactors memory related codes, including MR, MTR(Memory Translate Region) and MPT(Memory Protection Table). Changes since v1: * Add static keyword for hns_roce_mr_free(). * Link: https://patchwork.kernel.org/project/linux-rdma/cover/1611236882-41498-1-gi… Lang Cheng (2): RDMA/hns: Optimize the MR registration process RDMA/hns: Use new interface to set MPT related fields Xi Wang (1): RDMA/hns: Refactor the MTR creation flow drivers/infiniband/hw/hns/hns_roce_common.h | 22 ++ drivers/infiniband/hw/hns/hns_roce_cq.c | 1 - drivers/infiniband/hw/hns/hns_roce_device.h | 5 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 77 +++--- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 39 +++ drivers/infiniband/hw/hns/hns_roce_mr.c | 401 +++++++++++----------------- drivers/infiniband/hw/hns/hns_roce_qp.c | 1 - drivers/infiniband/hw/hns/hns_roce_srq.c | 2 - 8 files changed, 257 insertions(+), 291 deletions(-) -- 2.8.1

2 4

[PATCH] iommu: Check dev->iommu in iommu_dev_xxx functions
by Shameer Kolothum 28 Jan '21

28 Jan '21

The device iommu probe/attach might have failed leaving dev->iommu to NULL and device drivers may still invoke these functions resulting a crash in iommu vendor driver code. Hence make sure we check that. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi(a)huawei.com> --- drivers/iommu/iommu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index ffeebda8d6de..cb68153c5cc0 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2867,7 +2867,7 @@ bool iommu_dev_has_feature(struct device *dev, enum iommu_dev_features feat) { const struct iommu_ops *ops = dev->bus->iommu_ops; - if (ops && ops->dev_has_feat) + if (dev->iommu && ops && ops->dev_has_feat) return ops->dev_has_feat(dev, feat); return false; @@ -2878,7 +2878,7 @@ int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat) { const struct iommu_ops *ops = dev->bus->iommu_ops; - if (ops && ops->dev_enable_feat) + if (dev->iommu && ops && ops->dev_enable_feat) return ops->dev_enable_feat(dev, feat); return -ENODEV; @@ -2894,7 +2894,7 @@ int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat) { const struct iommu_ops *ops = dev->bus->iommu_ops; - if (ops && ops->dev_disable_feat) + if (dev->iommu && ops && ops->dev_disable_feat) return ops->dev_disable_feat(dev, feat); return -EBUSY; @@ -2905,7 +2905,7 @@ bool iommu_dev_feature_enabled(struct device *dev, enum iommu_dev_features feat) { const struct iommu_ops *ops = dev->bus->iommu_ops; - if (ops && ops->dev_feat_enabled) + if (dev->iommu && ops && ops->dev_feat_enabled) return ops->dev_feat_enabled(dev, feat); return false; -- 2.17.1

4 4

[PATCH 0/4] perf vendor events arm64: Some tidy-up/refactoring
by John Garry 28 Jan '21

28 Jan '21

There is much event duplication in the common and uarch events for A76 and Ampere eMag support, so factor out into a common JSON. Since the wording for events may differ between CPU datasheet and the architecture reference manual, the current wording is kept. This is unless there are minor differences. In addition, event names are renamed to be same as architecture reference manual, to keep commonality. Also a minor fix is included for the Ampere eMag JSON. John Garry (4): perf vendor events arm64: Fix Ampere eMag event typo perf vendor events arm64: Add common and uarch event JSON perf vendor events arm64: Reference common and uarch events for Ampere eMag perf vendor events arm64: Reference common and uarch events for A76 .../arch/arm64/ampere/emag/branch.json | 8 +- .../arch/arm64/ampere/emag/bus.json | 5 +- .../arch/arm64/ampere/emag/cache.json | 58 +--- .../arch/arm64/ampere/emag/clock.json | 4 +- .../arch/arm64/ampere/emag/exception.json | 10 +- .../arch/arm64/ampere/emag/instruction.json | 34 +-- .../arch/arm64/ampere/emag/memory.json | 11 +- .../arch/arm64/arm/cortex-a76-n1/branch.json | 12 +- .../arch/arm64/arm/cortex-a76-n1/bus.json | 19 +- .../arch/arm64/arm/cortex-a76-n1/cache.json | 118 +++------ .../arm64/arm/cortex-a76-n1/exception.json | 10 +- .../arm64/arm/cortex-a76-n1/instruction.json | 45 +--- .../arch/arm64/arm/cortex-a76-n1/memory.json | 6 +- .../arch/arm64/arm/cortex-a76-n1/other.json | 4 +- .../arm64/arm/cortex-a76-n1/pipeline.json | 12 +- .../arm64/armv8-common-and-microarch.json | 248 ++++++++++++++++++ 16 files changed, 356 insertions(+), 248 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json -- 2.26.2

2 7

[PATCH] percpu: set the pointer to NULL after free the memory in free_percpu
by Tian Tao 28 Jan '21

28 Jan '21

set the pointer to NULL after free the memory in free_percpu, so there is no need to set the pointer to NULL in the driver after calling free_percpu again. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- mm/percpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mm/percpu.c b/mm/percpu.c index f53b89b..af944cc 100644 --- a/mm/percpu.c +++ b/mm/percpu.c @@ -2121,6 +2121,8 @@ void free_percpu(void __percpu *ptr) if (need_balance) pcpu_schedule_balance_work(); + + ptr = NULL; } EXPORT_SYMBOL_GPL(free_percpu); -- 2.7.4

2 1

[PATCH RESEND] dma-mapping: benchmark: fix kernel crash when dma_map_single fails
by Barry Song 28 Jan '21

28 Jan '21

if dma_map_single() fails, kernel will give the below oops since task_struct has been destroyed and we are running into the memory corruption due to use-after-free in kthread_stop(): [ 48.095310] Unable to handle kernel paging request at virtual address 000000c473548040 [ 48.095736] Mem abort info: [ 48.095864] ESR = 0x96000004 [ 48.096025] EC = 0x25: DABT (current EL), IL = 32 bits [ 48.096268] SET = 0, FnV = 0 [ 48.096401] EA = 0, S1PTW = 0 [ 48.096538] Data abort info: [ 48.096659] ISV = 0, ISS = 0x00000004 [ 48.096820] CM = 0, WnR = 0 [ 48.097079] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000104639000 [ 48.098099] [000000c473548040] pgd=0000000000000000, p4d=0000000000000000 [ 48.098832] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 48.099232] Modules linked in: [ 48.099387] CPU: 0 PID: 2 Comm: kthreadd Tainted: G W [ 48.099887] Hardware name: linux,dummy-virt (DT) [ 48.100078] pstate: 60000005 (nZCv daif -PAN -UAO -TCO BTYPE=--) [ 48.100516] pc : __kmalloc_node+0x214/0x368 [ 48.100944] lr : __kmalloc_node+0x1f4/0x368 [ 48.101458] sp : ffff800011f0bb80 [ 48.101843] x29: ffff800011f0bb80 x28: ffff0000c0098ec0 [ 48.102330] x27: 0000000000000000 x26: 00000000001d4600 [ 48.102648] x25: ffff0000c0098ec0 x24: ffff800011b6a000 [ 48.102988] x23: 00000000ffffffff x22: ffff0000c0098ec0 [ 48.103333] x21: ffff8000101d7a54 x20: 0000000000000dc0 [ 48.103657] x19: ffff0000c0001e00 x18: 0000000000000000 [ 48.104069] x17: 0000000000000000 x16: 0000000000000000 [ 48.105449] x15: 000001aa0304e7b9 x14: 00000000000003b1 [ 48.106401] x13: ffff8000122d5000 x12: ffff80001228d000 [ 48.107296] x11: ffff0000c0154340 x10: 0000000000000000 [ 48.107862] x9 : ffff80000fffffff x8 : ffff0000c473527f [ 48.108326] x7 : ffff800011e62f58 x6 : ffff0000c01c8ed8 [ 48.108778] x5 : ffff0000c0098ec0 x4 : 0000000000000000 [ 48.109223] x3 : 00000000001d4600 x2 : 0000000000000040 [ 48.109656] x1 : 0000000000000001 x0 : ff0000c473548000 [ 48.110104] Call trace: [ 48.110287] __kmalloc_node+0x214/0x368 [ 48.110493] __vmalloc_node_range+0xc4/0x298 [ 48.110805] copy_process+0x2c8/0x15c8 [ 48.111133] kernel_clone+0x5c/0x3c0 [ 48.111373] kernel_thread+0x64/0x90 [ 48.111604] kthreadd+0x158/0x368 [ 48.111810] ret_from_fork+0x10/0x30 [ 48.112336] Code: 17ffffe9 b9402a62 b94008a1 11000421 (f8626802) [ 48.112884] ---[ end trace d4890e21e75419d5 ]--- Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/dma/map_benchmark.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index b1496e744c68..1b1b8ff875cb 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -147,8 +147,10 @@ static int do_map_benchmark(struct map_benchmark_data *map) atomic64_set(&map->sum_sq_unmap, 0); atomic64_set(&map->loops, 0); - for (i = 0; i < threads; i++) + for (i = 0; i < threads; i++) { + get_task_struct(tsk[i]); wake_up_process(tsk[i]); + } msleep_interruptible(map->bparam.seconds * 1000); @@ -183,6 +185,8 @@ static int do_map_benchmark(struct map_benchmark_data *map) } out: + for (i = 0; i < threads; i++) + put_task_struct(tsk[i]); put_device(map->dev); kfree(tsk); return ret; -- 2.25.1

2 1

[PATCH RFC 0/4] Fix arm64 crash for accessing unmapped IO port regions (reboot)
by John Garry 27 Jan '21

27 Jan '21

This is a reboot of my original series to address the problem of drivers for legacy ISA devices accessing unmapped IO port regions on arm64 systems and causing the system to crash. There was another recent report of such an issue [0], and some old ones [1] and [2] for reference. The background is that many systems do not include PCI host controllers, or they do and controller probe may have failed. For these cases, no IO ports are mapped. However, loading drivers for legacy ISA devices can crash the system as there is nothing to stop them accessing those IO ports (which have not been io remap'ed). My original solution tried to keep the kernel alive in these situations by rejecting logical PIO access to PCI IO regions until PCI IO port regions have been mapped. This series goes one step further, by just reserving the complete legacy IO port range in 0x0--0xffff for arm64. The motivation for doing this is to make the request_region() calls for those drivers fail, like this: root@ubuntu:/home/john# insmod mk712.ko [ 3415.575800] mk712: unable to get IO region insmod: ERROR: could not insert module mk712.ko: No such device Otherwise, in theory, those drivers could initiate rogue accesses to mapped IO port regions for other devices and cause corruptions or side-effects. Indeed, those drivers should not be allowed to access IO ports at all in such a system. As a secondary defence, for broken drivers who do not call request_region(), IO port accesses in range 0--0xffff will be ignored, again preserving the system. I am sending as an RFC as I am not sure of any problem with reserving first 0x10000 of IO space like this. There is reserve= commandline argument, which does allow this already. For reference, here's how /proc/ioports looks on my arm64 system with this change: root@ubuntu:/home/john# more /proc/ioports 00010000-0001ffff : PCI Bus 0002:f8 00010000-00010fff : PCI Bus 0002:f9 00010000-00010007 : 0002:f9:00.0 00010000-00010007 : serial 00010008-0001000f : 0002:f9:00.1 00010008-0001000f : serial 00010010-00010017 : 0002:f9:00.2 00010018-0001001f : 0002:f9:00.2 00020000-0002ffff : PCI Bus 0004:88 00030000-0003ffff : PCI Bus 0005:78 00040000-0004ffff : PCI Bus 0006:c0 00050000-0005ffff : PCI Bus 0007:90 00060000-0006ffff : PCI Bus 000a:10 00070000-0007ffff : PCI Bus 000c:20 00080000-0008ffff : PCI Bus 000d:30 [0] https://lore.kernel.org/linux-input/20210112055129.7840-1-song.bao.hua@hisi… [1] https://lore.kernel.org/linux-pci/56F209A9.4040304@huawei.com [2] https://lore.kernel.org/linux-arm-kernel/e6995b4a-184a-d8d4-f4d4-9ce75d8f47… Difference since v4: https://lore.kernel.org/linux-pci/1560262374-67875-1-git-send-email-john.ga… - Reserve legacy ISA region John Garry (4): arm64: io: Introduce IO_SPACE_BASE asm-generic/io.h: Add IO_SPACE_BASE kernel/resource: Make ioport_resource.start configurable logic_pio: Warn on and discard accesses to addresses below IO_SPACE_BASE arch/arm64/include/asm/io.h | 1 + include/asm-generic/io.h | 4 ++++ include/linux/logic_pio.h | 5 +++++ kernel/resource.c | 2 +- lib/logic_pio.c | 20 ++++++++++++++------ 5 files changed, 25 insertions(+), 7 deletions(-) -- 2.26.2

3 8

[PATCH v2 0/2] EDAC/ghes: Add EDAC device for reporting the CPU cache error count
by Shiju Jose 26 Jan '21

26 Jan '21

CPU cache corrected errors are detected occasionally on few of our ARM64 hardware boards. Though it is rare, the probability of the CPU cache errors frequently occurring can't be avoided. The earlier failure detection by monitoring the cache corrected errors for the frequent occurrences and taking preventive action could prevent more serious hardware faults. On Intel architectures, cache corrected errors are reported and the affected cores are offlined in the architecture specific method. http://www.mcelog.org/cache.html However for the firmware-first error reporting, specifically on ARM64 architectures, there is no provision present for reporting the cache corrected error count to the user-space and taking preventive action such as offline the affected cores. For this purpose, it was suggested to create the CPU EDAC device for the CPU caches for reporting the cache error count for the firmware-first error reporting. User-space application could monitor the recorded corrected error count for the earlier hardware failure detection and could take preventive action, such as offline the corresponding CPU core/s. Changes: RFC V1 -> RFC V2: 1. Fixed feedback by Boris. 1.1. Added reason of this patch. 1.2. Changed CPU errors to CPU cache errors in the drivers/edac/Kconfig 1.3 Changed EDAC cache list to percpu variables. 1.4 Changed configuration depends on ARM64. 1.5. Moved discovery of cacheinfo to ghes_scan_system(). 2. Changes in the descriptions. Shiju Jose (2): EDAC/ghes: Add EDAC device for reporting the CPU cache errors ACPI / APEI: Add reporting ARM64 CPU cache corrected error count Documentation/ABI/testing/sysfs-devices-edac | 15 ++ drivers/acpi/apei/ghes.c | 76 +++++++- drivers/edac/Kconfig | 12 ++ drivers/edac/ghes_edac.c | 186 +++++++++++++++++++ include/acpi/ghes.h | 27 +++ include/linux/cper.h | 4 + 6 files changed, 316 insertions(+), 4 deletions(-) -- 2.17.1

1 2

[PATCH] percpu: set the pointer to NULL after free the memory in free_percpu
by Tian Tao 26 Jan '21

26 Jan '21

set the pointer to NULL after free the memory in free_percpu, so there is no need to set the pointer to NULL in the driver after calling free_percpu again. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- mm/percpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mm/percpu.c b/mm/percpu.c index f53b89b..af944cc 100644 --- a/mm/percpu.c +++ b/mm/percpu.c @@ -2121,6 +2121,8 @@ void free_percpu(void __percpu *ptr) if (need_balance) pcpu_schedule_balance_work(); + + ptr = NULL; } EXPORT_SYMBOL_GPL(free_percpu); -- 2.7.4

1 0

[GIT PULL] arm64: dts: hisilicon dts updates for v5.12
by Wei Xu 26 Jan '21

26 Jan '21

Hi ARM-SoC team, Please consider to pull the following changes. Thanks! Best Regards, Wei --- The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e: Linux 5.11-rc1 (2020-12-27 15:30:22 -0800) are available in the git repository at: git://github.com/hisilicon/linux-hisi.git tags/hisi-arm64-dt-for-5.12 for you to fetch changes up to 9091f9b9d2965983ee38dd68609002daeacf5199: arm64: dts: hisilicon: hi3670.dtsi: add I2C settings (2021-01-26 15:48:22 +0800) ---------------------------------------------------------------- ARM64: DT: Hisilicon ARM64 DT updates for 5.12 - Further cleanups of the hisilicon DTS to align with the dtschema - Add or update the I2C, pinctrl and reset nodes for Hikey970 ---------------------------------------------------------------- Mauro Carvalho Chehab (3): arm64: dts: hisilicon: hi3670.dtsi: add iomcu_rst arm64: dts: hisilicon: hikey970-pinctrl.dtsi: add missing pinctrl settings arm64: dts: hisilicon: hi3670.dtsi: add I2C settings Zhen Lei (7): arm64: dts: hisilicon: correct vendor prefix hisi to hisilicon arm64: dts: hisilicon: separate each group of data in the property "ranges" arm64: dts: hisilicon: place clock-names "bus" before "core" arm64: dts: hisilicon: normalize the node name of the module thermal arm64: dts: hisilicon: normalize the node name of the localbus arm64: dts: hisilicon: avoid irrelevant nodes being mistakenly identified as PHY nodes arm64: dts: hisilicon: delete unused property smmu-cb-memtype arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 +- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 79 ++- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 +- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 8 +- .../arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi | 632 ++++++++++++++++++++- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 6 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 9 +- 8 files changed, 717 insertions(+), 37 deletions(-)

1 0

Re: [PATCH v2 plinth/topic-sas-5.10 3/4] {topost} scsi: hisi_sas: enable DFX by default
by John Garry 26 Jan '21

26 Jan '21

On 16/12/2020 10:38, Luo Jiaxing wrote: > This patch add a config option "CONFIG_SCSI_HISI_DEBUGFS_DEFAULT_ENABLE" I just noticed that this should really be CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE so, I will change it to be like that

1 0

[RFC PATCH] sched/fair: first try to fix the scheduling impact of NUMA diameter > 2
by Barry Song 26 Jan '21

26 Jan '21

This patch is a follow-up of the 3-hops issue reported by Valentin Schneider: [1] https://lore.kernel.org/lkml/jhjtux5edo2.mognet@arm.com/ [2] https://lore.kernel.org/lkml/20201110184300.15673-1-valentin.schneider@arm.… Here is a brief summary of the background: For a NUMA system with 3-hops, sched_group for NUMA 2-hops could be not a subset of sched_domain. For example, for a system with the below topology(two cpus in each NUMA node): node 0 1 2 3 0: 10 12 20 22 1: 12 10 22 24 2: 20 22 10 12 3: 22 24 12 10 For CPU0, domain-2 will span 0-5, but its group will span 0-3, 4-7. 4-7 isn't a subset of 0-5. CPU0 attaching sched-domain(s): domain-0: span=0-1 level=MC groups: 0:{ span=0 cap=989 }, 1:{ span=1 cap=1016 } domain-1: span=0-3 level=NUMA groups: 0:{ span=0-1 cap=2005 }, 2:{ span=2-3 cap=2028 } domain-2: span=0-5 level=NUMA groups: 0:{ span=0-3 cap=4033 }, 4:{ span=4-7 cap=3909 } ERROR: groups don't span domain->span domain-3: span=0-7 level=NUMA groups: 0:{ span=0-5 mask=0-1 cap=6062 }, 6:{ span=4-7 mask=6-7 cap=3928 } All other cpus also have the same issue: sched_group could be not a subset of sched_domain. Here I am trying to figure out the scheduling impact of this issue from two aspects: 1. find busiest cpu in load_balance 2. find idlest cpu in fork/exec/wake balance For case 1, load_balance() seems to be handling this issue correctly as it only fills cpus in sched_domain to the cpus of lb_env. Also, find_busiest_group() and find_busiest_queue() will result in scanning cpus within env.cpus only: static int load_balance(int this_cpu, struct rq *this_rq, struct sched_domain *sd, enum cpu_idle_type idle, int *continue_balancing) {` ... struct lb_env env = { ... .cpus = cpus, .fbq_type = all, .tasks = LIST_HEAD_INIT(env.tasks), }; /* added by barry: only cpus in sched_domain are put in lb_env */ cpumask_and(cpus, sched_domain_span(sd), cpu_active_mask); ... /* * added by barry: the below functions are only scanning cpus * in env.cpus */ group = find_busiest_group(&env); ... busiest = find_busiest_queue(&env, group); ... } But one thing which looks wrong is that update_sg_lb_stats() is only counting tasks in sched_domain, but sgs->group_capacity and sgs->group_weight are counting all cpus in the sched_group. Then finally, update_sg_lb_stats() uses the load of cpus which are in the sched_domain to calculate group_type and avg_load which can be seriously underestimated. This is explained in detail as the comments added by me in the code: static inline void update_sg_lb_stats() { int i, nr_running, local_group; /* added by barry: here it only counts cpu in the sched_domain */ for_each_cpu_and(i, sched_group_span(group), env->cpus) { ... sgs->group_load += cpu_load(rq); sgs->group_util += cpu_util(i); sgs->group_runnable += cpu_runnable(rq); sgs->sum_h_nr_running += rq->cfs.h_nr_running; nr_running = rq->nr_running; sgs->sum_nr_running += nr_running; ... } ... /* added by barry: here it count all cpus which might not be in the domain */ sgs->group_capacity = group->sgc->capacity; sgs->group_weight = group->group_weight; /* added by barry: finally the group_type and avg_load could be wrong */ sgs->group_type = group_classify(env->sd->imbalance_pct, group, sgs); if (sgs->group_type == group_overloaded) sgs->avg_load = (sgs->group_load * SCHED_CAPACITY_SCALE) / sgs->group_capacity; ... } For example, if we have 2 cpus in sched_domain and 4 cpus in sched_group, the code is using the load of 2 cpus to calculate the group_type and avg_load of 4 cpus, the sched_group is likely to get much lower load than the real case. This patch fixed it by only counting cpus within sched_domain for group_capacity and group_weight. For case 2, find_idlest_group() and find_idlest_group_cpu() don't use sched_domain for scanning at all. They are scanning all cpus in the sched_group though sched_group isn't a subset of sched_domain. So they can result in picking an idle cpu outside the sched_domain but inside the sched_group. This patch moved to only scan cpus within the sched_domain, which would be similar with load_balance(). For this moment, this is pretty much PoC code to get feedback. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/sched/fair.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 04a3ce20da67..f183dba4961e 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -5901,7 +5901,7 @@ find_idlest_group(struct sched_domain *sd, struct task_struct *p, int this_cpu); * find_idlest_group_cpu - find the idlest CPU among the CPUs in the group. */ static int -find_idlest_group_cpu(struct sched_group *group, struct task_struct *p, int this_cpu) +find_idlest_group_cpu(struct sched_domain *sd, struct sched_group *group, struct task_struct *p, int this_cpu) { unsigned long load, min_load = ULONG_MAX; unsigned int min_exit_latency = UINT_MAX; @@ -5916,6 +5916,10 @@ find_idlest_group_cpu(struct sched_group *group, struct task_struct *p, int this /* Traverse only the allowed CPUs */ for_each_cpu_and(i, sched_group_span(group), p->cpus_ptr) { + /* when sched_group isn't a subset of sched_domain */ + if (!cpumask_test_cpu(i, sched_domain_span(sd))) + continue; + if (sched_idle_cpu(i)) return i; @@ -5984,7 +5988,7 @@ static inline int find_idlest_cpu(struct sched_domain *sd, struct task_struct *p continue; } - new_cpu = find_idlest_group_cpu(group, p, cpu); + new_cpu = find_idlest_group_cpu(sd, group, p, cpu); if (new_cpu == cpu) { /* Now try balancing at a lower domain level of 'cpu': */ sd = sd->child; @@ -8416,6 +8420,8 @@ static inline void update_sg_lb_stats(struct lb_env *env, if ((env->flags & LBF_NOHZ_STATS) && update_nohz_stats(rq, false)) env->flags |= LBF_NOHZ_AGAIN; + sgs->group_capacity += capacity_of(i); + sgs->group_weight++; sgs->group_load += cpu_load(rq); sgs->group_util += cpu_util(i); sgs->group_runnable += cpu_runnable(rq); @@ -8462,10 +8468,6 @@ static inline void update_sg_lb_stats(struct lb_env *env, sgs->group_asym_packing = 1; } - sgs->group_capacity = group->sgc->capacity; - - sgs->group_weight = group->group_weight; - sgs->group_type = group_classify(env->sd->imbalance_pct, group, sgs); /* Computing avg_load makes sense only when group is overloaded */ @@ -8688,10 +8690,12 @@ static inline void update_sg_wakeup_stats(struct sched_domain *sd, memset(sgs, 0, sizeof(*sgs)); - for_each_cpu(i, sched_group_span(group)) { + for_each_cpu_and(i, sched_group_span(group), sched_domain_span(sd)) { struct rq *rq = cpu_rq(i); unsigned int local; + sgs->group_capacity += capacity_of(i); + sgs->group_weight++; sgs->group_load += cpu_load_without(rq, p); sgs->group_util += cpu_util_without(i, p); sgs->group_runnable += cpu_runnable_without(rq, p); @@ -8715,10 +8719,6 @@ static inline void update_sg_wakeup_stats(struct sched_domain *sd, sgs->group_misfit_task_load = 1; } - sgs->group_capacity = group->sgc->capacity; - - sgs->group_weight = group->group_weight; - sgs->group_type = group_classify(sd->imbalance_pct, group, sgs); /* -- 2.25.1

4 7

[PATCH v2 8/8] rasdaemon: Modify confiure.ac for Hisilicon Kunpeng errors
by Shiju Jose 26 Jan '21

26 Jan '21

Modify HIP07 SAS HW errors : $USE_HISI_NS_DECODE to HISI Kunpeng errors : $USE_HISI_NS_DECODE. Signed-off-by: Shiju Jose <shiju.jose(a)huawei.com> --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 9893bb4..3a8b0c7 100644 --- a/configure.ac +++ b/configure.ac @@ -191,7 +191,7 @@ compile time options summary EXTLOG : $USE_EXTLOG CPER non-standard : $USE_NON_STANDARD ABRT report : $USE_ABRT_REPORT - HIP07 SAS HW errors : $USE_HISI_NS_DECODE + HISI Kunpeng errors : $USE_HISI_NS_DECODE ARM events : $USE_ARM DEVLINK : $USE_DEVLINK Disk I/O errors : $USE_DISKERROR -- 2.17.1

1 0

[PATCH v2 7/8] rasdaemon: ras-mc-ctl: Add support for HiSilicon Kunpeng9xx common errors
by Shiju Jose 26 Jan '21

26 Jan '21

Add support for the HiSilicon Kunpeng9xx platforms common errors. Signed-off-by: Shiju Jose <shiju.jose(a)huawei.com> Reviewed-by: Xiaofei Tan <tanxiaofei(a)huawei.com> --- util/ras-mc-ctl.in | 44 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index 8befc5d..37a5042 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1519,6 +1519,7 @@ sub errors # Definitions of the vendor platform IDs. use constant { HISILICON_KUNPENG_920 => "Kunpeng920", + HISILICON_KUNPENG_9XX => "Kunpeng9xx", }; sub vendor_errors_summary @@ -1526,7 +1527,7 @@ sub vendor_errors_summary require DBI; my ($num_args, $platform_id); my ($query, $query_handle, $count, $out); - my ($module_id, $sub_module_id, $err_severity, $err_sev); + my ($module_id, $sub_module_id, $err_severity, $err_sev, $err_info); $num_args = $#ARGV + 1; $platform_id = 0; @@ -1601,6 +1602,24 @@ sub vendor_errors_summary $query_handle->finish; } + # HiSilicon Kunpeng9xx common errors + if ($platform_id eq HISILICON_KUNPENG_9XX) { + $query = "select err_info, count(*) from hisi_common_section"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($err_info, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= "\terrors: $count\n"; + } + if ($out ne "") { + print "HiSilicon Kunpeng9xx common error events summary:\n$out\n"; + } else { + print "No HiSilicon Kunpeng9xx common errors.\n\n"; + } + $query_handle->finish; + } + undef($dbh); } @@ -1610,7 +1629,7 @@ sub vendor_errors my ($num_args, $platform_id); my ($query, $query_handle, $id, $timestamp, $out); my ($version, $soc_id, $socket_id, $nimbus_id, $core_id, $port_id); - my ($module_id, $sub_module_id, $err_severity, $err_type, $regs); + my ($module_id, $sub_module_id, $err_severity, $err_type, $err_info, $regs); $num_args = $#ARGV + 1; $platform_id = 0; @@ -1696,6 +1715,26 @@ sub vendor_errors $query_handle->finish; } + # HiSilicon Kunpeng9xx common errors + if ($platform_id eq HISILICON_KUNPENG_9XX) { + $query = "select id, timestamp, err_info, regs_dump from hisi_common_section order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $err_info, $regs)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id. $timestamp "; + $out .= "Error Info:$err_info \n" if ($err_info); + $out .= "Error Registers: $regs\n\n" if ($regs); + } + if ($out ne "") { + print "HiSilicon Kunpeng9xx common error events:\n$out\n"; + } else { + print "No HiSilicon Kunpeng9xx common errors.\n"; + } + $query_handle->finish; + } + undef($dbh); } @@ -1703,6 +1742,7 @@ sub vendor_platforms { print "\nSupported platforms for the vendor-specific errors:\n"; print "\tHiSilicon Kunpeng920, platform-id=\"", HISILICON_KUNPENG_920, "\"\n"; + print "\tHiSilicon Kunpeng9xx, platform-id=\"", HISILICON_KUNPENG_9XX, "\"\n"; print "\n"; } -- 2.17.1

1 0

[PATCH v2 6/8] rasdaemon: ras-mc-ctl: Add support for HiSilicon Kunpeng920 errors
by Shiju Jose 26 Jan '21

26 Jan '21

Add support for the HiSilicon Kunpeng920 errors. Supported error formats: OEM type 1, OEM typ2 and PCIe controller error formats. Signed-off-by: Shiju Jose <shiju.jose(a)huawei.com> Reviewed-by: Xiaofei Tan <tanxiaofei(a)huawei.com> --- util/ras-mc-ctl.in | 149 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index 6820823..8befc5d 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1516,10 +1516,17 @@ sub errors undef($dbh); } +# Definitions of the vendor platform IDs. +use constant { + HISILICON_KUNPENG_920 => "Kunpeng920", +}; + sub vendor_errors_summary { require DBI; my ($num_args, $platform_id); + my ($query, $query_handle, $count, $out); + my ($module_id, $sub_module_id, $err_severity, $err_sev); $num_args = $#ARGV + 1; $platform_id = 0; @@ -1531,6 +1538,69 @@ sub vendor_errors_summary my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); + # HiSilicon Kunpeng920 errors + if ($platform_id eq HISILICON_KUNPENG_920) { + $query = "select err_severity, module_id, count(*) from hip08_oem_type1_event_v2 group by err_severity, module_id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($err_severity, $module_id, $count)); + $out = ""; + $err_sev = ""; + while($query_handle->fetch()) { + if ($err_severity ne $err_sev) { + $out .= "$err_severity errors:\n"; + $err_sev = $err_severity; + } + $out .= "\t$module_id: $count\n"; + } + if ($out ne "") { + print "HiSilicon Kunpeng920 OEM type1 error events summary:\n$out\n"; + } else { + print "No HiSilicon Kunpeng920 OEM type1 errors.\n\n"; + } + $query_handle->finish; + + $query = "select err_severity, module_id, count(*) from hip08_oem_type2_event_v2 group by err_severity, module_id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($err_severity, $module_id, $count)); + $out = ""; + $err_sev = ""; + while($query_handle->fetch()) { + if ($err_severity ne $err_sev) { + $out .= "$err_severity errors:\n"; + $err_sev = $err_severity; + } + $out .= "\t$module_id: $count\n"; + } + if ($out ne "") { + print "HiSilicon Kunpeng920 OEM type2 error events summary:\n$out\n"; + } else { + print "No HiSilicon Kunpeng920 OEM type2 errors.\n\n"; + } + $query_handle->finish; + + $query = "select err_severity, sub_module_id, count(*) from hip08_pcie_local_event_v2 group by err_severity, sub_module_id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($err_severity, $sub_module_id, $count)); + $out = ""; + $err_sev = ""; + while($query_handle->fetch()) { + if ($err_severity ne $err_sev) { + $out .= "$err_severity errors:\n"; + $err_sev = $err_severity; + } + $out .= "\t$sub_module_id: $count\n"; + } + if ($out ne "") { + print "HiSilicon Kunpeng920 PCIe controller error events summary:\n$out\n"; + } else { + print "No HiSilicon Kunpeng920 PCIe controller errors.\n\n"; + } + $query_handle->finish; + } + undef($dbh); } @@ -1538,6 +1608,9 @@ sub vendor_errors { require DBI; my ($num_args, $platform_id); + my ($query, $query_handle, $id, $timestamp, $out); + my ($version, $soc_id, $socket_id, $nimbus_id, $core_id, $port_id); + my ($module_id, $sub_module_id, $err_severity, $err_type, $regs); $num_args = $#ARGV + 1; $platform_id = 0; @@ -1549,12 +1622,88 @@ sub vendor_errors my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); + # HiSilicon Kunpeng920 errors + if ($platform_id eq HISILICON_KUNPENG_920) { + $query = "select id, timestamp, version, soc_id, socket_id, nimbus_id, module_id, sub_module_id, err_severity, regs_dump from hip08_oem_type1_event_v2 order by id, module_id, err_severity"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $version, $soc_id, $socket_id, $nimbus_id, $module_id, $sub_module_id, $err_severity, $regs)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id. $timestamp Error Info: "; + $out .= "version=$version, "; + $out .= "soc_id=$soc_id, " if ($soc_id); + $out .= "socket_id=$socket_id, " if ($socket_id); + $out .= "nimbus_id=$nimbus_id, " if ($nimbus_id); + $out .= "module_id=$module_id, " if ($module_id); + $out .= "sub_module_id=$sub_module_id, " if ($sub_module_id); + $out .= "err_severity=$err_severity, \n" if ($err_severity); + $out .= "Error Registers: $regs\n\n" if ($regs); + } + if ($out ne "") { + print "HiSilicon Kunpeng920 OEM type1 error events:\n$out\n"; + } else { + print "No HiSilicon Kunpeng920 OEM type1 errors.\n"; + } + $query_handle->finish; + + $query = "select id, timestamp, version, soc_id, socket_id, nimbus_id, module_id, sub_module_id, err_severity, regs_dump from hip08_oem_type2_event_v2 order by id, module_id, err_severity"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $version, $soc_id, $socket_id, $nimbus_id, $module_id, $sub_module_id, $err_severity, $regs)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id. $timestamp Error Info: "; + $out .= "version=$version, "; + $out .= "soc_id=$soc_id, " if ($soc_id); + $out .= "socket_id=$socket_id, " if ($socket_id); + $out .= "nimbus_id=$nimbus_id, " if ($nimbus_id); + $out .= "module_id=$module_id, " if ($module_id); + $out .= "sub_module_id=$sub_module_id, " if ($sub_module_id); + $out .= "err_severity=$err_severity, \n" if ($err_severity); + $out .= "Error Registers: $regs\n\n" if ($regs); + } + if ($out ne "") { + print "HiSilicon Kunpeng920 OEM type2 error events:\n$out\n"; + } else { + print "No HiSilicon Kunpeng920 OEM type2 errors.\n"; + } + $query_handle->finish; + + $query = "select id, timestamp, version, soc_id, socket_id, nimbus_id, sub_module_id, core_id, port_id, err_severity, err_type, regs_dump from hip08_pcie_local_event_v2 order by id, sub_module_id, err_severity"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $version, $soc_id, $socket_id, $nimbus_id, $sub_module_id, $core_id, $port_id, $err_severity, $err_type, $regs)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id. $timestamp Error Info: "; + $out .= "version=$version, "; + $out .= "soc_id=$soc_id, " if ($soc_id); + $out .= "socket_id=$socket_id, " if ($socket_id); + $out .= "nimbus_id=$nimbus_id, " if ($nimbus_id); + $out .= "sub_module_id=$sub_module_id, " if ($sub_module_id); + $out .= "core_id=$core_id, " if ($core_id); + $out .= "port_id=$port_id, " if ($port_id); + $out .= "err_severity=$err_severity, " if ($err_severity); + $out .= "err_type=$err_type, \n" if ($err_type); + $out .= "Error Registers: $regs\n\n" if ($regs); + } + if ($out ne "") { + print "HiSilicon Kunpeng920 PCIe controller error events:\n$out\n"; + } else { + print "No HiSilicon Kunpeng920 PCIe controller errors.\n"; + } + $query_handle->finish; + } + undef($dbh); } sub vendor_platforms { print "\nSupported platforms for the vendor-specific errors:\n"; + print "\tHiSilicon Kunpeng920, platform-id=\"", HISILICON_KUNPENG_920, "\"\n"; + print "\n"; } sub log_msg { print STDERR "$prog: ", @_ unless $conf{opt}{quiet}; } -- 2.17.1

1 0

[PATCH v2 5/8] rasdaemon: ras-mc-ctl: Add support for the vendor-specific errors
by Shiju Jose 26 Jan '21

26 Jan '21

Add commands to support logging the vendor-specific error info in the ras-mc-ctl. Signed-off-by: Shiju Jose <shiju.jose(a)huawei.com> Reviewed-by: Xiaofei Tan <tanxiaofei(a)huawei.com> --- util/ras-mc-ctl.in | 64 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index 97b1fa4..6820823 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -87,6 +87,9 @@ Usage: $prog [OPTIONS...] --summary Presents a summary of the logged errors. --errors Shows the errors stored at the error database. --error-count Shows the corrected and uncorrected error counts using sysfs. + --vendor-errors-summary <platform-id> Presents a summary of the vendor-specific logged errors. + --vendor-errors <platform-id> Shows the vendor-specific errors stored in the error database. + --vendor-platforms Shows the supported platforms with platform-ids for the vendor-specific errors. --help This help message. EOF @@ -134,6 +137,18 @@ if ($conf{opt}{errors}) { errors (); } +if ($conf{opt}{vendor_errors_summary}) { + vendor_errors_summary (); +} + +if ($conf{opt}{vendor_errors}) { + vendor_errors (); +} + +if ($conf{opt}{vendor_platforms}) { + vendor_platforms (); +} + exit (0); sub parse_cmdline @@ -149,6 +164,9 @@ sub parse_cmdline $conf{opt}{summary} = 0; $conf{opt}{errors} = 0; $conf{opt}{error_count} = 0; + $conf{opt}{vendor_errors_summary} = 0; + $conf{opt}{vendor_errors} = 0; + $conf{opt}{vendor_platforms} = 0; my $rref = \$conf{opt}{report}; my $mref = \$conf{opt}{mainboard}; @@ -166,7 +184,10 @@ sub parse_cmdline "layout" => \$conf{opt}{display_memory_layout}, "summary" => \$conf{opt}{summary}, "errors" => \$conf{opt}{errors}, - "error-count" => \$conf{opt}{error_count} + "error-count" => \$conf{opt}{error_count}, + "vendor-errors-summary" => \$conf{opt}{vendor_errors_summary}, + "vendor-errors" => \$conf{opt}{vendor_errors}, + "vendor-platforms" => \$conf{opt}{vendor_platforms}, ); usage(1) if !$rc; @@ -1495,6 +1516,47 @@ sub errors undef($dbh); } +sub vendor_errors_summary +{ + require DBI; + my ($num_args, $platform_id); + + $num_args = $#ARGV + 1; + $platform_id = 0; + if ($num_args ne 0) { + $platform_id = $ARGV[0]; + } else { + return; + } + + my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); + + undef($dbh); +} + +sub vendor_errors +{ + require DBI; + my ($num_args, $platform_id); + + $num_args = $#ARGV + 1; + $platform_id = 0; + if ($num_args ne 0) { + $platform_id = $ARGV[0]; + } else { + return; + } + + my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); + + undef($dbh); +} + +sub vendor_platforms +{ + print "\nSupported platforms for the vendor-specific errors:\n"; +} + sub log_msg { print STDERR "$prog: ", @_ unless $conf{opt}{quiet}; } sub log_error { log_msg ("Error: @_"); } -- 2.17.1

1 0

[PATCH v2 4/8] rasdaemon: ras-mc-ctl: Fix for exception when an event is not enabled
by Shiju Jose 26 Jan '21

26 Jan '21

When an event is not enabled in the build and thus the event's table is not present in the SQLite DB, then the DBI would detect exception and ras-mc-ctl exit without read and log remaining event's information. Following is the error log when the devlink_event is not enabled, "DBD::SQLite::db prepare failed: no such table: devlink_event at ./ras-mc-ctl line 1198. Can't call method "execute" on an undefined value at ./ras-mc-ctl line 1199" Add an extra check, whether an event is enabled in the build, before try reading the tables. Reported-by: Xiaofei Tan <tanxiaofei(a)huawei.com> Suggested-by: Mauro Carvalho Chehab <mchehab+huawei(a)kernel.org> Signed-off-by: Shiju Jose <shiju.jose(a)huawei.com> --- configure.ac | 7 + util/ras-mc-ctl.in | 506 ++++++++++++++++++++++++--------------------- 2 files changed, 278 insertions(+), 235 deletions(-) diff --git a/configure.ac b/configure.ac index a6251d4..9893bb4 100644 --- a/configure.ac +++ b/configure.ac @@ -42,6 +42,7 @@ AC_SUBST([SQLITE3_LIBS]) AC_ARG_ENABLE([aer], AS_HELP_STRING([--enable-aer], [enable PCIe AER events (currently experimental)])) +AC_SUBST([enable_aer]) AS_IF([test "x$enable_aer" = "xyes" || test "x$enable_all" == "xyes"], [ AC_DEFINE(HAVE_AER,1,"have PCIe AER events collect") @@ -63,6 +64,7 @@ AM_COND_IF([WITH_NON_STANDARD], [USE_NON_STANDARD="yes"], [USE_NON_STANDARD="no" AC_ARG_ENABLE([arm], AS_HELP_STRING([--enable-arm], [enable ARM events (currently experimental)])) +AC_SUBST([enable_arm]) AS_IF([test "x$enable_arm" = "xyes" || test "x$enable_all" == "xyes"], [ AC_DEFINE(HAVE_ARM,1,"have ARM events collect") @@ -73,6 +75,7 @@ AM_COND_IF([WITH_ARM], [USE_ARM="yes"], [USE_ARM="no"]) AC_ARG_ENABLE([mce], AS_HELP_STRING([--enable-mce], [enable MCE events (currently experimental)])) +AC_SUBST([enable_mce]) AS_IF([test "x$enable_mce" = "xyes" || test "x$enable_all" == "xyes"], [ AC_DEFINE(HAVE_MCE,1,"have PCIe MCE events collect") @@ -83,6 +86,7 @@ AM_COND_IF([WITH_MCE], [USE_MCE="yes"], [USE_MCE="no"]) AC_ARG_ENABLE([extlog], AS_HELP_STRING([--enable-extlog], [enable EXTLOG events (currently experimental)])) +AC_SUBST([enable_extlog]) AS_IF([test "x$enable_extlog" = "xyes" || test "x$enable_all" == "xyes"], [ AC_DEFINE(HAVE_EXTLOG,1,"have EXTLOG events collect") @@ -93,6 +97,7 @@ AM_COND_IF([WITH_EXTLOG], [USE_EXTLOG="yes"], [USE_EXTLOG="no"]) AC_ARG_ENABLE([devlink], AS_HELP_STRING([--enable-devlink], [enable devlink health events (currently experimental)])) +AC_SUBST([enable_devlink]) AS_IF([test "x$enable_devlink" = "xyes" || test "x$enable_all" == "xyes"], [ AC_DEFINE(HAVE_DEVLINK,1,"have devlink health events collect") @@ -103,6 +108,7 @@ AM_COND_IF([WITH_DEVLINK], [USE_DEVLINK="yes"], [USE_DEVLINK="no"]) AC_ARG_ENABLE([diskerror], AS_HELP_STRING([--enable-diskerror], [enable disk I/O error events (currently experimental)])) +AC_SUBST([enable_diskerror]) AS_IF([test "x$enable_diskerror" = "xyes" || test "x$enable_all" == "xyes"], [ AC_DEFINE(HAVE_DISKERROR,1,"have disk I/O errors collect") @@ -113,6 +119,7 @@ AM_COND_IF([WITH_DISKERROR], [USE_DISKERROR="yes"], [USE_DISKERROR="no"]) AC_ARG_ENABLE([memory_failure], AS_HELP_STRING([--enable-memory-failure], [enable memory failure events (currently experimental)])) +AC_SUBST([enable_memory_failure]) AS_IF([test "x$enable_memory_failure" = "xyes" || test "x$enable_all" == "xyes"], [ AC_DEFINE(HAVE_MEMORY_FAILURE,1,"have memory failure events collect") diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index eebcc4e..97b1fa4 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -65,6 +65,14 @@ $conf{mbconfig} = "$sysconfdir/ras/mainboard"; my $status = 0; +my $enable_aer = "@enable_aer@"; +my $enable_arm = "@enable_arm@"; +my $enable_mce = "@enable_mce@"; +my $enable_extlog = "@enable_extlog@"; +my $enable_devlink = "@enable_devlink@"; +my $enable_diskerror = "@enable_diskerror@"; +my $enable_mem_failure = "@enable_memory_failure@"; + my $usage = <<EOF; Usage: $prog [OPTIONS...] --quiet Quiet operation. @@ -1144,118 +1152,132 @@ sub summary $query_handle->finish; # PCIe AER aer_event errors - $query = "select err_type, err_msg, count(*) from aer_event group by err_type, err_msg"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($err_type, $msg, $count)); - $out = ""; - while($query_handle->fetch()) { - $out .= "\t$count $err_type errors: $msg\n"; - } - if ($out ne "") { - print "PCIe AER events summary:\n$out\n"; - } else { - print "No PCIe AER errors.\n\n"; + if ($enable_aer eq "yes") { + $query = "select err_type, err_msg, count(*) from aer_event group by err_type, err_msg"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($err_type, $msg, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= "\t$count $err_type errors: $msg\n"; + } + if ($out ne "") { + print "PCIe AER events summary:\n$out\n"; + } else { + print "No PCIe AER errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # ARM processor arm_event errors - $query = "select mpidr, count(*) from arm_event group by mpidr"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($mpidr, $count)); - $out = ""; - while($query_handle->fetch()) { - $out .= sprintf "\tCPU(mpidr=0x%x) has %d errors\n", $mpidr, $count; - } - if ($out ne "") { - print "ARM processor events summary:\n$out\n"; - } else { - print "No ARM processor errors.\n\n"; + if ($enable_arm eq "yes") { + $query = "select mpidr, count(*) from arm_event group by mpidr"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($mpidr, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= sprintf "\tCPU(mpidr=0x%x) has %d errors\n", $mpidr, $count; + } + if ($out ne "") { + print "ARM processor events summary:\n$out\n"; + } else { + print "No ARM processor errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # extlog errors - $query = "select etype, severity, count(*) from extlog_event group by etype, severity"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($etype, $severity, $count)); - $out = ""; - while($query_handle->fetch()) { - $etype_string = get_extlog_type($etype); - $severity_string = get_extlog_severity($severity); - $out .= "\t$count $etype_string $severity_string errors\n"; - } - if ($out ne "") { - print "Extlog records summary:\n$out"; - } else { - print "No Extlog errors.\n\n"; + if ($enable_extlog eq "yes") { + $query = "select etype, severity, count(*) from extlog_event group by etype, severity"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($etype, $severity, $count)); + $out = ""; + while($query_handle->fetch()) { + $etype_string = get_extlog_type($etype); + $severity_string = get_extlog_severity($severity); + $out .= "\t$count $etype_string $severity_string errors\n"; + } + if ($out ne "") { + print "Extlog records summary:\n$out"; + } else { + print "No Extlog errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # devlink errors - $query = "select dev_name, count(*) from devlink_event group by dev_name"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($dev_name, $count)); - $out = ""; - while($query_handle->fetch()) { - $out .= "\t$dev_name has $count errors\n"; - } - if ($out ne "") { - print "Devlink records summary:\n$out"; - } else { - print "No devlink errors.\n"; + if ($enable_devlink eq "yes") { + $query = "select dev_name, count(*) from devlink_event group by dev_name"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($dev_name, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= "\t$dev_name has $count errors\n"; + } + if ($out ne "") { + print "Devlink records summary:\n$out"; + } else { + print "No devlink errors.\n"; + } + $query_handle->finish; } - $query_handle->finish; # Disk errors - $query = "select dev, count(*) from disk_errors group by dev"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($dev, $count)); - $out = ""; - while($query_handle->fetch()) { - $out .= "\t$dev has $count errors\n"; - } - if ($out ne "") { - print "Disk errors summary:\n$out"; - } else { - print "No disk errors.\n"; + if ($enable_diskerror eq "yes") { + $query = "select dev, count(*) from disk_errors group by dev"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($dev, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= "\t$dev has $count errors\n"; + } + if ($out ne "") { + print "Disk errors summary:\n$out"; + } else { + print "No disk errors.\n"; + } + $query_handle->finish; } - $query_handle->finish; # Memory failure errors - $query = "select action_result, count(*) from memory_failure_event group by action_result"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($action_result, $count)); - $out = ""; - while($query_handle->fetch()) { - $out .= "\t$action_result errors: $count\n"; - } - if ($out ne "") { - print "Memory failure events summary:\n$out\n"; - } else { - print "No Memory failure errors.\n\n"; + if ($enable_mem_failure eq "yes") { + $query = "select action_result, count(*) from memory_failure_event group by action_result"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($action_result, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= "\t$action_result errors: $count\n"; + } + if ($out ne "") { + print "Memory failure events summary:\n$out\n"; + } else { + print "No Memory failure errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # MCE mce_record errors - $query = "select error_msg, count(*) from mce_record group by error_msg"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($msg, $count)); - $out = ""; - while($query_handle->fetch()) { - $out .= "\t$count $msg errors\n"; - } - if ($out ne "") { - print "MCE records summary:\n$out"; - } else { - print "No MCE errors.\n"; + if ($enable_mce eq "yes") { + $query = "select error_msg, count(*) from mce_record group by error_msg"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($msg, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= "\t$count $msg errors\n"; + } + if ($out ne "") { + print "MCE records summary:\n$out"; + } else { + print "No MCE errors.\n"; + } + $query_handle->finish; } - $query_handle->finish; undef($dbh); } @@ -1294,167 +1316,181 @@ sub errors $query_handle->finish; # PCIe AER aer_event errors - $query = "select id, timestamp, dev_name, err_type, err_msg from aer_event order by id"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($id, $time, $devname, $type, $msg)); - $out = ""; - while($query_handle->fetch()) { - $out .= "$id $time $devname $type error: $msg\n"; - } - if ($out ne "") { - print "PCIe AER events:\n$out\n"; - } else { - print "No PCIe AER errors.\n\n"; + if ($enable_aer eq "yes") { + $query = "select id, timestamp, dev_name, err_type, err_msg from aer_event order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $time, $devname, $type, $msg)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $time $devname $type error: $msg\n"; + } + if ($out ne "") { + print "PCIe AER events:\n$out\n"; + } else { + print "No PCIe AER errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # ARM processor arm_event errors - $query = "select id, timestamp, error_count, affinity, mpidr, running_state, psci_state from arm_event order by id"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $error_count, $affinity, $mpidr, $r_state, $psci_state)); - $out = ""; - while($query_handle->fetch()) { - $out .= "$id $timestamp error: "; - $out .= "error_count=$error_count, " if ($error_count); - $out .= "affinity_level=$affinity, "; - $out .= sprintf "mpidr=0x%x, ", $mpidr; - $out .= sprintf "running_state=0x%x, ", $r_state; - $out .= sprintf "psci_state=0x%x", $psci_state; - $out .= "\n"; - } - if ($out ne "") { - print "ARM processor events:\n$out\n"; - } else { - print "No ARM processor errors.\n\n"; + if ($enable_arm eq "yes") { + $query = "select id, timestamp, error_count, affinity, mpidr, running_state, psci_state from arm_event order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $error_count, $affinity, $mpidr, $r_state, $psci_state)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $timestamp error: "; + $out .= "error_count=$error_count, " if ($error_count); + $out .= "affinity_level=$affinity, "; + $out .= sprintf "mpidr=0x%x, ", $mpidr; + $out .= sprintf "running_state=0x%x, ", $r_state; + $out .= sprintf "psci_state=0x%x", $psci_state; + $out .= "\n"; + } + if ($out ne "") { + print "ARM processor events:\n$out\n"; + } else { + print "No ARM processor errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # Extlog errors - $query = "select id, timestamp, etype, severity, address, fru_id, fru_text, cper_data from extlog_event order by id"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $etype, $severity, $addr, $fru_id, $fru_text, $cper_data)); - $out = ""; - while($query_handle->fetch()) { - $etype_string = get_extlog_type($etype); - $severity_string = get_extlog_severity($severity); - $out .= "$id $timestamp error: "; - $out .= "type=$etype_string, "; - $out .= "severity=$severity_string, "; - $out .= sprintf "address=0x%08x, ", $addr; - $out .= sprintf "fru_id=%s, ", get_uuid_le($fru_id); - $out .= "fru_text='$fru_text', "; - $out .= get_cper_data_text($cper_data) if ($cper_data); - $out .= "\n"; - } - if ($out ne "") { - print "Extlog events:\n$out\n"; - } else { - print "No Extlog errors.\n\n"; + if ($enable_extlog eq "yes") { + $query = "select id, timestamp, etype, severity, address, fru_id, fru_text, cper_data from extlog_event order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $etype, $severity, $addr, $fru_id, $fru_text, $cper_data)); + $out = ""; + while($query_handle->fetch()) { + $etype_string = get_extlog_type($etype); + $severity_string = get_extlog_severity($severity); + $out .= "$id $timestamp error: "; + $out .= "type=$etype_string, "; + $out .= "severity=$severity_string, "; + $out .= sprintf "address=0x%08x, ", $addr; + $out .= sprintf "fru_id=%s, ", get_uuid_le($fru_id); + $out .= "fru_text='$fru_text', "; + $out .= get_cper_data_text($cper_data) if ($cper_data); + $out .= "\n"; + } + if ($out ne "") { + print "Extlog events:\n$out\n"; + } else { + print "No Extlog errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # devlink errors - $query = "select id, timestamp, bus_name, dev_name, driver_name, reporter_name, msg from devlink_event order by id"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $bus_name, $dev_name, $driver_name, $reporter_name, $msg)); - $out = ""; - while($query_handle->fetch()) { - $out .= "$id $timestamp error: "; - $out .= "bus_name=$bus_name, "; - $out .= "dev_name=$dev_name, "; - $out .= "driver_name=$driver_name, "; - $out .= "reporter_name=$reporter_name, "; - $out .= "message='$msg', "; - $out .= "\n"; - } - if ($out ne "") { - print "Devlink events:\n$out\n"; - } else { - print "No devlink errors.\n\n"; + if ($enable_devlink eq "yes") { + $query = "select id, timestamp, bus_name, dev_name, driver_name, reporter_name, msg from devlink_event order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $bus_name, $dev_name, $driver_name, $reporter_name, $msg)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $timestamp error: "; + $out .= "bus_name=$bus_name, "; + $out .= "dev_name=$dev_name, "; + $out .= "driver_name=$driver_name, "; + $out .= "reporter_name=$reporter_name, "; + $out .= "message='$msg', "; + $out .= "\n"; + } + if ($out ne "") { + print "Devlink events:\n$out\n"; + } else { + print "No devlink errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # Disk errors - $query = "select id, timestamp, dev, sector, nr_sector, error, rwbs, cmd from disk_errors order by id"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $dev, $sector, $nr_sector, $error, $rwbs, $cmd)); - $out = ""; - while($query_handle->fetch()) { - $out .= "$id $timestamp error: "; - $out .= "dev=$dev, "; - $out .= "sector=$sector, "; - $out .= "nr_sector=$nr_sector, "; - $out .= "error='$error', "; - $out .= "rwbs='$rwbs', "; - $out .= "cmd='$cmd', "; - $out .= "\n"; - } - if ($out ne "") { - print "Disk errors\n$out\n"; - } else { - print "No disk errors.\n\n"; + if ($enable_diskerror eq "yes") { + $query = "select id, timestamp, dev, sector, nr_sector, error, rwbs, cmd from disk_errors order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $dev, $sector, $nr_sector, $error, $rwbs, $cmd)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $timestamp error: "; + $out .= "dev=$dev, "; + $out .= "sector=$sector, "; + $out .= "nr_sector=$nr_sector, "; + $out .= "error='$error', "; + $out .= "rwbs='$rwbs', "; + $out .= "cmd='$cmd', "; + $out .= "\n"; + } + if ($out ne "") { + print "Disk errors\n$out\n"; + } else { + print "No disk errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # Memory failure errors - $query = "select id, timestamp, pfn, page_type, action_result from memory_failure_event order by id"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $pfn, $page_type, $action_result)); - $out = ""; - while($query_handle->fetch()) { - $out .= "$id $timestamp error: "; - $out .= "pfn=$pfn, page_type=$page_type, action_result=$action_result\n"; - } - if ($out ne "") { - print "Memory failure events:\n$out\n"; - } else { - print "No Memory failure errors.\n\n"; + if ($enable_mem_failure eq "yes") { + $query = "select id, timestamp, pfn, page_type, action_result from memory_failure_event order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $pfn, $page_type, $action_result)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $timestamp error: "; + $out .= "pfn=$pfn, page_type=$page_type, action_result=$action_result\n"; + } + if ($out ne "") { + print "Memory failure events:\n$out\n"; + } else { + print "No Memory failure errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; # MCE mce_record errors - $query = "select id, timestamp, mcgcap, mcgstatus, status, addr, misc, ip, tsc, walltime, cpu, cpuid, apicid, socketid, cs, bank, cpuvendor, bank_name, error_msg, mcgstatus_msg, mcistatus_msg, user_action, mc_location from mce_record order by id"; - $query_handle = $dbh->prepare($query); - $query_handle->execute(); - $query_handle->bind_columns(\($id, $time, $mcgcap,$mcgstatus, $status, $addr, $misc, $ip, $tsc, $walltime, $cpu, $cpuid, $apicid, $socketid, $cs, $bank, $cpuvendor, $bank_name, $msg, $mcgstatus_msg, $mcistatus_msg, $user_action, $mc_location)); - $out = ""; - while($query_handle->fetch()) { - $out .= "$id $time error: $msg"; - $out .= ", CPU $cpuvendor" if ($cpuvendor); - $out .= ", bank $bank_name" if ($bank_name); - $out .= ", mcg $mcgstatus_msg" if ($mcgstatus_msg); - $out .= ", mci $mcistatus_msg" if ($mcistatus_msg); - $out .= ", $mc_location" if ($mc_location); - $out .= ", $user_action" if ($user_action); - $out .= sprintf ", mcgcap=0x%08x", $mcgcap if ($mcgcap); - $out .= sprintf ", mcgstatus=0x%08x", $mcgstatus if ($mcgstatus); - $out .= sprintf ", status=0x%08x", $status if ($status); - $out .= sprintf ", addr=0x%08x", $addr if ($addr); - $out .= sprintf ", misc=0x%08x", $misc if ($misc); - $out .= sprintf ", ip=0x%08x", $ip if ($ip); - $out .= sprintf ", tsc=0x%08x", $tsc if ($tsc); - $out .= sprintf ", walltime=0x%08x", $walltime if ($walltime); - $out .= sprintf ", cpu=0x%08x", $cpu if ($cpu); - $out .= sprintf ", cpuid=0x%08x", $cpuid if ($cpuid); - $out .= sprintf ", apicid=0x%08x", $apicid if ($apicid); - $out .= sprintf ", socketid=0x%08x", $socketid if ($socketid); - $out .= sprintf ", cs=0x%08x", $cs if ($cs); - $out .= sprintf ", bank=0x%08x", $bank if ($bank); - - $out .= "\n"; - } - if ($out ne "") { - print "MCE events:\n$out\n"; - } else { - print "No MCE errors.\n\n"; + if ($enable_mce eq "yes") { + $query = "select id, timestamp, mcgcap, mcgstatus, status, addr, misc, ip, tsc, walltime, cpu, cpuid, apicid, socketid, cs, bank, cpuvendor, bank_name, error_msg, mcgstatus_msg, mcistatus_msg, user_action, mc_location from mce_record order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $time, $mcgcap,$mcgstatus, $status, $addr, $misc, $ip, $tsc, $walltime, $cpu, $cpuid, $apicid, $socketid, $cs, $bank, $cpuvendor, $bank_name, $msg, $mcgstatus_msg, $mcistatus_msg, $user_action, $mc_location)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $time error: $msg"; + $out .= ", CPU $cpuvendor" if ($cpuvendor); + $out .= ", bank $bank_name" if ($bank_name); + $out .= ", mcg $mcgstatus_msg" if ($mcgstatus_msg); + $out .= ", mci $mcistatus_msg" if ($mcistatus_msg); + $out .= ", $mc_location" if ($mc_location); + $out .= ", $user_action" if ($user_action); + $out .= sprintf ", mcgcap=0x%08x", $mcgcap if ($mcgcap); + $out .= sprintf ", mcgstatus=0x%08x", $mcgstatus if ($mcgstatus); + $out .= sprintf ", status=0x%08x", $status if ($status); + $out .= sprintf ", addr=0x%08x", $addr if ($addr); + $out .= sprintf ", misc=0x%08x", $misc if ($misc); + $out .= sprintf ", ip=0x%08x", $ip if ($ip); + $out .= sprintf ", tsc=0x%08x", $tsc if ($tsc); + $out .= sprintf ", walltime=0x%08x", $walltime if ($walltime); + $out .= sprintf ", cpu=0x%08x", $cpu if ($cpu); + $out .= sprintf ", cpuid=0x%08x", $cpuid if ($cpuid); + $out .= sprintf ", apicid=0x%08x", $apicid if ($apicid); + $out .= sprintf ", socketid=0x%08x", $socketid if ($socketid); + $out .= sprintf ", cs=0x%08x", $cs if ($cs); + $out .= sprintf ", bank=0x%08x", $bank if ($bank); + + $out .= "\n"; + } + if ($out ne "") { + print "MCE events:\n$out\n"; + } else { + print "No MCE errors.\n\n"; + } + $query_handle->finish; } - $query_handle->finish; undef($dbh); } -- 2.17.1

1 0

[PATCH v2 3/8] rasdaemon: ras-mc-ctl: Add memory failure events
by Shiju Jose 26 Jan '21

26 Jan '21

Add supporting memory failure errors (memory_failure_event) to the ras-mc-ctl tool. Sample Log, ras-mc-ctl --summary ... Memory failure events summary: Delayed errors: 4 Failed errors: 1 ... ras-mc-ctl --errors ... Memory failure events: 1 2020-10-28 23:20:41 -0800 error: pfn=0x204000000, page_type=free buddy page, action_result=Delayed 2 2020-10-28 23:31:38 -0800 error: pfn=0x204000000, page_type=free buddy page, action_result=Delayed 3 2020-10-28 23:54:54 -0800 error: pfn=0x205000000, page_type=free buddy page, action_result=Delayed 4 2020-10-29 00:12:25 -0800 error: pfn=0x204000000, page_type=free buddy page, action_result=Delayed 5 2020-10-29 00:26:36 -0800 error: pfn=0x204000000, page_type=free buddy page, action_result=Failed Signed-off-by: Shiju Jose <shiju.jose(a)huawei.com> --- util/ras-mc-ctl.in | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index d8abdbd..eebcc4e 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1120,7 +1120,7 @@ sub summary { require DBI; my ($query, $query_handle, $out); - my ($err_type, $label, $mc, $top, $mid, $low, $count, $msg); + my ($err_type, $label, $mc, $top, $mid, $low, $count, $msg, $action_result); my ($etype, $severity, $etype_string, $severity_string); my ($dev_name, $dev); my ($mpidr); @@ -1225,6 +1225,22 @@ sub summary } $query_handle->finish; + # Memory failure errors + $query = "select action_result, count(*) from memory_failure_event group by action_result"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($action_result, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= "\t$action_result errors: $count\n"; + } + if ($out ne "") { + print "Memory failure events summary:\n$out\n"; + } else { + print "No Memory failure errors.\n\n"; + } + $query_handle->finish; + # MCE mce_record errors $query = "select error_msg, count(*) from mce_record group by error_msg"; $query_handle = $dbh->prepare($query); @@ -1253,6 +1269,7 @@ sub errors my ($bus_name, $dev_name, $driver_name, $reporter_name); my ($dev, $sector, $nr_sector, $error, $rwbs, $cmd); my ($error_count, $affinity, $mpidr, $r_state, $psci_state); + my ($pfn, $page_type, $action_result); my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); @@ -1384,6 +1401,23 @@ sub errors } $query_handle->finish; + # Memory failure errors + $query = "select id, timestamp, pfn, page_type, action_result from memory_failure_event order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + $query_handle->bind_columns(\($id, $timestamp, $pfn, $page_type, $action_result)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $timestamp error: "; + $out .= "pfn=$pfn, page_type=$page_type, action_result=$action_result\n"; + } + if ($out ne "") { + print "Memory failure events:\n$out\n"; + } else { + print "No Memory failure errors.\n\n"; + } + $query_handle->finish; + # MCE mce_record errors $query = "select id, timestamp, mcgcap, mcgstatus, status, addr, misc, ip, tsc, walltime, cpu, cpuid, apicid, socketid, cs, bank, cpuvendor, bank_name, error_msg, mcgstatus_msg, mcistatus_msg, user_action, mc_location from mce_record order by id"; $query_handle = $dbh->prepare($query); -- 2.17.1

1 0

[PATCH v2 2/8] rasdaemon: ras-mc-ctl: Modify ARM processor error summary log
by Shiju Jose 26 Jan '21

26 Jan '21

Add CPU's mpidr information to the ARM processor error summary log. Signed-off-by: Shiju Jose <shiju.jose(a)huawei.com> --- util/ras-mc-ctl.in | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index dd7d56f..d8abdbd 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1123,7 +1123,7 @@ sub summary my ($err_type, $label, $mc, $top, $mid, $low, $count, $msg); my ($etype, $severity, $etype_string, $severity_string); my ($dev_name, $dev); - my ($affinity, $mpidr); + my ($mpidr); my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); @@ -1160,13 +1160,13 @@ sub summary $query_handle->finish; # ARM processor arm_event errors - $query = "select affinity, mpidr, count(*) from arm_event group by affinity, mpidr"; + $query = "select mpidr, count(*) from arm_event group by mpidr"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($affinity, $mpidr, $count)); + $query_handle->bind_columns(\($mpidr, $count)); $out = ""; while($query_handle->fetch()) { - $out .= "\t$count errors\n"; + $out .= sprintf "\tCPU(mpidr=0x%x) has %d errors\n", $mpidr, $count; } if ($out ne "") { print "ARM processor events summary:\n$out\n"; -- 2.17.1

1 0

[PATCH] mm/zswap: fix potential memory leak
by Tian Tao 25 Jan '21

25 Jan '21

If entry is NULL, the requested memory tmp should be freed, otherwise it may cause a memory leak. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com> --- mm/zswap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/mm/zswap.c b/mm/zswap.c index 42d13dd..8d1381b 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -961,6 +961,7 @@ static int zswap_writeback_entry(struct zpool *pool, unsigned long handle) /* entry was invalidated */ spin_unlock(&tree->lock); zpool_unmap_handle(pool, handle); + kfree(tmp); return 0; } spin_unlock(&tree->lock); -- 2.7.4

2 1

[PATCH] genirq/msi: Make sure early activation of all PCI MSIs
by Shameer Kolothum 23 Jan '21

23 Jan '21

We currently do early activation of MSI irqs for PCI/MSI based on the MSI_FLAG_ACTIVATE_EARLY flag. Though this activates all the allocated MSIs in the case of MSI-X, it only does so for the base irq in the case of MSI. This is because, for MSI, there is only one msi_desc entry for all the 32 irqs it can support and the current implementation iterates over the msi entries and ends up activating the base irq only. The above creates an issue on platforms where the msi controller supports direct injection of vLPIs(eg: ARM GICv4 ITS). On these platforms, upon irq activation, ITS driver maps the event to an ITT entry. And for Guest pass-through to work, early mapping of all the dev MSI vectors is required. Otherwise, the vfio irq bypass manager registration will fail. eg, On a HiSilicon D06 platform with GICv4 enabled, Guest boot with zip dev pass-through reports, "vfio-pci 0000:75:00.1: irq bypass producer (token 0000000006e5176a) registration fails: 66311" and Guest boot fails. This is traced to, kvm_arch_irq_bypass_add_producer kvm_vgic_v4_set_forwarding vgic_its_resolve_lpi --> returns E_ITS_INT_UNMAPPED_INTERRUPT Hence make sure we activate all the irqs for both MSI and MSI-x cases. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi(a)huawei.com> --- It is unclear to me whether not performing the early activation of all MSI irqs was deliberate and has consequences on any other platforms. Please let me know. Thanks, Shameer --- kernel/irq/msi.c | 114 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 90 insertions(+), 24 deletions(-) diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 2c0c4d6d0f83..eec187fc32a9 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -395,6 +395,78 @@ static bool msi_check_reservation_mode(struct irq_domain *domain, return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit; } +static void msi_domain_deactivate_irq(struct irq_domain *domain, int irq) +{ + struct irq_data *irqd; + + irqd = irq_domain_get_irq_data(domain, irq); + if (irqd_is_activated(irqd)) + irq_domain_deactivate_irq(irqd); +} + +static int msi_domain_activate_irq(struct irq_domain *domain, + int irq, bool can_reserve) +{ + struct irq_data *irqd; + + irqd = irq_domain_get_irq_data(domain, irq); + if (!can_reserve) { + irqd_clr_can_reserve(irqd); + if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK) + irqd_set_msi_nomask_quirk(irqd); + } + return irq_domain_activate_irq(irqd, can_reserve); +} + +static int msi_domain_activate_msix_irqs(struct irq_domain *domain, + struct device *dev, bool can_reserve) +{ + struct msi_desc *desc; + int ret, irq; + + for_each_msi_entry(desc, dev) { + irq = desc->irq; + ret = msi_domain_activate_irq(domain, irq, can_reserve); + if (ret) + goto out; + } + return 0; + +out: + for_each_msi_entry(desc, dev) { + if (irq == desc->irq) + break; + msi_domain_deactivate_irq(domain, desc->irq); + } + return ret; +} + +static int msi_domain_activate_msi_irqs(struct irq_domain *domain, + struct device *dev, bool can_reserve) +{ + struct msi_desc *desc; + int i, ret, base, irq; + + desc = first_msi_entry(dev); + base = desc->irq; + + for (i = 0; i < desc->nvec_used; i++) { + irq = base + i; + ret = msi_domain_activate_irq(domain, irq, can_reserve); + if (ret) + goto out; + } + return 0; + +out: + for (i = 0; i < desc->nvec_used; i++) { + if (irq == base + i) + break; + msi_domain_deactivate_irq(domain, base + i); + } + return ret; +} + int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, int nvec) { @@ -443,21 +515,25 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, else dev_dbg(dev, "irq [%d-%d] for MSI\n", virq, virq + desc->nvec_used - 1); - /* - * This flag is set by the PCI layer as we need to activate - * the MSI entries before the PCI layer enables MSI in the - * card. Otherwise the card latches a random msi message. - */ - if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY)) - continue; + } - irq_data = irq_domain_get_irq_data(domain, desc->irq); - if (!can_reserve) { - irqd_clr_can_reserve(irq_data); - if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK) - irqd_set_msi_nomask_quirk(irq_data); - } - ret = irq_domain_activate_irq(irq_data, can_reserve); + /* + * This flag is set by the PCI layer as we need to activate + * the MSI entries before the PCI layer enables MSI in the + * card. Otherwise the card latches a random msi message. + * Early activation is also required when the msi controller + * supports direct injection of virtual LPIs(eg. ARM GICv4 ITS). + * Otherwise, the DevID/EventID -> LPI translation for pass-through + * devices will fail. Make sure we do activate all the allocated + * irqs for MSI and MSI-X cases. + */ + if ((info->flags & MSI_FLAG_ACTIVATE_EARLY)) { + desc = first_msi_entry(dev); + + if (desc->msi_attrib.is_msix) + ret = msi_domain_activate_msix_irqs(domain, dev, can_reserve); + else + ret = msi_domain_activate_msi_irqs(domain, dev, can_reserve); if (ret) goto cleanup; } @@ -475,16 +551,6 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, return 0; cleanup: - for_each_msi_entry(desc, dev) { - struct irq_data *irqd; - - if (desc->irq == virq) - break; - - irqd = irq_domain_get_irq_data(domain, desc->irq); - if (irqd_is_activated(irqd)) - irq_domain_deactivate_irq(irqd); - } msi_domain_free_irqs(domain, dev); return ret; } -- 2.17.1

3 3

[dpdk-dev] [PATCH v2 0/2] Add Hisilicon kunpeng series SoC build
by Chengchang Tang 23 Jan '21

23 Jan '21

Add cross build file for kunpeng series ARM SoC and optimize the compile. Chengchang Tang (2): config: add Hisilicon kunpeng 920 SoC build config: add Hisilicon kunpeng 930 Soc build config/arm/arm64_kunpeng920_linux_gcc | 19 +++++++++++++++ config/arm/arm64_kunpeng930_linux_gcc | 19 +++++++++++++++ config/arm/meson.build | 27 ++++++++++++++++++++++ .../linux_gsg/cross_build_dpdk_for_arm64.rst | 5 ++++ 4 files changed, 70 insertions(+) create mode 100644 config/arm/arm64_kunpeng920_linux_gcc create mode 100644 config/arm/arm64_kunpeng930_linux_gcc -- 2.7.4

1 2

[RFC] some questions for speed_capa usage
by oulijun 23 Jan '21

23 Jan '21

Hi, The 'speed_capa' will be reported in rte_eth_dev_info_get API. How should users use the field? 1) The driver reports only the capabilities supported by the NIC, and users only obtain the capabilities. Maybe, there is a case that a rate bit in 'speed_capa' is not supported by the current transmission medium, such as, copper cable optical modules and optical interface modules. 2) The field is used only to inform users of the speed_capa supported by the current transmission medium. And users set the fixed speed or auto-negotiation by using 'link_speeds' according to the field. According to the existing implementations of all drivers, it seems that both of the above behaviors exist. How should we report and use it? Thanks Lijun Ou

2 2

[PATCH RFC 0/7] RDMA/hns: Add support for Dynamic Context Attachment
by Weihang Li 22 Jan '21

22 Jan '21

The hip09 introduces the DCA(Dynamic Context Attachment) feature which supports many RC QPs to share the WQE buffer in a memory pool. If a QP enables DCA feature, the WQE's buffer will not be allocated when creating but when the users start to post WRs. This will reduce the memory consumption when there are too many QPs are inactive. Xi Wang (7): RDMA/hns: Introduce DCA for RC QP RDMA/hns: Add method for shrinking DCA memory pool RDMA/hns: Configure DCA mode for the userspace QP RDMA/hns: Add method for attaching WQE buffer RDMA/hns: Setup the configuration of WQE addressing to QPC RDMA/hns: Add method to detach WQE buffer RDMA/hns: Add method to query WQE buffer's address drivers/infiniband/hw/hns/Makefile | 2 +- drivers/infiniband/hw/hns/hns_roce_dca.c | 1264 +++++++++++++++++++++++++++ drivers/infiniband/hw/hns/hns_roce_dca.h | 68 ++ drivers/infiniband/hw/hns/hns_roce_device.h | 32 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 223 ++++- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 3 + drivers/infiniband/hw/hns/hns_roce_main.c | 27 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 119 ++- include/uapi/rdma/hns-abi.h | 60 ++ 9 files changed, 1751 insertions(+), 47 deletions(-) create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.c create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.h -- 2.8.1

4 15

[PATCH v2 for-next] RDMA/hns: Add caps flag for UD inline of userspace
by Weihang Li 22 Jan '21

22 Jan '21

HIP09 supports UD inline up to size of 1024 Bytes, the caps flag is got from firmware and passed back to userspace when creating QP. Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- Changes since v1: - Avoid overwriting some fields in set_default_caps(). - Link: https://patchwork.kernel.org/project/linux-rdma/patch/1609810615-50515-1-gi… drivers/infiniband/hw/hns/hns_roce_device.h | 1 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 18 +++++++++++------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 1 + drivers/infiniband/hw/hns/hns_roce_qp.c | 3 +++ include/uapi/rdma/hns-abi.h | 1 + 5 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 55d5386..87716da 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -214,6 +214,7 @@ enum { HNS_ROCE_CAP_FLAG_FRMR = BIT(8), HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), + HNS_ROCE_CAP_FLAG_UD_SQ_INL = BIT(13), HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), HNS_ROCE_CAP_FLAG_STASH = BIT(17), }; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 833e1f2..1454cd9 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1800,7 +1800,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; - caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; caps->num_uars = HNS_ROCE_V2_UAR_NUM; caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; @@ -1817,7 +1816,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; - caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; @@ -1825,7 +1823,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; - caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; caps->reserved_lkey = 0; caps->reserved_pds = 0; @@ -1871,11 +1868,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; caps->pkey_table_len[0] = 1; - caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; - caps->aeqe_size = HNS_ROCE_AEQE_SIZE; - caps->ceqe_size = HNS_ROCE_CEQE_SIZE; caps->local_ca_ack_delay = 0; caps->max_mtu = IB_MTU_4096; @@ -1897,7 +1891,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->cqc_timer_buf_pg_sz = 0; caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; - caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; caps->sccc_ba_pg_sz = 0; caps->sccc_buf_pg_sz = 0; caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; @@ -1916,6 +1909,16 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->gmv_buf_pg_sz = 0; caps->gid_table_len[0] = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); + caps->flags |= HNS_ROCE_CAP_FLAG_UD_SQ_INL; + caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INL_EXT; + } else { + caps->aeqe_size = HNS_ROCE_AEQE_SIZE; + caps->ceqe_size = HNS_ROCE_CEQE_SIZE; + caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; + caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; + caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; + caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; + caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; } } @@ -5084,6 +5087,7 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, qp_attr->cur_qp_state = qp_attr->qp_state; qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; + qp_attr->cap.max_inline_data = hr_qp->max_inline_data; if (!ibqp->uobject) { qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index bdaccf8..ab685a4 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -61,6 +61,7 @@ #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 +#define HNS_ROCE_V2_MAX_SQ_INL_EXT 0x400 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32 #define HNS_ROCE_V2_UAR_NUM 256 #define HNS_ROCE_V2_PHY_UAR_NUM 1 diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index d8e2fe5..b19fcbd 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -1020,6 +1020,9 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, } if (udata) { + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_UD_SQ_INL) + resp.cap_flags |= HNS_ROCE_QP_CAP_UD_SQ_INL; + ret = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); if (ret) { diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h index 90b739d..79dba94 100644 --- a/include/uapi/rdma/hns-abi.h +++ b/include/uapi/rdma/hns-abi.h @@ -77,6 +77,7 @@ enum hns_roce_qp_cap_flags { HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0, HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1, HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2, + HNS_ROCE_QP_CAP_UD_SQ_INL = 1 << 3, }; struct hns_roce_ib_create_qp_resp { -- 2.8.1

4 6

[PATCH] perf metricgroup: Fix for metrics containing duration_time
by John Garry 22 Jan '21

22 Jan '21

Metrics containing duration_time cause a segfault: $./perf stat -v -M L1D_Cache_Fill_BW sleep 1 Using CPUID GenuineIntel-6-3D-4 metric expr 64 * l1d.replacement / 1000000000 / duration_time for L1D_Cache_Fill_BW found event duration_time found event l1d.replacement adding {l1d.replacement}:W,duration_time l1d.replacement -> cpu/umask=0x1,(null)=0x1e8483,event=0x51/ Segmentation fault In commit c2337d67199a ("perf metricgroup: Fix metrics using aliases covering multiple PMUs"), the logic in find_evsel_group() when iter'ing events was changed to not only select events in same group, but also for aliased PMUs. Checking whether events were for aliased PMUs was done by comparing the event PMU name. This was not safe for duration_time event, which has no associated PMU (and no PMU name), so fix by checking if the event PMU name is set also. Fixes: c2337d67199a ("perf metricgroup: Fix metrics using aliases covering multiple PMUs") Reported-by: Joakim Zhang <qiangqing.zhang(a)nxp.com> Signed-off-by: John Garry <john.garry(a)huawei.com> diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 2e60ee170abc..e6d3452031e5 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -162,6 +162,14 @@ static bool contains_event(struct evsel **metric_events, int num_events, return false; } +static bool evsel_same_pmu(struct evsel *ev1, struct evsel *ev2) +{ + if (!ev1->pmu_name || !ev2->pmu_name) + return false; + + return !strcmp(ev1->pmu_name, ev2->pmu_name); +} + /** * Find a group of events in perf_evlist that correspond to those from a parsed * metric expression. Note, as find_evsel_group is called in the same order as @@ -280,8 +288,7 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist, */ if (!has_constraint && ev->leader != metric_events[i]->leader && - !strcmp(ev->leader->pmu_name, - metric_events[i]->leader->pmu_name)) + evsel_same_pmu(ev->leader, metric_events[i]->leader)) break; if (!strcmp(metric_events[i]->name, ev->name)) { set_bit(ev->idx, evlist_used); -- 2.26.2

4 6

[PATCH for-next 0/3] RDMA/hns: Refactor codes about memory
by Weihang Li 22 Jan '21

22 Jan '21

This series refactors memory related codes, including MR, MTR(Memory Translate Region) and MPT(Memory Protection Table). Lang Cheng (2): RDMA/hns: Optimize the MR registration process RDMA/hns: Use new interface to set MPT related fields Xi Wang (1): RDMA/hns: Refactor the MTR creation flow drivers/infiniband/hw/hns/hns_roce_common.h | 22 ++ drivers/infiniband/hw/hns/hns_roce_cq.c | 1 - drivers/infiniband/hw/hns/hns_roce_device.h | 4 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 77 +++--- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 39 +++ drivers/infiniband/hw/hns/hns_roce_mr.c | 404 +++++++++++----------------- drivers/infiniband/hw/hns/hns_roce_qp.c | 1 - drivers/infiniband/hw/hns/hns_roce_srq.c | 2 - 8 files changed, 258 insertions(+), 292 deletions(-) -- 2.8.1

2 4

[PATCH] mm/zswap: fix variable 'entry' is uninitialized when used
by Tian Tao 21 Jan '21

21 Jan '21

the entry has not been initialized when it is used, so allocate PAGE_SIZE Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> Reported-by: kernel test robot <lkp(a)intel.com> --- mm/zswap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/zswap.c b/mm/zswap.c index 6e0bb61..4b7b6ad 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -944,7 +944,7 @@ static int zswap_writeback_entry(struct zpool *pool, unsigned long handle) if (!zpool_can_sleep_mapped(pool)) { - tmp = kmalloc(entry->length, GFP_ATOMIC); + tmp = kmalloc(PAGE_SIZE, GFP_ATOMIC); if (!tmp) return -ENOMEM; } -- 2.7.4

2 1

[PATCH net-next] net: hns3: debugfs add dump tm info of nodes, priority and qset
by Huazhong Tan 21 Jan '21

21 Jan '21

From: Guangbin Huang <huangguangbin2(a)huawei.com> To increase methods to dump more tm info, adds three debugfs commands to dump tm info of nodes, priority and qset. And a new tm file of debugfs is created for only dumping tm info. Unlike previous debugfs commands, to dump each tm information, user needs to enter two commands now. The first command writes parameters to tm and the second command reads info from tm. For examples, to dump tm info of priority 0, user needs to enter follow two commands: 1. echo dump priority 0 > tm 2. cat tm The reason for adding new tm file is because we accepted Jakub Kicinski's opinion as link https://lkml.org/lkml/2020/9/29/2101. And in order to avoid generating too many files, we implement write ops to allow user to input parameters. However, If there are two or more users concurrently write parameters to tm, parameters of the latest command will overwrite previous commands, this concurrency problem will confuse users, but now there is no good method to fix it. Signed-off-by: Guangbin Huang <huangguangbin2(a)huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong(a)huawei.com> --- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 9 + drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 118 ++++++++++ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 6 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 1 + .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 251 +++++++++++++++++++++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 1 + .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 23 ++ 8 files changed, 411 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index a7daf6d..39b8ac7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -247,6 +247,10 @@ struct hnae3_vector_info { int vector; }; +enum hnae3_dbg_module_type { + HNAE3_DBG_MODULE_TYPE_TM, +}; + #define HNAE3_RING_TYPE_B 0 #define HNAE3_RING_TYPE_TX 0 #define HNAE3_RING_TYPE_RX 1 @@ -465,6 +469,8 @@ struct hnae3_ae_dev { * Delete clsflower rule * cls_flower_active * Check if any cls flower rule exist + * dbg_read_cmd + * Execute debugfs read command. */ struct hnae3_ae_ops { int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); @@ -620,6 +626,8 @@ struct hnae3_ae_ops { int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, u16 flow_id, struct flow_keys *fkeys); int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf); + int (*dbg_read_cmd)(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len); pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); bool (*get_hw_reset_stat)(struct hnae3_handle *handle); bool (*ae_dev_resetting)(struct hnae3_handle *handle); @@ -757,6 +765,7 @@ struct hnae3_handle { u8 netdev_flags; struct dentry *hnae3_dbgfs; + int dbgfs_type; /* Network interface message level enabled bits */ u32 msg_enable; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c index 9d4e9c0..e2b6924 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c @@ -12,6 +12,10 @@ static struct dentry *hns3_dbgfs_root; +#define HNS3_HELP_INFO "help" + +#define HNS3_DBG_MODULE_NAME_TM "tm" + static int hns3_dbg_queue_info(struct hnae3_handle *h, const char *cmd_buf) { @@ -338,6 +342,23 @@ static void hns3_dbg_help(struct hnae3_handle *h) dev_info(&h->pdev->dev, "%s", printf_buf); } +static void hns3_dbg_tm_help(struct hnae3_handle *h, char *buf, int len) +{ + struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + int pos; + + pos = scnprintf(buf, len, "available commands:\n"); + + if (!hns3_is_phys_func(h->pdev)) + return; + + if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) + pos += scnprintf(buf + pos, len - pos, "dump nodes\n"); + + pos += scnprintf(buf + pos, len - pos, "dump priority <pri id>\n"); + pos += scnprintf(buf + pos, len - pos, "dump qset <qset id>\n"); +} + static void hns3_dbg_dev_caps(struct hnae3_handle *h) { struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); @@ -484,6 +505,93 @@ static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer, return count; } +static ssize_t hns3_dbg_tm_read(struct file *filp, char __user *buffer, + size_t count, loff_t *ppos) +{ + struct hnae3_handle *handle = filp->private_data; + const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hns3_nic_priv *priv = handle->priv; + char *cmd_buf, *read_buf; + ssize_t size = 0; + int ret = 0; + + if (strncmp(filp->f_path.dentry->d_iname, HNS3_DBG_MODULE_NAME_TM, + strlen(HNS3_DBG_MODULE_NAME_TM)) != 0) + return -EINVAL; + + if (!priv->dbg_in_msg.tm) + return -EINVAL; + + read_buf = kzalloc(HNS3_DBG_READ_LEN, GFP_KERNEL); + if (!read_buf) + return -ENOMEM; + + cmd_buf = priv->dbg_in_msg.tm; + handle->dbgfs_type = HNAE3_DBG_MODULE_TYPE_TM; + + if (strncmp(cmd_buf, HNS3_HELP_INFO, strlen(HNS3_HELP_INFO)) == 0) + hns3_dbg_tm_help(handle, read_buf, HNS3_DBG_READ_LEN); + else if (ops->dbg_read_cmd) + ret = ops->dbg_read_cmd(handle, cmd_buf, read_buf, + HNS3_DBG_READ_LEN); + + if (ret) { + dev_info(priv->dev, "unknown command\n"); + goto out; + } + + size = simple_read_from_buffer(buffer, count, ppos, read_buf, + strlen(read_buf)); +out: + kfree(read_buf); + return size; +} + +static ssize_t hns3_dbg_tm_write(struct file *filp, const char __user *buffer, + size_t count, loff_t *ppos) +{ + struct hnae3_handle *handle = filp->private_data; + struct hns3_nic_priv *priv = handle->priv; + char *cmd_buf, *cmd_buf_tmp; + int uncopied_bytes; + + if (*ppos != 0) + return 0; + + /* Judge if the instance is being reset. */ + if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || + test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) + return 0; + + if (count > HNS3_DBG_WRITE_LEN) + return -ENOSPC; + + kfree(priv->dbg_in_msg.tm); + priv->dbg_in_msg.tm = NULL; + + cmd_buf = kzalloc(count + 1, GFP_KERNEL); + if (!cmd_buf) + return count; + + uncopied_bytes = copy_from_user(cmd_buf, buffer, count); + if (uncopied_bytes) { + kfree(cmd_buf); + return -EFAULT; + } + + cmd_buf[count] = '\0'; + + cmd_buf_tmp = strchr(cmd_buf, '\n'); + if (cmd_buf_tmp) { + *cmd_buf_tmp = '\0'; + count = cmd_buf_tmp - cmd_buf + 1; + } + + priv->dbg_in_msg.tm = cmd_buf; + + return count; +} + static const struct file_operations hns3_dbg_cmd_fops = { .owner = THIS_MODULE, .open = simple_open, @@ -491,6 +599,13 @@ static const struct file_operations hns3_dbg_cmd_fops = { .write = hns3_dbg_cmd_write, }; +static const struct file_operations hns3_dbg_tm_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = hns3_dbg_tm_read, + .write = hns3_dbg_tm_write, +}; + void hns3_dbg_init(struct hnae3_handle *handle) { const char *name = pci_name(handle->pdev); @@ -499,6 +614,9 @@ void hns3_dbg_init(struct hnae3_handle *handle) debugfs_create_file("cmd", 0600, handle->hnae3_dbgfs, handle, &hns3_dbg_cmd_fops); + + debugfs_create_file(HNS3_DBG_MODULE_NAME_TM, 0600, handle->hnae3_dbgfs, + handle, &hns3_dbg_tm_fops); } void hns3_dbg_uninit(struct hnae3_handle *handle) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h index 0a7b606..76dd30d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h @@ -490,6 +490,10 @@ struct hns3_enet_tqp_vector { unsigned long last_jiffies; } ____cacheline_internodealigned_in_smp; +struct hns3_dbg_input_msg { + char *tm; +}; + struct hns3_nic_priv { struct hnae3_handle *ae_handle; struct net_device *netdev; @@ -510,6 +514,8 @@ struct hns3_nic_priv { struct hns3_enet_coalesce tx_coal; struct hns3_enet_coalesce rx_coal; + + struct hns3_dbg_input_msg dbg_in_msg; }; union l3_hdr_info { diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h index edfadb5..f861bdb 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h @@ -160,6 +160,7 @@ enum hclge_opcode_type { HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, + HCLGE_OPC_TM_NODES = 0x0816, HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, HCLGE_OPC_QSET_DFX_STS = 0x0844, HCLGE_OPC_PRI_DFX_STS = 0x0845, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c index 8f6dea5..1f13a5b 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c @@ -800,6 +800,224 @@ static void hclge_dbg_dump_tm_map(struct hclge_dev *hdev, cmd, ret); } +static void hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len) +{ + struct hclge_tm_nodes_cmd *nodes; + struct hclge_desc desc; + int pos = 0; + int ret; + + if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) { + dev_err(&hdev->pdev->dev, "unsupported command!\n"); + return; + } + + hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to dump tm nodes, ret = %d\n", ret); + return; + } + + nodes = (struct hclge_tm_nodes_cmd *)desc.data; + + pos += scnprintf(buf + pos, len - pos, "PG base_id: %u\n", + nodes->pg_base_id); + pos += scnprintf(buf + pos, len - pos, "PG number: %u\n", + nodes->pg_num); + pos += scnprintf(buf + pos, len - pos, "PRI base_id: %u\n", + nodes->pri_base_id); + pos += scnprintf(buf + pos, len - pos, "PRI number: %u\n", + nodes->pri_num); + pos += scnprintf(buf + pos, len - pos, "QSET base_id: %u\n", + le16_to_cpu(nodes->qset_base_id)); + pos += scnprintf(buf + pos, len - pos, "QSET number: %u\n", + le16_to_cpu(nodes->qset_num)); + pos += scnprintf(buf + pos, len - pos, "QUEUE base_id: %u\n", + le16_to_cpu(nodes->queue_base_id)); + pos += scnprintf(buf + pos, len - pos, "QUEUE number: %u\n", + le16_to_cpu(nodes->queue_num)); +} + +static int hclge_dbg_dump_tm_pri_sch(struct hclge_dev *hdev, u8 pri_id, + char *buf, int len) +{ + struct hclge_priority_weight_cmd *priority_weight; + struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode; + enum hclge_opcode_type cmd; + struct hclge_desc desc; + int pos = 0; + int ret; + + cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + pri_sch_mode = (struct hclge_pri_sch_mode_cfg_cmd *)desc.data; + pri_sch_mode->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_sch_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "PRI schedule mode: %s\n", + (pri_sch_mode->sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK) ? + "dwrr" : "sp"); + + cmd = HCLGE_OPC_TM_PRI_WEIGHT; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + priority_weight = (struct hclge_priority_weight_cmd *)desc.data; + priority_weight->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_sch_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "PRI dwrr: %u\n", + priority_weight->dwrr); + + return pos; + +err_tm_pri_sch_cmd_send: + dev_err(&hdev->pdev->dev, + "failed to dump tm priority(0x%x), ret = %d\n", cmd, ret); + + return pos; +} + +static void hclge_dbg_dump_tm_pri_shaping(struct hclge_dev *hdev, u8 pri_id, + char *buf, int len) +{ + struct hclge_pri_shapping_cmd *shap_cfg_cmd; + u8 ir_u, ir_b, ir_s, bs_b, bs_s; + enum hclge_opcode_type cmd; + struct hclge_desc desc; + u32 shapping_para; + int pos = 0; + int ret; + + cmd = HCLGE_OPC_TM_PRI_C_SHAPPING; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; + shap_cfg_cmd->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_shaping_cmd_send; + + shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para); + ir_b = hclge_tm_get_field(shapping_para, IR_B); + ir_u = hclge_tm_get_field(shapping_para, IR_U); + ir_s = hclge_tm_get_field(shapping_para, IR_S); + bs_b = hclge_tm_get_field(shapping_para, BS_B); + bs_s = hclge_tm_get_field(shapping_para, BS_S); + pos += scnprintf(buf + pos, len - pos, + "PRI_C ir_b:%u ir_u:%u ir_s:%u bs_b:%u bs_s:%u\n", + ir_b, ir_u, ir_s, bs_b, bs_s); + pos += scnprintf(buf + pos, len - pos, "PRI_C flag: %#x\n", + shap_cfg_cmd->flag); + pos += scnprintf(buf + pos, len - pos, "PRI_C pri_rate: %u(Mbps)\n", + le32_to_cpu(shap_cfg_cmd->pri_rate)); + + cmd = HCLGE_OPC_TM_PRI_P_SHAPPING; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; + shap_cfg_cmd->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_shaping_cmd_send; + + shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para); + ir_b = hclge_tm_get_field(shapping_para, IR_B); + ir_u = hclge_tm_get_field(shapping_para, IR_U); + ir_s = hclge_tm_get_field(shapping_para, IR_S); + bs_b = hclge_tm_get_field(shapping_para, BS_B); + bs_s = hclge_tm_get_field(shapping_para, BS_S); + pos += scnprintf(buf + pos, len - pos, + "PRI_P ir_b:%u ir_u:%u ir_s:%u bs_b:%u bs_s:%u\n", + ir_b, ir_u, ir_s, bs_b, bs_s); + pos += scnprintf(buf + pos, len - pos, "PRI_P flag: %#x\n", + shap_cfg_cmd->flag); + pos += scnprintf(buf + pos, len - pos, "PRI_P pri_rate: %u(Mbps)\n", + le32_to_cpu(shap_cfg_cmd->pri_rate)); + + return; + +err_tm_pri_shaping_cmd_send: + dev_err(&hdev->pdev->dev, + "failed to dump tm priority(0x%x), ret = %d\n", cmd, ret); +} + +static void hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, const char *cmd_buf, + char *buf, int len) +{ + int ret, pos; + u8 pri_id; + + ret = kstrtou8(cmd_buf, 0, &pri_id); + pri_id = (ret != 0) ? 0 : pri_id; + + pos = scnprintf(buf, len, "priority id: %u\n", pri_id); + + pos += hclge_dbg_dump_tm_pri_sch(hdev, pri_id, buf + pos, len - pos); + hclge_dbg_dump_tm_pri_shaping(hdev, pri_id, buf + pos, len - pos); +} + +static void hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, const char *cmd_buf, + char *buf, int len) +{ + struct hclge_qs_sch_mode_cfg_cmd *qs_sch_mode; + struct hclge_qs_weight_cmd *qs_weight; + struct hclge_qs_to_pri_link_cmd *map; + enum hclge_opcode_type cmd; + struct hclge_desc desc; + int ret, pos; + u16 qset_id; + + ret = kstrtou16(cmd_buf, 0, &qset_id); + qset_id = (ret != 0) ? 0 : qset_id; + + pos = scnprintf(buf, len, "qset id: %u\n", qset_id); + + cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK; + map = (struct hclge_qs_to_pri_link_cmd *)desc.data; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + map->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_qset_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "QS map pri id: %u\n", + map->priority); + pos += scnprintf(buf + pos, len - pos, "QS map link_vld: %u\n", + map->link_vld); + + cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + qs_sch_mode = (struct hclge_qs_sch_mode_cfg_cmd *)desc.data; + qs_sch_mode->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_qset_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "QS schedule mode: %s\n", + (qs_sch_mode->sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK) ? + "dwrr" : "sp"); + + cmd = HCLGE_OPC_TM_QS_WEIGHT; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + qs_weight = (struct hclge_qs_weight_cmd *)desc.data; + qs_weight->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_qset_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "QS dwrr: %u\n", + qs_weight->dwrr); + + return; + +err_tm_qset_cmd_send: + dev_err(&hdev->pdev->dev, "failed to dump tm qset(0x%x), ret = %d\n", + cmd, ret); +} + static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev) { struct hclge_cfg_pause_param_cmd *pause_param; @@ -1591,3 +1809,36 @@ int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf) return 0; } + +static int hclge_dbg_read_cmd_tm(struct hnae3_handle *handle, + const char *cmd_buf, char *buf, int len) +{ +#define DUMP_TM_NODE "dump nodes" +#define DUMP_TM_PRI "dump priority" +#define DUMP_TM_QSET "dump qset" + + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + if (strncmp(cmd_buf, DUMP_TM_NODE, strlen(DUMP_TM_NODE)) == 0) + hclge_dbg_dump_tm_nodes(hdev, buf, len); + else if (strncmp(cmd_buf, DUMP_TM_PRI, strlen(DUMP_TM_PRI)) == 0) + hclge_dbg_dump_tm_pri(hdev, &cmd_buf[sizeof(DUMP_TM_PRI)], + buf, len); + else if (strncmp(cmd_buf, DUMP_TM_QSET, strlen(DUMP_TM_QSET)) == 0) + hclge_dbg_dump_tm_qset(hdev, &cmd_buf[sizeof(DUMP_TM_QSET)], + buf, len); + else + return -EINVAL; + + return 0; +} + +int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len) +{ + if (handle->dbgfs_type == HNAE3_DBG_MODULE_TYPE_TM) + return hclge_dbg_read_cmd_tm(handle, cmd_buf, buf, len); + + return -EINVAL; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index c242883..16ccb1a 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -11850,6 +11850,7 @@ static const struct hnae3_ae_ops hclge_ops = { .enable_fd = hclge_enable_fd, .add_arfs_entry = hclge_add_fd_entry_by_arfs, .dbg_run_cmd = hclge_dbg_run_cmd, + .dbg_read_cmd = hclge_dbg_read_cmd, .handle_hw_ras_error = hclge_handle_hw_ras_error, .get_hw_reset_stat = hclge_get_hw_reset_stat, .ae_dev_resetting = hclge_ae_dev_resetting, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index ca46bc9..32e5f82 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -1006,6 +1006,8 @@ int hclge_vport_start(struct hclge_vport *vport); void hclge_vport_stop(struct hclge_vport *vport); int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf); +int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len); u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); int hclge_notify_client(struct hclge_dev *hdev, enum hnae3_reset_notify_type type); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h index 5498d73..4fd7e4f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h @@ -65,6 +65,18 @@ struct hclge_priority_weight_cmd { u8 dwrr; }; +struct hclge_pri_sch_mode_cfg_cmd { + u8 pri_id; + u8 rev[3]; + u8 sch_mode; +}; + +struct hclge_qs_sch_mode_cfg_cmd { + __le16 qs_id; + u8 rev[2]; + u8 sch_mode; +}; + struct hclge_qs_weight_cmd { __le16 qs_id; u8 dwrr; @@ -173,6 +185,17 @@ struct hclge_shaper_ir_para { u8 ir_s; /* IR_S parameter of IR shaper */ }; +struct hclge_tm_nodes_cmd { + u8 pg_base_id; + u8 pri_base_id; + __le16 qset_base_id; + __le16 queue_base_id; + u8 pg_num; + u8 pri_num; + __le16 qset_num; + __le16 queue_num; +}; + #define hclge_tm_set_field(dest, string, val) \ hnae3_set_field((dest), \ (HCLGE_TM_SHAP_##string##_MSK), \ -- 2.7.4

2 6

[PATCH v2 0/8] rasdaemon: add support for memory_failure events,
by Shiju Jose 20 Jan '21

20 Jan '21

Add support for the memory_failure trace event in the rasdaemon and add improvements & support for the vendor specific errors in the util/ras-mc-ctl.in. Changes: v1 -> v2 1. Fix the feedback by Mauro for the fix patch for the exception in the ras-mc-ctl.in. 2. Rebased and grouped the previous v1 rasdaemon patches posted. Shiju Jose (8): rasdaemon: add support for memory_failure events rasdaemon: ras-mc-ctl: Modify ARM processor error summary log rasdaemon: ras-mc-ctl: Add memory failure events rasdaemon: ras-mc-ctl: Fix for exception when an event is not enabled rasdaemon: ras-mc-ctl: Add support for the vendor-specific errors rasdaemon: ras-mc-ctl: Add support for HiSilicon Kunpeng920 errors rasdaemon: ras-mc-ctl: Add support for HiSilicon Kunpeng9xx common errors rasdaemon: Modify confiure.ac for Hisilicon Kunpeng errors .travis.yml | 2 +- Makefile.am | 7 +- configure.ac | 20 +- ras-events.c | 15 + ras-events.h | 1 + ras-memory-failure-handler.c | 179 +++++++++ ras-memory-failure-handler.h | 25 ++ ras-record.c | 70 ++++ ras-record.h | 13 + ras-report.c | 68 ++++ ras-report.h | 2 + util/ras-mc-ctl.in | 737 +++++++++++++++++++++++++---------- 12 files changed, 927 insertions(+), 212 deletions(-) create mode 100644 ras-memory-failure-handler.c create mode 100644 ras-memory-failure-handler.h -- 2.17.1

1 8

[PATCH for-rc] RDMA/hns: Use mutex instead of spinlock for ida allocation
by Weihang Li 20 Jan '21

20 Jan '21

From: Yangyang Li <liyangyang20(a)huawei.com> GFP_KERNEL may cause ida_alloc_range() to sleep, but the spinlock covering this function is not allowed to sleep, so the spinlock needs to be changed to mutex. As there is a certain chance of memory allocation failure, GFP_ATOMIC is not suitable for QP allocation scenarios. Fixes: 71586dd20010 ("RDMA/hns: Create QP with selected QPN for bank load balance") Signed-off-by: Yangyang Li <liyangyang20(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_device.h | 2 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 11 ++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 55d5386..ad82532 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -532,7 +532,7 @@ struct hns_roce_qp_table { struct hns_roce_hem_table sccc_table; struct mutex scc_mutex; struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; - spinlock_t bank_lock; + struct mutex bank_mutex; }; struct hns_roce_cq_table { diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index d8e2fe5..1116371 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -209,7 +209,7 @@ static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) hr_qp->doorbell_qpn = 1; } else { - spin_lock(&qp_table->bank_lock); + mutex_lock(&qp_table->bank_mutex); bankid = get_least_load_bankid_for_qp(qp_table->bank); ret = alloc_qpn_with_bankid(&qp_table->bank[bankid], bankid, @@ -217,12 +217,12 @@ static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) if (ret) { ibdev_err(&hr_dev->ib_dev, "failed to alloc QPN, ret = %d\n", ret); - spin_unlock(&qp_table->bank_lock); + mutex_unlock(&qp_table->bank_mutex); return ret; } qp_table->bank[bankid].inuse++; - spin_unlock(&qp_table->bank_lock); + mutex_unlock(&qp_table->bank_mutex); hr_qp->doorbell_qpn = (u32)num; } @@ -408,9 +408,9 @@ static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) ida_free(&hr_dev->qp_table.bank[bankid].ida, hr_qp->qpn >> 3); - spin_lock(&hr_dev->qp_table.bank_lock); + mutex_lock(&hr_dev->qp_table.bank_mutex); hr_dev->qp_table.bank[bankid].inuse--; - spin_unlock(&hr_dev->qp_table.bank_lock); + mutex_unlock(&hr_dev->qp_table.bank_mutex); } static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap, @@ -1371,6 +1371,7 @@ int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) unsigned int i; mutex_init(&qp_table->scc_mutex); + mutex_init(&qp_table->bank_mutex); xa_init(&hr_dev->qp_table_xa); reserved_from_bot = hr_dev->caps.reserved_qps; -- 2.8.1

2 1

Re: [RFC PATCH 1/2] EDAC/ghes: Add EDAC device for the CPU caches
by Shiju Jose 19 Jan '21

19 Jan '21

Hi Boris, Thanks for the feedback. Apologies for the delay. >-----Original Message----- >From: Borislav Petkov [mailto:bp@alien8.de] >Sent: 31 December 2020 16:44 >To: Shiju Jose <shiju.jose(a)huawei.com> >Cc: linux-edac(a)vger.kernel.org; linux-acpi(a)vger.kernel.org; linux- >kernel(a)vger.kernel.org; james.morse(a)arm.com; >mchehab+huawei(a)kernel.org; tony.luck(a)intel.com; rjw(a)rjwysocki.net; >lenb(a)kernel.org; rrichter(a)marvell.com; Linuxarm <linuxarm(a)huawei.com>; >xuwei (O) <xuwei5(a)huawei.com>; Jonathan Cameron ><jonathan.cameron(a)huawei.com>; John Garry <john.garry(a)huawei.com>; >tanxiaofei <tanxiaofei(a)huawei.com>; Shameerali Kolothum Thodi ><shameerali.kolothum.thodi(a)huawei.com>; Salil Mehta ><salil.mehta(a)huawei.com> >Subject: Re: [RFC PATCH 1/2] EDAC/ghes: Add EDAC device for the CPU >caches > >On Tue, Dec 08, 2020 at 05:29:58PM +0000, Shiju Jose wrote: >> The corrected error count on the CPU caches required reporting to the >> user-space for the predictive failure analysis. For this purpose, add >> an EDAC device and device blocks for the CPU caches found. >> The cache's corrected error count would be stored in the >> /sys/devices/system/edac/cpu/cpu*/cache*/ce_count. > >This still doesn't begin to explain why the kernel needs this. I had already >asked whether errors in CPU caches are something which happen often >enough so that software should count them but nothing came. So pls justify >first why this wants to be added to the kernel. L2 cache corrected errors are detected occasionally on few of our ARM64 hardware boards. Though it is rare, the probability of the CPU cache errors frequently occurring can't be avoided. The earlier failure detection by monitoring the cache corrected errors for the frequent occurrences and taking preventive action could prevent more serious hardware faults. On Intel architectures, cache corrected errors are reported and the affected cores are offline in the architecture specific method. http://www.mcelog.org/cache.html However for the firmware-first error reporting, specifically on ARM64 architectures, there is no provision present for reporting the cache corrected error count to the user-space and taking preventive action such as offline the affected cores. > >> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index >> 7a47680d6f07..c73eeab27ac9 100644 >> --- a/drivers/edac/Kconfig >> +++ b/drivers/edac/Kconfig >> @@ -74,6 +74,16 @@ config EDAC_GHES >> >> In doubt, say 'Y'. >> >> +config EDAC_GHES_CPU_ERROR >> + bool "EDAC device for reporting firmware-first BIOS detected CPU >error count" > >Why a separate Kconfig item? CONFIG_EDAC_GHES_CPU_CACHE_ERROR is added to make this feature optional only for the platforms which need this and supported. > >> + depends on EDAC_GHES >> + help >> + EDAC device for the firmware-first BIOS detected CPU error count >> +reported > >Well this is not what it is doing - you're talking about cache errors. >"CPU errors" can be a lot more than just cache errors. Sure. I will change. > >> +static void ghes_edac_create_cpu_device(struct device *dev) { >> + int cpu; >> + struct cpu_cacheinfo *this_cpu_ci; >> + >> + /* >> + * Find the maximum number of caches present in the CPU heirarchy >> + * among the online CPUs. >> + */ >> + for_each_online_cpu(cpu) { >> + this_cpu_ci = get_cpu_cacheinfo(cpu); >> + if (!this_cpu_ci) >> + continue; >> + if (max_number_of_caches < this_cpu_ci->num_leaves) >> + max_number_of_caches = this_cpu_ci->num_leaves; > >So this is counting the number of cache levels on the system? So you want to >count the errors per cache levels? Yes. This was the suggestion from James and to offline the affected cores for the shared cache. > >> + } >> + if (!max_number_of_caches) >> + return; >> + >> + /* >> + * EDAC device interface only supports creating the CPU cache >hierarchy for alls >> + * the CPUs together. Thus need to allocate cpu_edac_block_list for >the >> + * max_number_of_caches among all the CPUs irrespective of the >number of caches >> + * per CPU might vary. >> + */ > >So this is lumping all the caches together into a single list? What for? >To untangle to the proper ones when the error gets reported? > >Have you heard of percpu variables? Yes. Changed the list to the percpu variable. > >> @@ -624,6 +787,10 @@ int ghes_edac_register(struct ghes *ghes, struct >device *dev) >> ghes_pvt = pvt; >> spin_unlock_irqrestore(&ghes_lock, flags); >> >> +#if defined(CONFIG_EDAC_GHES_CPU_ERROR) >> + ghes_edac_create_cpu_device(dev); >> +#endif >> + > >Init stuff belongs into ghes_scan_system(). > Did you mean calling ghes_edac_create_cpu_device() in the ghes_scan_system()? >... > >Ok, I've seen enough. "required reporting to the user-space for the predictive >failure analysis." is not even trying to explain *why* you're doing this, what >*actual* problem it is addressing and why should the kernel get it. > >And without a proper problem definition of what you're trying to solve, this >is not going anywhere. > >-- >Regards/Gruss, > Boris. > Thanks, Shiju

2 3

[PATCH mm/zswap 0/2] Fix the compatibility of zsmalloc and zswap
by Tian Tao 19 Jan '21

19 Jan '21

patch #1 add a flag to zpool, then zswap used to determine if zpool drivers such as zbud/z3fold/zsmalloc whether can sleep in atoimc context. patch #2 set flag sleep_mapped to true indicates that zbud/z3fold can sleep in atomic context. zsmalloc didin't support sleep in atomic context, so not set that flag to true. Tian Tao (2): mm/zswap: add the flag can_sleep_mapped mm: set the sleep_mapped to true for zbud and z3fold include/linux/zpool.h | 3 +++ mm/z3fold.c | 1 + mm/zbud.c | 1 + mm/zpool.c | 13 +++++++++++++ mm/zswap.c | 50 +++++++++++++++++++++++++++++++++++++++++++++----- 5 files changed, 63 insertions(+), 5 deletions(-) -- 2.7.4

2 4

[PATCH v2 for-next] RDMA/hns: Create CQ with selected CQN for bank load balance
by Weihang Li 19 Jan '21

19 Jan '21

From: Yangyang Li <liyangyang20(a)huawei.com> In order to improve performance by balancing the load between different banks of cache, the CQC cache is desigend to choose one of 4 banks according to lower 2 bits of CQN. The hns driver needs to count the number of CQ on each bank and then assigns the CQ being created to the bank with the minimum load first. Signed-off-by: Yangyang Li <liyangyang20(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- Changes since v1: - Change GFP_ATOMIC to GFP_KERNEL as there is a chance of memory allocation failure, and change the spin lock to mutex lock because ida_alloc_range() may sleep. - Link: https://patchwork.kernel.org/project/linux-rdma/patch/1609742115-47270-1-gi… drivers/infiniband/hw/hns/hns_roce_cq.c | 115 +++++++++++++++++++++++----- drivers/infiniband/hw/hns/hns_roce_device.h | 10 ++- drivers/infiniband/hw/hns/hns_roce_main.c | 8 +- 3 files changed, 105 insertions(+), 28 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c index 8533fc2..ffb7f7e 100644 --- a/drivers/infiniband/hw/hns/hns_roce_cq.c +++ b/drivers/infiniband/hw/hns/hns_roce_cq.c @@ -38,11 +38,74 @@ #include "hns_roce_hem.h" #include "hns_roce_common.h" +static u8 get_least_load_bankid_for_cq(struct hns_roce_bank *bank) +{ + u32 least_load = bank[0].inuse; + u8 bankid = 0; + u32 bankcnt; + u8 i; + + for (i = 1; i < HNS_ROCE_CQ_BANK_NUM; i++) { + bankcnt = bank[i].inuse; + if (bankcnt < least_load) { + least_load = bankcnt; + bankid = i; + } + } + + return bankid; +} + +static int alloc_cqn(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) +{ + struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; + struct hns_roce_bank *bank; + u8 bankid; + int id; + + mutex_lock(&cq_table->bank_mutex); + bankid = get_least_load_bankid_for_cq(cq_table->bank); + bank = &cq_table->bank[bankid]; + + id = ida_alloc_range(&bank->ida, bank->min, bank->max, GFP_KERNEL); + if (id < 0) { + mutex_unlock(&cq_table->bank_mutex); + return id; + } + + /* the lower 2 bits is bankid */ + hr_cq->cqn = (id << CQ_BANKID_SHIFT) | bankid; + bank->inuse++; + mutex_unlock(&cq_table->bank_mutex); + + return 0; +} + +static inline u8 get_cq_bankid(unsigned long cqn) +{ + /* The lower 2 bits of CQN are used to hash to different banks */ + return (u8)(cqn & GENMASK(1, 0)); +} + +static void free_cqn(struct hns_roce_dev *hr_dev, unsigned long cqn) +{ + struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; + struct hns_roce_bank *bank; + + bank = &cq_table->bank[get_cq_bankid(cqn)]; + + ida_free(&bank->ida, cqn >> CQ_BANKID_SHIFT); + + mutex_lock(&cq_table->bank_mutex); + bank->inuse--; + mutex_unlock(&cq_table->bank_mutex); +} + static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) { + struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; struct ib_device *ibdev = &hr_dev->ib_dev; struct hns_roce_cmd_mailbox *mailbox; - struct hns_roce_cq_table *cq_table; u64 mtts[MTT_MIN_COUNT] = { 0 }; dma_addr_t dma_handle; int ret; @@ -54,13 +117,6 @@ static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) return -EINVAL; } - cq_table = &hr_dev->cq_table; - ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn); - if (ret) { - ibdev_err(ibdev, "failed to alloc CQ bitmap, ret = %d.\n", ret); - return ret; - } - /* Get CQC memory HEM(Hardware Entry Memory) table */ ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn); if (ret) { @@ -110,7 +166,6 @@ static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); err_out: - hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR); return ret; } @@ -138,7 +193,6 @@ static void free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) wait_for_completion(&hr_cq->free); hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); - hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR); } static int alloc_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq, @@ -298,11 +352,17 @@ int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, goto err_cq_buf; } + ret = alloc_cqn(hr_dev, hr_cq); + if (ret) { + ibdev_err(ibdev, "failed to alloc CQN, ret = %d.\n", ret); + goto err_cq_db; + } + ret = alloc_cqc(hr_dev, hr_cq); if (ret) { ibdev_err(ibdev, "failed to alloc CQ context, ret = %d.\n", ret); - goto err_cq_db; + goto err_cqn; } /* @@ -326,6 +386,8 @@ int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, err_cqc: free_cqc(hr_dev, hr_cq); +err_cqn: + free_cqn(hr_dev, hr_cq->cqn); err_cq_db: free_cq_db(hr_dev, hr_cq, udata); err_cq_buf: @@ -341,9 +403,11 @@ int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) if (hr_dev->hw->destroy_cq) hr_dev->hw->destroy_cq(ib_cq, udata); - free_cq_buf(hr_dev, hr_cq); - free_cq_db(hr_dev, hr_cq, udata); free_cqc(hr_dev, hr_cq); + free_cqn(hr_dev, hr_cq->cqn); + free_cq_db(hr_dev, hr_cq, udata); + free_cq_buf(hr_dev, hr_cq); + return 0; } @@ -402,18 +466,33 @@ void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type) complete(&hr_cq->free); } -int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev) +void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev) { struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; + unsigned int reserved_from_bot; + unsigned int i; + mutex_init(&cq_table->bank_mutex); xa_init(&cq_table->array); - return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs, - hr_dev->caps.num_cqs - 1, - hr_dev->caps.reserved_cqs, 0); + reserved_from_bot = hr_dev->caps.reserved_cqs; + + for (i = 0; i < reserved_from_bot; i++) { + cq_table->bank[get_cq_bankid(i)].inuse++; + cq_table->bank[get_cq_bankid(i)].min++; + } + + for (i = 0; i < HNS_ROCE_CQ_BANK_NUM; i++) { + ida_init(&cq_table->bank[i].ida); + cq_table->bank[i].max = hr_dev->caps.num_cqs / + HNS_ROCE_CQ_BANK_NUM - 1; + } } void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev) { - hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap); + int i; + + for (i = 0; i < HNS_ROCE_CQ_BANK_NUM; i++) + ida_destroy(&hr_dev->cq_table.bank[i].ida); } diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 55d5386..c46b330 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -119,6 +119,9 @@ #define SRQ_DB_REG 0x230 #define HNS_ROCE_QP_BANK_NUM 8 +#define HNS_ROCE_CQ_BANK_NUM 4 + +#define CQ_BANKID_SHIFT 2 /* The chip implementation of the consumer index is calculated * according to twice the actual EQ depth @@ -536,9 +539,10 @@ struct hns_roce_qp_table { }; struct hns_roce_cq_table { - struct hns_roce_bitmap bitmap; struct xarray array; struct hns_roce_hem_table table; + struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; + struct mutex bank_mutex; }; struct hns_roce_srq_table { @@ -779,7 +783,7 @@ struct hns_roce_caps { u32 max_cqes; u32 min_cqes; u32 min_wqes; - int reserved_cqs; + u32 reserved_cqs; int reserved_srqs; int num_aeq_vectors; int num_comp_vectors; @@ -1164,7 +1168,7 @@ int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); -int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); +void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c index d9179ba..2b78b1f 100644 --- a/drivers/infiniband/hw/hns/hns_roce_main.c +++ b/drivers/infiniband/hw/hns/hns_roce_main.c @@ -748,11 +748,7 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) goto err_pd_table_free; } - ret = hns_roce_init_cq_table(hr_dev); - if (ret) { - dev_err(dev, "Failed to init completion queue table.\n"); - goto err_mr_table_free; - } + hns_roce_init_cq_table(hr_dev); ret = hns_roce_init_qp_table(hr_dev); if (ret) { @@ -777,8 +773,6 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) err_cq_table_free: hns_roce_cleanup_cq_table(hr_dev); - -err_mr_table_free: hns_roce_cleanup_mr_table(hr_dev); err_pd_table_free: -- 2.8.1

2 1

Re: [PATCH v3 01/22] ethdev: fix MTU size exceeds max rx packet length
by oulijun 18 Jan '21

18 Jan '21

Hi Steve This is a very good job! But I have some question and suggestions. Please check it. 在 2021/1/14 17:45, Steve Yang 写道: > Ethdev is using default Ethernet overhead to decide if provided > 'max_rx_pkt_len' value is bigger than max (non jumbo) MTU value, > and limits it to MAX if it is. > > Since the application/driver used Ethernet overhead is different than > the ethdev one, check result is wrong. > > If the driver is using Ethernet overhead bigger than the default one, > the provided 'max_rx_pkt_len' is trimmed down, and in the driver when > correct Ethernet overhead is used to convert back, the resulting MTU is > less than the intended one, causing some packets to be dropped. > > Like, > app -> max_rx_pkt_len = 1500/*mtu*/ + 22/*overhead*/ = 1522 > ethdev -> 1522 > 1518/*MAX*/; max_rx_pkt_len = 1518 > driver -> MTU = 1518 - 22 = 1496 > Packets with size 1497-1500 are dropped although intention is to be able > to send/receive them. > > The fix is to make ethdev use the correct Ethernet overhead for port, > instead of default one. > > Fixes: 59d0ecdbf0e1 ("ethdev: MTU accessors") > > Signed-off-by: Steve Yang <stevex.yang(a)intel.com> > --- > lib/librte_ethdev/rte_ethdev.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c > index 17ddacc78d..19ca4c4512 100644 > --- a/lib/librte_ethdev/rte_ethdev.c > +++ b/lib/librte_ethdev/rte_ethdev.c > @@ -1292,8 +1292,10 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, > struct rte_eth_dev *dev; > struct rte_eth_dev_info dev_info; > struct rte_eth_conf orig_conf; > + uint16_t overhead_len; > int diag; > int ret; > + uint16_t old_mtu; > > RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); > > @@ -1319,10 +1321,20 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, > memcpy(&dev->data->dev_conf, dev_conf, > sizeof(dev->data->dev_conf)); > > + /* Backup mtu for rollback */ > + old_mtu = dev->data->mtu; > + > ret = rte_eth_dev_info_get(port_id, &dev_info); > if (ret != 0) > goto rollback; > > + /* Get the real Ethernet overhead length */ > + if (dev_info.max_mtu != UINT16_MAX && > + dev_info.max_rx_pktlen > dev_info.max_mtu) > + overhead_len = dev_info.max_rx_pktlen - dev_info.max_mtu; > + else > + overhead_len = RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; > + The Ethernet frame header length supported by each NIC may be different, which cause the difference of allowed packets size and drop you say. The diference of Ethernet frame header length have an impact for the maximum Ethernet frame length, which is a boundary value of enabling jumbo frame through the ' max_rx_pkt_len '. However, we need to do the same thing you do above to get the overhead_len every time, which will cause a lot of duplicate code in the framework and app. For examples, parsing and processing for '--max-pkt-len=xxx' parameter, and " cmd_config_max_pkt_len_parsed " in testpmd, and here modifying here dev_configure API. It's a little redundant and troublesome. Maybe, it is necessary for driver to directly report the supported maximum Ethernet frame length by rte_dev_info_get API. As following: struct rte_eth_dev_info { xxxx /** * The maximum Ethernet frame length supported by each * driver varies with the Ethernet header length. */ uint16_t eth_max_len; xxxx } int rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info) { xxx dev_info->min_mtu = RTE_ETHER_MIN_MTU; dev_info->max_mtu = UINT16_MAX; dev_info->eth_max_len = RTE_ETHER_MAX_LEN; xxx } And then: xxx_devv_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) { xxx info->eth_max_len = xxx_ETHER_MAX _LEN; xxx } What do you think? > /* If number of queues specified by application for both Rx and Tx is > * zero, use driver preferred values. This cannot be done individually > * as it is valid for either Tx or Rx (but not both) to be zero. > @@ -1410,11 +1422,18 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, > goto rollback; > } > } else { > - if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN || > - dev_conf->rxmode.max_rx_pkt_len > RTE_ETHER_MAX_LEN) > + uint16_t pktlen = dev_conf->rxmode.max_rx_pkt_len; > + if (pktlen < RTE_ETHER_MIN_MTU + overhead_len || > + pktlen > RTE_ETHER_MTU + overhead_len) > /* Use default value */ > dev->data->dev_conf.rxmode.max_rx_pkt_len = > - RTE_ETHER_MAX_LEN; > + RTE_ETHER_MTU + overhead_len; > + } > + > + /* Scale the MTU size to adapt max_rx_pkt_len */ > + if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { > + dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - > + overhead_len; > } Now that we update mtu here when jumbo frame enabled. It is necessary to check validity of max_rx_pkt_len. As following: if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen || dev_conf->rxmode.max_rx_pkt_len <= RTE_ETHER_MTU + overhead_len) { xxxx } } else { xxx } If it does not thing above, which will cause an unreasonable case. Like, dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME == 1 dev_conf->rxmode.max_rx_pkt_len = 1500 overhead_len = 26 dev->data->mtu = dev_conf->rxmode.max_rx_pkt_len - overhead_len = 1500 - 26 = 1474 In fact, DEV_RX_OFFLOAD_JUMBO_FRAME is set to rxmode.offloads when mtu > 1500. > > /* > @@ -1549,6 +1568,8 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, > eth_dev_tx_queue_config(dev, 0); > rollback: > memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf)); > + if (old_mtu != dev->data->mtu) > + dev->data->mtu = old_mtu; > > rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, ret); > return ret; >

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[PATCH] maintainers: remove maintainer for hns3
by Lijun Ou 18 Jan '21

18 Jan '21

Because Wei Hu has changed to a new job and the email address(xavier.huwei(a)huawei.com) has expired, we remove him from the hns3 maintainer list. All patches signed-off-by Wei Hu will be copied to Lijun Ou. Signed-off-by: Lijun Ou <oulijun(a)huawei.com> --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 76ed473..7a16af3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -648,7 +648,6 @@ F: doc/guides/nics/enic.rst F: doc/guides/nics/features/enic.ini Hisilicon hns3 -M: Wei Hu (Xavier) <xavier.huwei(a)huawei.com> M: Min Hu (Connor) <humin29(a)huawei.com> M: Yisen Zhuang <yisen.zhuang(a)huawei.com> M: Lijun Ou <oulijun(a)huawei.com> -- 2.7.4

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Re: [PATCH v13 08/15] iommu/smmuv3: Implement cache_invalidate
by chenxiang (M) 16 Jan '21

16 Jan '21

Hi Eric, 在 2020/11/18 19:21, Eric Auger 写道: > Implement domain-selective and page-selective IOTLB invalidations. > > Signed-off-by: Eric Auger <eric.auger(a)redhat.com> > > --- > v7 -> v8: > - ASID based invalidation using iommu_inv_pasid_info > - check ARCHID/PASID flags in addr based invalidation > - use __arm_smmu_tlb_inv_context and __arm_smmu_tlb_inv_range_nosync > > v6 -> v7 > - check the uapi version > > v3 -> v4: > - adapt to changes in the uapi > - add support for leaf parameter > - do not use arm_smmu_tlb_inv_range_nosync or arm_smmu_tlb_inv_context > anymore > > v2 -> v3: > - replace __arm_smmu_tlb_sync by arm_smmu_cmdq_issue_sync > > v1 -> v2: > - properly pass the asid > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 53 +++++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index fdecc9f17b36..24124361dd3b 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2771,6 +2771,58 @@ static void arm_smmu_detach_pasid_table(struct iommu_domain *domain) > mutex_unlock(&smmu_domain->init_mutex); > } > > +static int > +arm_smmu_cache_invalidate(struct iommu_domain *domain, struct device *dev, > + struct iommu_cache_invalidate_info *inv_info) > +{ > + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + if (smmu_domain->stage != ARM_SMMU_DOMAIN_NESTED) > + return -EINVAL; > + > + if (!smmu) > + return -EINVAL; > + > + if (inv_info->version != IOMMU_CACHE_INVALIDATE_INFO_VERSION_1) > + return -EINVAL; > + > + if (inv_info->cache & IOMMU_CACHE_INV_TYPE_IOTLB) { > + if (inv_info->granularity == IOMMU_INV_GRANU_PASID) { > + struct iommu_inv_pasid_info *info = > + &inv_info->granu.pasid_info; > + > + if (!(info->flags & IOMMU_INV_PASID_FLAGS_ARCHID) || > + (info->flags & IOMMU_INV_PASID_FLAGS_PASID)) > + return -EINVAL; > + > + __arm_smmu_tlb_inv_context(smmu_domain, info->archid); > + > + } else if (inv_info->granularity == IOMMU_INV_GRANU_ADDR) { > + struct iommu_inv_addr_info *info = &inv_info->granu.addr_info; > + size_t size = info->nb_granules * info->granule_size; > + bool leaf = info->flags & IOMMU_INV_ADDR_FLAGS_LEAF; > + > + if (!(info->flags & IOMMU_INV_ADDR_FLAGS_ARCHID) || > + (info->flags & IOMMU_INV_ADDR_FLAGS_PASID)) > + return -EINVAL; > + > + __arm_smmu_tlb_inv_range(info->addr, size, > + info->granule_size, leaf, > + smmu_domain, info->archid); When debugging with vSMMU on ARM64 huawei platform, there is a issue: RIL feature is enabled on guest OS while it is not supported on host OS, with some operations (such as rmmod driver during iperf between guest and host), SMMU translation error occurs frequently, and it works well if RIL feature is disabled on guest OS. We find that in function vfio_iommu_unmap_notify() (qemu code) it passes total size of tlb (num_pages * granule_size) as granule size to host OS : addr_info->granules_size = size addr_info->nb_granule = 1 So total size (num_pages * granule_size) is passed as granule size to function __arm_smmu_inv_range(), if RIL feature is not supported, then total size may be not the granule size that host OS can recongize, i will only invalidate part of tlb it wants to invalidate (for example, 4K/2M/1G pagesize is supported on host OS, if total_size = 8K, then addr_info->granule_size = 8K, addr_info->nb_granule = 1, as RIL feature is not supported, it invalidates just 4K one time but it thought it had invalidated 8K). Please have a check of the issue, and we have a temporary fix as follows on the issue. hw/arm/smmuv3.c | 3 ++- hw/vfio/common.c | 6 +++--- include/exec/memory.h | 1 + 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 6725019..891a65d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -821,7 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, entry.target_as = &address_space_memory; entry.iova = iova; - entry.addr_mask = num_pages * (1 << granule) - 1; + entry.addr_mask = (1 << granule) - 1; + entry.num_pages = num_pages; entry.perm = IOMMU_NONE; entry.arch_id = asid; entry.flags = IOMMU_INV_GRANU_ADDR; diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 5d365e0..c0164b1 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -604,7 +604,7 @@ static void vfio_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) hwaddr start = iotlb->iova + giommu->iommu_offset; VFIOContainer *container = giommu->container; struct vfio_iommu_type1_cache_invalidate ustruct = {}; - size_t size = iotlb->addr_mask + 1; + size_t size = iotlb->num_pages * (iotlb->addr_mask + 1); int ret; assert(iotlb->perm == IOMMU_NONE); @@ -632,8 +632,8 @@ static void vfio_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) } addr_info->archid = iotlb->arch_id; addr_info->addr = start; - addr_info->granule_size = size; - addr_info->nb_granules = 1; + addr_info->granule_size = iotlb->addr_mask + 1; + addr_info->nb_granules = iotlb->num_pages; } trace_vfio_iommu_addr_inv_iotlb(iotlb->arch_id, start, size, 1, iotlb->leaf); diff --git a/include/exec/memory.h b/include/exec/memory.h index 21959a7..aa8d43e 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -103,6 +103,7 @@ struct IOMMUTLBEntry { hwaddr iova; hwaddr translated_addr; hwaddr addr_mask; + uint64_t num_pages; IOMMUAccessFlags perm; uint32_t arch_id; uint32_t flags;

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Re: [RESEND PATCH v3 0/4] iommu/iova: Solve longterm IOVA issue
by John Garry 15 Jan '21

15 Jan '21

+ linux-scsi (see https://lore.kernel.org/linux-iommu/1607538189-237944-4-git-send-email-john…) On 17/11/2020 10:25, John Garry wrote: > This series contains a patch to solve the longterm IOVA issue which > leizhen originally tried to address at [0]. > > A sieved kernel log is at the following, showing periodic dumps of IOVA > sizes, per CPU and per depot bin, per IOVA size granule: > https://raw.githubusercontent.com/hisilicon/kernel-dev/topic-iommu-5.10-iov… > > Notice, for example, the following logs: > [13175.355584] print_iova1 cpu_total=40135 depot_total=3866 total=44001 > [83483.457858] print_iova1 cpu_total=62532 depot_total=24476 total=87008 > > Where total IOVA rcache size has grown from 44K->87K over a long time. > JFYI, I am able to reproduce this aging issue on another storage card, an LSI SAS 3008, so now it's harder to say it's an issue specific to a (buggy) single driver. A log of the IOVA size dumps is here: https://raw.githubusercontent.com/hisilicon/kernel-dev/064c4dc8869b3f2ad07e… Notice again how the total IOVA size goes up over time, like: [ 68.176914] print_iova1 cpu_total=23663 depot_total=256 total=23919 [ 2337.008194] print_iova1 cpu_total=67361 depot_total=9088 total=76449 [17141.860078] print_iova1 cpu_total=73397 depot_total=10368 total=83765 [27087.850830] print_iova1 cpu_total=73386 depot_total=10624 total=84010 [10434.042877] print_iova1 cpu_total=90652 depot_total=12928 total=103580 I had to change some settings for that storage card to reproduce, though [0]. Could explain why no other reports. So please consider this issue again... Thanks, john [0] https://lore.kernel.org/linux-scsi/dd8e6fdc-397d-b6ad-3371-0b65d1932ad1@hua… > Along with this patch, I included the following: > - A smaller helper to clear all IOVAs for a domain > - Change polarity of the IOVA magazine helpers > - Small optimisation from Cong Wang included, which was never applied [1]. > There was some debate of the other patches in that series, but this one > is quite straightforward. > > Differnces to v2: > - Update commit message for patch 3/4

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[RFC PATCH] sched/fair: first try to fix the scheduling impact of NUMA diameter > 2
by Barry Song 15 Jan '21

15 Jan '21

This patch is a follow-up of the 3-hops issue reported by Valentin Schneider: [1] https://lore.kernel.org/lkml/jhjtux5edo2.mognet@arm.com/ [2] https://lore.kernel.org/lkml/20201110184300.15673-1-valentin.schneider@arm.… Here is a brief summary of the background: For a NUMA system with 3-hops, sched_group for NUMA 2-hops could be not a subset of sched_domain. For example, for a system with the below topology(two cpus in each NUMA node): node 0 1 2 3 0: 10 12 20 22 1: 12 10 22 24 2: 20 22 10 12 3: 22 24 12 10 For CPU0, domain-2 will span 0-5, but its group will span 0-3, 4-7. 4-7 isn't a subset of 0-5. CPU0 attaching sched-domain(s): domain-0: span=0-1 level=MC groups: 0:{ span=0 cap=989 }, 1:{ span=1 cap=1016 } domain-1: span=0-3 level=NUMA groups: 0:{ span=0-1 cap=2005 }, 2:{ span=2-3 cap=2028 } domain-2: span=0-5 level=NUMA groups: 0:{ span=0-3 cap=4033 }, 4:{ span=4-7 cap=3909 } ERROR: groups don't span domain->span domain-3: span=0-7 level=NUMA groups: 0:{ span=0-5 mask=0-1 cap=6062 }, 6:{ span=4-7 mask=6-7 cap=3928 } All other cpus also have the same issue: sched_group could be not a subset of sched_domain. Here I am trying to figure out the scheduling impact of this issue from two aspects: 1. find busiest cpu in load_balance 2. find idlest cpu in fork/exec/wake balance For case 1, load_balance() seems to be handling this issue correctly as it only fills cpus in sched_domain to the cpus of lb_env. Also, find_busiest_group() and find_busiest_queue() will result in scanning cpus within env.cpus only: static int load_balance(int this_cpu, struct rq *this_rq, struct sched_domain *sd, enum cpu_idle_type idle, int *continue_balancing) {` ... struct lb_env env = { ... .cpus = cpus, .fbq_type = all, .tasks = LIST_HEAD_INIT(env.tasks), }; /* added by barry: only cpus in sched_domain are put in lb_env */ cpumask_and(cpus, sched_domain_span(sd), cpu_active_mask); ... /* * added by barry: the below functions are only scanning cpus * in env.cpus */ group = find_busiest_group(&env); ... busiest = find_busiest_queue(&env, group); ... } But one thing which looks wrong is that update_sg_lb_stats() is only counting tasks in sched_domain, but sgs->group_capacity and sgs->group_weight are counting all cpus in the sched_group. Then finally, update_sg_lb_stats() uses the load of cpus which are in the sched_domain to calculate group_type and avg_load which can be seriously underestimated. This is explained in detail as the comments added by me in the code: static inline void update_sg_lb_stats() { int i, nr_running, local_group; /* added by barry: here it only counts cpu in the sched_domain */ for_each_cpu_and(i, sched_group_span(group), env->cpus) { ... sgs->group_load += cpu_load(rq); sgs->group_util += cpu_util(i); sgs->group_runnable += cpu_runnable(rq); sgs->sum_h_nr_running += rq->cfs.h_nr_running; nr_running = rq->nr_running; sgs->sum_nr_running += nr_running; ... } ... /* added by barry: here it count all cpus which might not be in the domain */ sgs->group_capacity = group->sgc->capacity; sgs->group_weight = group->group_weight; /* added by barry: finally the group_type and avg_load could be wrong */ sgs->group_type = group_classify(env->sd->imbalance_pct, group, sgs); if (sgs->group_type == group_overloaded) sgs->avg_load = (sgs->group_load * SCHED_CAPACITY_SCALE) / sgs->group_capacity; ... } For example, if we have 2 cpus in sched_domain and 4 cpus in sched_group, the code is using the load of 2 cpus to calculate the group_type and avg_load of 4 cpus, the sched_group is likely to get much lower load than the real case. This patch fixed it by only counting cpus within sched_domain for group_capacity and group_weight. For case 2, find_idlest_group() and find_idlest_group_cpu() don't use sched_domain for scanning at all. They are scanning all cpus in the sched_group though sched_group isn't a subset of sched_domain. So they can result in picking an idle cpu outside the sched_domain but inside the sched_group. This patch moved to only scan cpus within the sched_domain, which would be similar with load_balance(). For this moment, this is pretty much PoC code to get feedback. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/sched/fair.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 04a3ce20da67..f183dba4961e 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -5901,7 +5901,7 @@ find_idlest_group(struct sched_domain *sd, struct task_struct *p, int this_cpu); * find_idlest_group_cpu - find the idlest CPU among the CPUs in the group. */ static int -find_idlest_group_cpu(struct sched_group *group, struct task_struct *p, int this_cpu) +find_idlest_group_cpu(struct sched_domain *sd, struct sched_group *group, struct task_struct *p, int this_cpu) { unsigned long load, min_load = ULONG_MAX; unsigned int min_exit_latency = UINT_MAX; @@ -5916,6 +5916,10 @@ find_idlest_group_cpu(struct sched_group *group, struct task_struct *p, int this /* Traverse only the allowed CPUs */ for_each_cpu_and(i, sched_group_span(group), p->cpus_ptr) { + /* when sched_group isn't a subset of sched_domain */ + if (!cpumask_test_cpu(i, sched_domain_span(sd))) + continue; + if (sched_idle_cpu(i)) return i; @@ -5984,7 +5988,7 @@ static inline int find_idlest_cpu(struct sched_domain *sd, struct task_struct *p continue; } - new_cpu = find_idlest_group_cpu(group, p, cpu); + new_cpu = find_idlest_group_cpu(sd, group, p, cpu); if (new_cpu == cpu) { /* Now try balancing at a lower domain level of 'cpu': */ sd = sd->child; @@ -8416,6 +8420,8 @@ static inline void update_sg_lb_stats(struct lb_env *env, if ((env->flags & LBF_NOHZ_STATS) && update_nohz_stats(rq, false)) env->flags |= LBF_NOHZ_AGAIN; + sgs->group_capacity += capacity_of(i); + sgs->group_weight++; sgs->group_load += cpu_load(rq); sgs->group_util += cpu_util(i); sgs->group_runnable += cpu_runnable(rq); @@ -8462,10 +8468,6 @@ static inline void update_sg_lb_stats(struct lb_env *env, sgs->group_asym_packing = 1; } - sgs->group_capacity = group->sgc->capacity; - - sgs->group_weight = group->group_weight; - sgs->group_type = group_classify(env->sd->imbalance_pct, group, sgs); /* Computing avg_load makes sense only when group is overloaded */ @@ -8688,10 +8690,12 @@ static inline void update_sg_wakeup_stats(struct sched_domain *sd, memset(sgs, 0, sizeof(*sgs)); - for_each_cpu(i, sched_group_span(group)) { + for_each_cpu_and(i, sched_group_span(group), sched_domain_span(sd)) { struct rq *rq = cpu_rq(i); unsigned int local; + sgs->group_capacity += capacity_of(i); + sgs->group_weight++; sgs->group_load += cpu_load_without(rq, p); sgs->group_util += cpu_util_without(i, p); sgs->group_runnable += cpu_runnable_without(rq, p); @@ -8715,10 +8719,6 @@ static inline void update_sg_wakeup_stats(struct sched_domain *sd, sgs->group_misfit_task_load = 1; } - sgs->group_capacity = group->sgc->capacity; - - sgs->group_weight = group->group_weight; - sgs->group_type = group_classify(sd->imbalance_pct, group, sgs); /* -- 2.25.1

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[RFC PATCH 0/2] EDAC/ghes: Add EDAC device for recording the CPU cache error count
by Shiju Jose 14 Jan '21

14 Jan '21

ARM64 server chip Kunpeng 920 occasionally detected L2 cache corrected errors on few hardware. Thus the probability of the CPU cache errors occurring often exists. The earlier failure detection by monitoring the cache corrected errors for the frequent occurrences and taking preventive action could prevent more serious hardware faults. For the firmware-first error handling, especially on ARM64 architectures, there is no provision for recording the CPU cache corrected error count is present. For Intel architectures cache corrected errors reporting and offline the cores is done through more architecture specific method. http://www.mcelog.org/cache.html For this purpose, the suggestion was to create the CPU EDAC device for the CPU caches for recording the cache error count. The EDAC device blocks for the CPU caches would be created based on the cache information obtained from the cpu_cacheinfo. User-space application could monitor the recorded corrected error count for the earlier hardware failure detection and could take preventive action. Changes: RFC V1 -> RFC V2: 1. Fixed feedback by Boris. 1.1. Added reason of this patch. 1.2. Changed CPU errors to CPU cache errors in the drivers/edac/Kconfig 1.3 Changed EDAC cache list to percpu variables. 2. Changes in the descriptions. Shiju Jose (2): EDAC/ghes: Add EDAC device for reporting the CPU cache errors ACPI / APEI: Add reporting ARM64 CPU cache corrected error count Documentation/ABI/testing/sysfs-devices-edac | 15 ++ drivers/acpi/apei/ghes.c | 76 +++++++- drivers/edac/Kconfig | 10 + drivers/edac/ghes_edac.c | 181 +++++++++++++++++++ include/acpi/ghes.h | 27 +++ include/linux/cper.h | 4 + 6 files changed, 309 insertions(+), 4 deletions(-) -- 2.17.1

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[PATCH v2] input - mk712: remove the driver as it is obsolete and causes kernel crash
by Barry Song 13 Jan '21

13 Jan '21

While debugging other issues, I enabled mk712 then I got the below crash during arm64 linux boot: [ 1.150412] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO BTYPE=--) [ 1.150541] pc : logic_outb+0x3c/0xa8 [ 1.150657] lr : mk712_init+0x74/0x1ec [ 1.150745] sp : ffff800011efbd40 [ 1.150950] x29: ffff800011efbd40 x28: 0000000000000000 [ 1.151098] x27: ffff800011681078 x26: ffff8000115d04b8 [ 1.151192] x25: ffff8000116ff6b4 x24: ffff8000115bac10 [ 1.151287] x23: ffff800011dfa000 x22: ffff800011b8dbe0 [ 1.151421] x21: ffff800011eac000 x20: 0000000000000000 [ 1.151527] x19: fffffbfffe800266 x18: 0000000000000000 [ 1.151674] x17: ffff800010a7bc38 x16: ffff800010a7b0e0 [ 1.151944] x15: 0000a0d665e7ee58 x14: 000000000000011a [ 1.152060] x13: 0000000000000001 x12: 0000000000000000 [ 1.152149] x11: 0000000000000000 x10: 0000000000000a60 [ 1.152291] x9 : 0000000000000000 x8 : ffff0000c0a2a480 [ 1.152429] x7 : 0000000000000000 x6 : ffff0000c0b0c9b8 [ 1.152522] x5 : 0000000000001000 x4 : ffff0000c03613b0 [ 1.152614] x3 : 0000000000000267 x2 : 0000000000000260 [ 1.152731] x1 : fffffbfffe800000 x0 : 0000000000ffbffe [ 1.153135] Call trace: [ 1.153342] logic_outb+0x3c/0xa8 [ 1.153434] mk712_init+0x74/0x1ec [ 1.153571] do_one_initcall+0x54/0x1b8 [ 1.153705] kernel_init_freeable+0x1d0/0x238 [ 1.153860] kernel_init+0x14/0x118 [ 1.153960] ret_from_fork+0x10/0x30 [ 1.154304] Code: d2bfd001 f2df7fe1 f2ffffe1 8b010273 (39000274) [ 1.155013] ---[ end trace f9b157c311d20edd ]--- [ 1.155854] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 1.156236] SMP: stopping secondary CPUs The driver is very old and resources are totally hardcoded, no bus model. And it seems there is no way to stop users from enabling it in Kconfig. Plus, it is likely that there is no "Gateway AOL Connected Touchpad computers" running 5.x kernel any more. So remove this driver. Cc: Daniel Quinlan <quinlan(a)pathname.com> Cc: Vojtech Pavlik <vojtech(a)suse.cz> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- drivers/input/touchscreen/Kconfig | 11 -- drivers/input/touchscreen/Makefile | 1 - drivers/input/touchscreen/mk712.c | 215 ----------------------------- 3 files changed, 227 deletions(-) delete mode 100644 drivers/input/touchscreen/mk712.c diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index cc18f54ea887..0638ec5d1bd7 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -630,17 +630,6 @@ config TOUCHSCREEN_INEXIO To compile this driver as a module, choose M here: the module will be called inexio. -config TOUCHSCREEN_MK712 - tristate "ICS MicroClock MK712 touchscreen" - help - Say Y here if you have the ICS MicroClock MK712 touchscreen - controller chip in your system. - - If unsure, say N. - - To compile this driver as a module, choose M here: the - module will be called mk712. - config TOUCHSCREEN_HP600 tristate "HP Jornada 6xx touchscreen" depends on SH_HP6XX && SH_ADC diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 6233541e9173..75a60b8282b4 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -60,7 +60,6 @@ obj-$(CONFIG_TOUCHSCREEN_MELFAS_MIP4) += melfas_mip4.o obj-$(CONFIG_TOUCHSCREEN_MIGOR) += migor_ts.o obj-$(CONFIG_TOUCHSCREEN_MMS114) += mms114.o obj-$(CONFIG_TOUCHSCREEN_MTOUCH) += mtouch.o -obj-$(CONFIG_TOUCHSCREEN_MK712) += mk712.o obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o obj-$(CONFIG_TOUCHSCREEN_HP7XX) += jornada720_ts.o obj-$(CONFIG_TOUCHSCREEN_IPAQ_MICRO) += ipaq-micro-ts.o diff --git a/drivers/input/touchscreen/mk712.c b/drivers/input/touchscreen/mk712.c deleted file mode 100644 index 753d9cc1de1f..000000000000 --- a/drivers/input/touchscreen/mk712.c +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ICS MK712 touchscreen controller driver - * - * Copyright (c) 1999-2002 Transmeta Corporation - * Copyright (c) 2005 Rick Koch <n1gp(a)hotmail.com> - * Copyright (c) 2005 Vojtech Pavlik <vojtech(a)suse.cz> - */ - - -/* - * This driver supports the ICS MicroClock MK712 TouchScreen controller, - * found in Gateway AOL Connected Touchpad computers. - * - * Documentation for ICS MK712 can be found at: - * https://www.idt.com/general-parts/mk712-touch-screen-controller - */ - -/* - * 1999-12-18: original version, Daniel Quinlan - * 1999-12-19: added anti-jitter code, report pen-up events, fixed mk712_poll - * to use queue_empty, Nathan Laredo - * 1999-12-20: improved random point rejection, Nathan Laredo - * 2000-01-05: checked in new anti-jitter code, changed mouse protocol, fixed - * queue code, added module options, other fixes, Daniel Quinlan - * 2002-03-15: Clean up for kernel merge <alan(a)redhat.com> - * Fixed multi open race, fixed memory checks, fixed resource - * allocation, fixed close/powerdown bug, switched to new init - * 2005-01-18: Ported to 2.6 from 2.4.28, Rick Koch - * 2005-02-05: Rewritten for the input layer, Vojtech Pavlik - * - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/delay.h> -#include <linux/ioport.h> -#include <linux/interrupt.h> -#include <linux/input.h> -#include <asm/io.h> - -MODULE_AUTHOR("Daniel Quinlan <quinlan(a)pathname.com>, Vojtech Pavlik <vojtech(a)suse.cz>"); -MODULE_DESCRIPTION("ICS MicroClock MK712 TouchScreen driver"); -MODULE_LICENSE("GPL"); - -static unsigned int mk712_io = 0x260; /* Also 0x200, 0x208, 0x300 */ -module_param_hw_named(io, mk712_io, uint, ioport, 0); -MODULE_PARM_DESC(io, "I/O base address of MK712 touchscreen controller"); - -static unsigned int mk712_irq = 10; /* Also 12, 14, 15 */ -module_param_hw_named(irq, mk712_irq, uint, irq, 0); -MODULE_PARM_DESC(irq, "IRQ of MK712 touchscreen controller"); - -/* eight 8-bit registers */ -#define MK712_STATUS 0 -#define MK712_X 2 -#define MK712_Y 4 -#define MK712_CONTROL 6 -#define MK712_RATE 7 - -/* status */ -#define MK712_STATUS_TOUCH 0x10 -#define MK712_CONVERSION_COMPLETE 0x80 - -/* control */ -#define MK712_ENABLE_INT 0x01 -#define MK712_INT_ON_CONVERSION_COMPLETE 0x02 -#define MK712_INT_ON_CHANGE_IN_TOUCH_STATUS 0x04 -#define MK712_ENABLE_PERIODIC_CONVERSIONS 0x10 -#define MK712_READ_ONE_POINT 0x20 -#define MK712_POWERUP 0x40 - -static struct input_dev *mk712_dev; -static DEFINE_SPINLOCK(mk712_lock); - -static irqreturn_t mk712_interrupt(int irq, void *dev_id) -{ - unsigned char status; - static int debounce = 1; - static unsigned short last_x; - static unsigned short last_y; - - spin_lock(&mk712_lock); - - status = inb(mk712_io + MK712_STATUS); - - if (~status & MK712_CONVERSION_COMPLETE) { - debounce = 1; - goto end; - } - - if (~status & MK712_STATUS_TOUCH) { - debounce = 1; - input_report_key(mk712_dev, BTN_TOUCH, 0); - goto end; - } - - if (debounce) { - debounce = 0; - goto end; - } - - input_report_key(mk712_dev, BTN_TOUCH, 1); - input_report_abs(mk712_dev, ABS_X, last_x); - input_report_abs(mk712_dev, ABS_Y, last_y); - - end: - last_x = inw(mk712_io + MK712_X) & 0x0fff; - last_y = inw(mk712_io + MK712_Y) & 0x0fff; - input_sync(mk712_dev); - spin_unlock(&mk712_lock); - return IRQ_HANDLED; -} - -static int mk712_open(struct input_dev *dev) -{ - unsigned long flags; - - spin_lock_irqsave(&mk712_lock, flags); - - outb(0, mk712_io + MK712_CONTROL); /* Reset */ - - outb(MK712_ENABLE_INT | MK712_INT_ON_CONVERSION_COMPLETE | - MK712_INT_ON_CHANGE_IN_TOUCH_STATUS | - MK712_ENABLE_PERIODIC_CONVERSIONS | - MK712_POWERUP, mk712_io + MK712_CONTROL); - - outb(10, mk712_io + MK712_RATE); /* 187 points per second */ - - spin_unlock_irqrestore(&mk712_lock, flags); - - return 0; -} - -static void mk712_close(struct input_dev *dev) -{ - unsigned long flags; - - spin_lock_irqsave(&mk712_lock, flags); - - outb(0, mk712_io + MK712_CONTROL); - - spin_unlock_irqrestore(&mk712_lock, flags); -} - -static int __init mk712_init(void) -{ - int err; - - if (!request_region(mk712_io, 8, "mk712")) { - printk(KERN_WARNING "mk712: unable to get IO region\n"); - return -ENODEV; - } - - outb(0, mk712_io + MK712_CONTROL); - - if ((inw(mk712_io + MK712_X) & 0xf000) || /* Sanity check */ - (inw(mk712_io + MK712_Y) & 0xf000) || - (inw(mk712_io + MK712_STATUS) & 0xf333)) { - printk(KERN_WARNING "mk712: device not present\n"); - err = -ENODEV; - goto fail1; - } - - mk712_dev = input_allocate_device(); - if (!mk712_dev) { - printk(KERN_ERR "mk712: not enough memory\n"); - err = -ENOMEM; - goto fail1; - } - - mk712_dev->name = "ICS MicroClock MK712 TouchScreen"; - mk712_dev->phys = "isa0260/input0"; - mk712_dev->id.bustype = BUS_ISA; - mk712_dev->id.vendor = 0x0005; - mk712_dev->id.product = 0x0001; - mk712_dev->id.version = 0x0100; - - mk712_dev->open = mk712_open; - mk712_dev->close = mk712_close; - - mk712_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); - mk712_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); - input_set_abs_params(mk712_dev, ABS_X, 0, 0xfff, 88, 0); - input_set_abs_params(mk712_dev, ABS_Y, 0, 0xfff, 88, 0); - - if (request_irq(mk712_irq, mk712_interrupt, 0, "mk712", mk712_dev)) { - printk(KERN_WARNING "mk712: unable to get IRQ\n"); - err = -EBUSY; - goto fail1; - } - - err = input_register_device(mk712_dev); - if (err) - goto fail2; - - return 0; - - fail2: free_irq(mk712_irq, mk712_dev); - fail1: input_free_device(mk712_dev); - release_region(mk712_io, 8); - return err; -} - -static void __exit mk712_exit(void) -{ - input_unregister_device(mk712_dev); - free_irq(mk712_irq, mk712_dev); - release_region(mk712_io, 8); -} - -module_init(mk712_init); -module_exit(mk712_exit); -- 2.25.1

3 3

[PATCH 0/2] hisi_sas: Expose hw queues for v2 hw and remove unused code
by John Garry 13 Jan '21

13 Jan '21

Patch "scsi: hisi_sas: Expose HW queues for v2 hw" was not merged for v5.11, so resending for v5.12. Unused module param auto_affine_msi_experimental for v3 hw is also removed in the other patch. John Garry (2): scsi: hisi_sas: Remove auto_affine_msi_experimental module_param scsi: hisi_sas: Expose HW queues for v2 hw drivers/scsi/hisi_sas/hisi_sas.h | 4 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 11 +++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 66 +++++++++++++++++++++----- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 5 -- 4 files changed, 68 insertions(+), 18 deletions(-) -- 2.26.2

2 5

[RFC PATCH 0/2] EDAC/ghes: Add EDAC device for recording the CPU cache error count
by Shiju Jose 12 Jan '21

12 Jan '21

ARM64 server chip Kunpeng 920 occasionally detected L2 cache corrected errors on few hardware. Thus CPU cache errors seems not uncommon. The earlier failure detection by monitoring the cache corrected errors and taking preventive action could prevent more serious hardware failures. For the firmware-first error handling on ARM64 hardware platforms, CPU cache corrected error count is not recorded. For this purpose, the suggestion was to create an CPU EDAC device and device blocks for the CPU caches. The EDAC device blocks would be created based on the cache information obtained from the cpu_cacheinfo. User-space application could monitor the recorded corrected error count for the earlier hardware failure detection and could take preventive action. Changes: RFC V1 -> RFC V2: 1. Fixed feedback by Boris. 1.1. Added reason of this patch. 1.2. Changed CPU errors to CPU cache errors in the drivers/edac/Kconfig 1.3 Changed EDAC cache list to percpu variables. 2. Changes in the descriptions. Shiju Jose (2): EDAC/ghes: Add EDAC device for reporting the CPU cache errors ACPI / APEI: Add reporting ARM64 CPU cache corrected error count Documentation/ABI/testing/sysfs-devices-edac | 15 ++ drivers/acpi/apei/ghes.c | 76 +++++++- drivers/edac/Kconfig | 10 + drivers/edac/ghes_edac.c | 181 +++++++++++++++++++ include/acpi/ghes.h | 27 +++ include/linux/cper.h | 4 + 6 files changed, 309 insertions(+), 4 deletions(-) -- 2.17.1

1 2

[PATCH] input - mk712: fix the kernel crash while mk712 is selected
by Barry Song 12 Jan '21

12 Jan '21

While debugging other issues, I enabled mk712 then I got the below crash during arm64 linux boot: [ 1.150412] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO BTYPE=--) [ 1.150541] pc : logic_outb+0x3c/0xa8 [ 1.150657] lr : mk712_init+0x74/0x1ec [ 1.150745] sp : ffff800011efbd40 [ 1.150950] x29: ffff800011efbd40 x28: 0000000000000000 [ 1.151098] x27: ffff800011681078 x26: ffff8000115d04b8 [ 1.151192] x25: ffff8000116ff6b4 x24: ffff8000115bac10 [ 1.151287] x23: ffff800011dfa000 x22: ffff800011b8dbe0 [ 1.151421] x21: ffff800011eac000 x20: 0000000000000000 [ 1.151527] x19: fffffbfffe800266 x18: 0000000000000000 [ 1.151674] x17: ffff800010a7bc38 x16: ffff800010a7b0e0 [ 1.151944] x15: 0000a0d665e7ee58 x14: 000000000000011a [ 1.152060] x13: 0000000000000001 x12: 0000000000000000 [ 1.152149] x11: 0000000000000000 x10: 0000000000000a60 [ 1.152291] x9 : 0000000000000000 x8 : ffff0000c0a2a480 [ 1.152429] x7 : 0000000000000000 x6 : ffff0000c0b0c9b8 [ 1.152522] x5 : 0000000000001000 x4 : ffff0000c03613b0 [ 1.152614] x3 : 0000000000000267 x2 : 0000000000000260 [ 1.152731] x1 : fffffbfffe800000 x0 : 0000000000ffbffe [ 1.153135] Call trace: [ 1.153342] logic_outb+0x3c/0xa8 [ 1.153434] mk712_init+0x74/0x1ec [ 1.153571] do_one_initcall+0x54/0x1b8 [ 1.153705] kernel_init_freeable+0x1d0/0x238 [ 1.153860] kernel_init+0x14/0x118 [ 1.153960] ret_from_fork+0x10/0x30 [ 1.154304] Code: d2bfd001 f2df7fe1 f2ffffe1 8b010273 (39000274) [ 1.155013] ---[ end trace f9b157c311d20edd ]--- [ 1.155854] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 1.156236] SMP: stopping secondary CPUs The driver is very old and resources are totally hardcoded, no bus model. It seems the simplest way to fix this issue is disabling it by parameter. If someone really needs the old driver, it should enable the parameter by cmdline. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- drivers/input/touchscreen/mk712.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/input/touchscreen/mk712.c b/drivers/input/touchscreen/mk712.c index 753d9cc1de1f..8a3110f27ce7 100644 --- a/drivers/input/touchscreen/mk712.c +++ b/drivers/input/touchscreen/mk712.c @@ -53,6 +53,9 @@ static unsigned int mk712_irq = 10; /* Also 12, 14, 15 */ module_param_hw_named(irq, mk712_irq, uint, irq, 0); MODULE_PARM_DESC(irq, "IRQ of MK712 touchscreen controller"); +static bool mk712_enabled; +module_param(mk712_enabled, bool, 0); + /* eight 8-bit registers */ #define MK712_STATUS 0 #define MK712_X 2 @@ -149,6 +152,11 @@ static int __init mk712_init(void) { int err; + if (!mk712_enabled) { + printk(KERN_WARNING "mk712: device is not enabled\n"); + return -ENODEV; + } + if (!request_region(mk712_io, 8, "mk712")) { printk(KERN_WARNING "mk712: unable to get IO region\n"); return -ENODEV; -- 2.25.1

3 2

Re: [PATCH 2/2] KVM: arm64: Workaround firmware wrongly advertising GICv2-on-v3 compatibility
by Shameerali Kolothum Thodi 11 Jan '21

11 Jan '21

Hi Marc, > -----Original Message----- > From: Marc Zyngier [mailto:maz@kernel.org] > Sent: 08 January 2021 17:12 > To: linux-arm-kernel(a)lists.infradead.org; kvmarm(a)lists.cs.columbia.edu > Cc: Shameerali Kolothum Thodi <shameerali.kolothum.thodi(a)huawei.com>; > James Morse <james.morse(a)arm.com>; Julien Thierry > <julien.thierry.kdev(a)gmail.com>; Suzuki K Poulose > <suzuki.poulose(a)arm.com>; Ard Biesheuvel <ardb(a)kernel.org>; > kernel-team(a)android.com > Subject: [PATCH 2/2] KVM: arm64: Workaround firmware wrongly advertising > GICv2-on-v3 compatibility > > It looks like we have broken firmware out there that wrongly advertises > a GICv2 compatibility interface, despite the CPUs not being able to deal > with it. > > To work around this, check that the CPU initialising KVM is actually able > to switch to MMIO instead of system registers, and use that as a > precondition to enable GICv2 compatibility in KVM. > > Note that the detection happens on a single CPU. If the firmware is > lying *and* that the CPUs are asymetric, all hope is lost anyway. > > Reported-by: Shameerali Kolothum Thodi > <shameerali.kolothum.thodi(a)huawei.com> > Signed-off-by: Marc Zyngier <maz(a)kernel.org> > --- > arch/arm64/kvm/hyp/vgic-v3-sr.c | 34 +++++++++++++++++++++++++++++++-- > arch/arm64/kvm/vgic/vgic-v3.c | 8 ++++++-- > 2 files changed, 38 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c > b/arch/arm64/kvm/hyp/vgic-v3-sr.c > index 005daa0c9dd7..d504499ab917 100644 > --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c > +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c > @@ -408,11 +408,41 @@ void __vgic_v3_init_lrs(void) > /* > * Return the GIC CPU configuration: > * - [31:0] ICH_VTR_EL2 > - * - [63:32] RES0 > + * - [62:32] RES0 > + * - [63] MMIO (GICv2) capable > */ > u64 __vgic_v3_get_gic_config(void) > { > - return read_gicreg(ICH_VTR_EL2); > + u64 sre = read_gicreg(ICC_SRE_EL1); > + unsigned long flags = 0; > + bool v2_capable; > + > + /* > + * To check whether we have a MMIO-based (GICv2 compatible) > + * CPU interface, we need to disable the system register > + * view. To do that safely, we have to prevent any interrupt > + * from firing (which would be deadly). > + * > + * Note that this only makes sense on VHE, as interrupts are > + * already masked for nVHE as part of the exception entry to > + * EL2. > + */ > + if (has_vhe()) > + flags = local_daif_save(); > + > + write_gicreg(0, ICC_SRE_EL1); > + isb(); > + > + v2_capable = !(read_gicreg(ICC_SRE_EL1) & ICC_SRE_EL1_SRE); > + > + write_gicreg(sre, ICC_SRE_EL1); > + isb(); > + > + if (has_vhe()) > + local_daif_restore(flags); > + > + return (read_gicreg(ICH_VTR_EL2) | > + v2_capable ? (1ULL << 63) : 0); > } Thanks for sending this out. I had a go with this series and unfortunately it didn't work on a system with faulty BIOS. It looks like the culprit here is the ?: operator. There seems to be an operator precedence at play here and it returns, vgic_v3_probe: ich_vtr_el2 0x8000000000000000 And with the below change, return (read_gicreg(ICH_VTR_EL2) | - v2_capable ? (1ULL << 63) : 0); + (v2_capable ? (1ULL << 63) : 0)); } It returns, vgic_v3_probe: ich_vtr_el2 0x90080003 and works correctly. [ 18.918738] kvm [1]: disabling GICv2 emulation Thanks, Shameer > u64 __vgic_v3_read_vmcr(void) > diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c > index 8e7bf3151057..67b27b47312b 100644 > --- a/arch/arm64/kvm/vgic/vgic-v3.c > +++ b/arch/arm64/kvm/vgic/vgic-v3.c > @@ -584,8 +584,10 @@ early_param("kvm-arm.vgic_v4_enable", > early_gicv4_enable); > int vgic_v3_probe(const struct gic_kvm_info *info) > { > u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config); > + bool has_v2; > int ret; > > + has_v2 = ich_vtr_el2 >> 63; > ich_vtr_el2 = (u32)ich_vtr_el2; > > /* > @@ -605,13 +607,15 @@ int vgic_v3_probe(const struct gic_kvm_info *info) > gicv4_enable ? "en" : "dis"); > } > > + kvm_vgic_global_state.vcpu_base = 0; > + > if (!info->vcpu.start) { > kvm_info("GICv3: no GICV resource entry\n"); > - kvm_vgic_global_state.vcpu_base = 0; > + } else if (!has_v2) { > + pr_warn("CPU interface incapable of MMIO access\n"); > } else if (!PAGE_ALIGNED(info->vcpu.start)) { > pr_warn("GICV physical address 0x%llx not page aligned\n", > (unsigned long long)info->vcpu.start); > - kvm_vgic_global_state.vcpu_base = 0; > } else { > kvm_vgic_global_state.vcpu_base = info->vcpu.start; > kvm_vgic_global_state.can_emulate_gicv2 = true; > -- > 2.29.2

2 1

Re: [PATCH v11 12/13] vfio/pci: Register a DMA fault response region
by Shameerali Kolothum Thodi 08 Jan '21

08 Jan '21

Hi Eric, > -----Original Message----- > From: Eric Auger [mailto:eric.auger@redhat.com] > Sent: 16 November 2020 11:00 > To: eric.auger.pro(a)gmail.com; eric.auger(a)redhat.com; > iommu(a)lists.linux-foundation.org; linux-kernel(a)vger.kernel.org; > kvm(a)vger.kernel.org; kvmarm(a)lists.cs.columbia.edu; will(a)kernel.org; > joro(a)8bytes.org; maz(a)kernel.org; robin.murphy(a)arm.com; > alex.williamson(a)redhat.com > Cc: jean-philippe(a)linaro.org; zhangfei.gao(a)linaro.org; > zhangfei.gao(a)gmail.com; vivek.gautam(a)arm.com; Shameerali Kolothum > Thodi <shameerali.kolothum.thodi(a)huawei.com>; > jacob.jun.pan(a)linux.intel.com; yi.l.liu(a)intel.com; tn(a)semihalf.com; > nicoleotsuka(a)gmail.com; yuzenghui <yuzenghui(a)huawei.com> > Subject: [PATCH v11 12/13] vfio/pci: Register a DMA fault response region > > In preparation for vSVA, let's register a DMA fault response region, > where the userspace will push the page responses and increment the > head of the buffer. The kernel will pop those responses and inject them > on iommu side. > > Signed-off-by: Eric Auger <eric.auger(a)redhat.com> > --- > drivers/vfio/pci/vfio_pci.c | 114 +++++++++++++++++++++++++--- > drivers/vfio/pci/vfio_pci_private.h | 5 ++ > drivers/vfio/pci/vfio_pci_rdwr.c | 39 ++++++++++ > include/uapi/linux/vfio.h | 32 ++++++++ > 4 files changed, 181 insertions(+), 9 deletions(-) > > diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c > index 65a83fd0e8c0..e9a904ce3f0d 100644 > --- a/drivers/vfio/pci/vfio_pci.c > +++ b/drivers/vfio/pci/vfio_pci.c > @@ -318,9 +318,20 @@ static void vfio_pci_dma_fault_release(struct > vfio_pci_device *vdev, > kfree(vdev->fault_pages); > } > > -static int vfio_pci_dma_fault_mmap(struct vfio_pci_device *vdev, > - struct vfio_pci_region *region, > - struct vm_area_struct *vma) > +static void > +vfio_pci_dma_fault_response_release(struct vfio_pci_device *vdev, > + struct vfio_pci_region *region) > +{ > + if (vdev->dma_fault_response_wq) > + destroy_workqueue(vdev->dma_fault_response_wq); > + kfree(vdev->fault_response_pages); > + vdev->fault_response_pages = NULL; > +} > + > +static int __vfio_pci_dma_fault_mmap(struct vfio_pci_device *vdev, > + struct vfio_pci_region *region, > + struct vm_area_struct *vma, > + u8 *pages) > { > u64 phys_len, req_len, pgoff, req_start; > unsigned long long addr; > @@ -333,14 +344,14 @@ static int vfio_pci_dma_fault_mmap(struct > vfio_pci_device *vdev, > ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); > req_start = pgoff << PAGE_SHIFT; > > - /* only the second page of the producer fault region is mmappable */ > + /* only the second page of the fault region is mmappable */ > if (req_start < PAGE_SIZE) > return -EINVAL; > > if (req_start + req_len > phys_len) > return -EINVAL; > > - addr = virt_to_phys(vdev->fault_pages); > + addr = virt_to_phys(pages); > vma->vm_private_data = vdev; > vma->vm_pgoff = (addr >> PAGE_SHIFT) + pgoff; > > @@ -349,13 +360,29 @@ static int vfio_pci_dma_fault_mmap(struct > vfio_pci_device *vdev, > return ret; > } > > -static int vfio_pci_dma_fault_add_capability(struct vfio_pci_device *vdev, > - struct vfio_pci_region *region, > - struct vfio_info_cap *caps) > +static int vfio_pci_dma_fault_mmap(struct vfio_pci_device *vdev, > + struct vfio_pci_region *region, > + struct vm_area_struct *vma) > +{ > + return __vfio_pci_dma_fault_mmap(vdev, region, vma, > vdev->fault_pages); > +} > + > +static int > +vfio_pci_dma_fault_response_mmap(struct vfio_pci_device *vdev, > + struct vfio_pci_region *region, > + struct vm_area_struct *vma) > +{ > + return __vfio_pci_dma_fault_mmap(vdev, region, vma, > vdev->fault_response_pages); > +} > + > +static int __vfio_pci_dma_fault_add_capability(struct vfio_pci_device *vdev, > + struct vfio_pci_region *region, > + struct vfio_info_cap *caps, > + u32 cap_id) > { > struct vfio_region_info_cap_sparse_mmap *sparse = NULL; > struct vfio_region_info_cap_fault cap = { > - .header.id = VFIO_REGION_INFO_CAP_DMA_FAULT, > + .header.id = cap_id, > .header.version = 1, > .version = 1, > }; > @@ -383,6 +410,14 @@ static int vfio_pci_dma_fault_add_capability(struct > vfio_pci_device *vdev, > return ret; > } > > +static int vfio_pci_dma_fault_add_capability(struct vfio_pci_device *vdev, > + struct vfio_pci_region *region, > + struct vfio_info_cap *caps) > +{ > + return __vfio_pci_dma_fault_add_capability(vdev, region, caps, > + VFIO_REGION_INFO_CAP_DMA_FAULT); > +} > + > static const struct vfio_pci_regops vfio_pci_dma_fault_regops = { > .rw = vfio_pci_dma_fault_rw, > .release = vfio_pci_dma_fault_release, > @@ -390,6 +425,13 @@ static const struct vfio_pci_regops > vfio_pci_dma_fault_regops = { > .add_capability = vfio_pci_dma_fault_add_capability, > }; > > +static const struct vfio_pci_regops vfio_pci_dma_fault_response_regops = { > + .rw = vfio_pci_dma_fault_response_rw, > + .release = vfio_pci_dma_fault_response_release, > + .mmap = vfio_pci_dma_fault_response_mmap, > + .add_capability = vfio_pci_dma_fault_add_capability, > +}; > + > int vfio_pci_iommu_dev_fault_handler(struct iommu_fault *fault, void *data) > { > struct vfio_pci_device *vdev = (struct vfio_pci_device *)data; > @@ -500,6 +542,55 @@ static int vfio_pci_dma_fault_init(struct > vfio_pci_device *vdev) > return ret; > } > > +#define DMA_FAULT_RESPONSE_RING_LENGTH 512 > + > +static int vfio_pci_dma_fault_response_init(struct vfio_pci_device *vdev) > +{ > + struct vfio_region_dma_fault_response *header; > + struct iommu_domain *domain; > + size_t size; > + bool nested; > + int ret; > + > + domain = iommu_get_domain_for_dev(&vdev->pdev->dev); > + ret = iommu_domain_get_attr(domain, DOMAIN_ATTR_NESTING, > &nested); The above will fail((Thanks to Zengtao for reporting this) if the Guest is booted in "enable_unsafe_noiommu_mode" (CONFIG_VFIO_NOIOMMU) and dpdk testpmd is attempted. This is because even though there is an iommu group created for this mode, no iommu domain gets attached to it. And results in below crash, root@ubuntu:/mnt/dpdk/build/app# ./testpmd -w 0000:00:02.0 --file-prefix socket0 -l 0-1 -n 2 -- -i EAL: Detected 8 lcore(s) EAL: Detected 1 NUMA nodes EAL: Multi-process socket /var/run/dpdk/socket0/mp_socket EAL: Selected IOVA mode 'PA' EAL: No available hugepages reported in hugepages-32768kB EAL: No available hugepages reported in hugepages-64kB EAL: No available hugepages reported in hugepages-1048576kB EAL: Probing VFIO support... EAL: VFIO support initialized EAL: Invalid NUMA socket, default to 0 EAL: using IOMMU type 8 (No-IOMMU) [ 84.942213] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000008 [ 84.943047] Mem abort info: --- I have pushed a temp fix for this in my test branch here, https://github.com/hisilicon/kernel-dev/commit/7784d96fbac9c48e8093ec9dbf43… Please take a look. (I am seeing another issue with testpmd + vsmmu. I will explain that in another thread). Thanks, Shameer > + if (ret || !nested) > + return ret; > + > + mutex_init(&vdev->fault_response_queue_lock); > + > + /* > + * We provision 1 page for the header and space for > + * DMA_FAULT_RING_LENGTH fault records in the ring buffer. > + */ > + size = ALIGN(sizeof(struct iommu_page_response) * > + DMA_FAULT_RESPONSE_RING_LENGTH, PAGE_SIZE) + > PAGE_SIZE; > + > + vdev->fault_response_pages = kzalloc(size, GFP_KERNEL); > + if (!vdev->fault_response_pages) > + return -ENOMEM; > + > + ret = vfio_pci_register_dev_region(vdev, > + VFIO_REGION_TYPE_NESTED, > + VFIO_REGION_SUBTYPE_NESTED_DMA_FAULT_RESPONSE, > + &vfio_pci_dma_fault_response_regops, size, > + VFIO_REGION_INFO_FLAG_READ | > VFIO_REGION_INFO_FLAG_WRITE | > + VFIO_REGION_INFO_FLAG_MMAP, > + vdev->fault_response_pages); > + if (ret) > + goto out; > + > + header = (struct vfio_region_dma_fault_response > *)vdev->fault_response_pages; > + header->entry_size = sizeof(struct iommu_page_response); > + header->nb_entries = DMA_FAULT_RESPONSE_RING_LENGTH; > + header->offset = PAGE_SIZE; > + > + return 0; > +out: > + vdev->fault_response_pages = NULL; > + return ret; > +} > + > static int vfio_pci_enable(struct vfio_pci_device *vdev) > { > struct pci_dev *pdev = vdev->pdev; > @@ -602,6 +693,10 @@ static int vfio_pci_enable(struct vfio_pci_device > *vdev) > if (ret) > goto disable_exit; > > + ret = vfio_pci_dma_fault_response_init(vdev); > + if (ret) > + goto disable_exit; > + > vfio_pci_probe_mmaps(vdev); > > return 0; > @@ -2227,6 +2322,7 @@ static int vfio_pci_probe(struct pci_dev *pdev, const > struct pci_device_id *id) > INIT_LIST_HEAD(&vdev->ioeventfds_list); > mutex_init(&vdev->vma_lock); > INIT_LIST_HEAD(&vdev->vma_list); > + INIT_LIST_HEAD(&vdev->dummy_resources_list); > init_rwsem(&vdev->memory_lock); > > ret = vfio_add_group_dev(&pdev->dev, &vfio_pci_ops, vdev); > diff --git a/drivers/vfio/pci/vfio_pci_private.h > b/drivers/vfio/pci/vfio_pci_private.h > index e180b5435c8f..035634521cd0 100644 > --- a/drivers/vfio/pci/vfio_pci_private.h > +++ b/drivers/vfio/pci/vfio_pci_private.h > @@ -144,7 +144,9 @@ struct vfio_pci_device { > struct eventfd_ctx *err_trigger; > struct eventfd_ctx *req_trigger; > u8 *fault_pages; > + u8 *fault_response_pages; > struct mutex fault_queue_lock; > + struct mutex fault_response_queue_lock; > struct list_head dummy_resources_list; > struct mutex ioeventfds_lock; > struct list_head ioeventfds_list; > @@ -189,6 +191,9 @@ extern long vfio_pci_ioeventfd(struct vfio_pci_device > *vdev, loff_t offset, > extern size_t vfio_pci_dma_fault_rw(struct vfio_pci_device *vdev, > char __user *buf, size_t count, > loff_t *ppos, bool iswrite); > +extern size_t vfio_pci_dma_fault_response_rw(struct vfio_pci_device *vdev, > + char __user *buf, size_t count, > + loff_t *ppos, bool iswrite); > > extern int vfio_pci_init_perm_bits(void); > extern void vfio_pci_uninit_perm_bits(void); > diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c > index 164120607469..efde0793360b 100644 > --- a/drivers/vfio/pci/vfio_pci_rdwr.c > +++ b/drivers/vfio/pci/vfio_pci_rdwr.c > @@ -400,6 +400,45 @@ size_t vfio_pci_dma_fault_rw(struct vfio_pci_device > *vdev, char __user *buf, > return ret; > } > > +size_t vfio_pci_dma_fault_response_rw(struct vfio_pci_device *vdev, char > __user *buf, > + size_t count, loff_t *ppos, bool iswrite) > +{ > + unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - > VFIO_PCI_NUM_REGIONS; > + loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; > + void *base = vdev->region[i].data; > + int ret = -EFAULT; > + > + if (pos >= vdev->region[i].size) > + return -EINVAL; > + > + count = min(count, (size_t)(vdev->region[i].size - pos)); > + > + if (iswrite) { > + struct vfio_region_dma_fault_response *header = > + (struct vfio_region_dma_fault_response *)base; > + uint32_t new_head; > + > + if (pos != 0 || count != 4) > + return -EINVAL; > + > + if (copy_from_user((void *)&new_head, buf, count)) > + return -EFAULT; > + > + if (new_head >= header->nb_entries) > + return -EINVAL; > + > + mutex_lock(&vdev->fault_response_queue_lock); > + header->head = new_head; > + mutex_unlock(&vdev->fault_response_queue_lock); > + } else { > + if (copy_to_user(buf, base + pos, count)) > + return -EFAULT; > + } > + *ppos += count; > + ret = count; > + return ret; > +} > + > static void vfio_pci_ioeventfd_do_write(struct vfio_pci_ioeventfd *ioeventfd, > bool test_mem) > { > diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h > index 1e5c82f9d14d..5d106db7a4c5 100644 > --- a/include/uapi/linux/vfio.h > +++ b/include/uapi/linux/vfio.h > @@ -345,6 +345,7 @@ struct vfio_region_info_cap_type { > > #define VFIO_REGION_TYPE_NESTED (2) > #define VFIO_REGION_SUBTYPE_NESTED_DMA_FAULT (1) > +#define VFIO_REGION_SUBTYPE_NESTED_DMA_FAULT_RESPONSE (2) > > /** > * struct vfio_region_gfx_edid - EDID region layout. > @@ -1022,6 +1023,17 @@ struct vfio_region_info_cap_fault { > __u32 version; > }; > > +/* > + * Capability exposed by the DMA fault response region > + * @version: ABI version > + */ > +#define VFIO_REGION_INFO_CAP_DMA_FAULT_RESPONSE 7 > + > +struct vfio_region_info_cap_fault_response { > + struct vfio_info_cap_header header; > + __u32 version; > +}; > + > /* > * DMA Fault Region Layout > * @tail: index relative to the start of the ring buffer at which the > @@ -1042,6 +1054,26 @@ struct vfio_region_dma_fault { > __u32 head; > }; > > +/* > + * DMA Fault Response Region Layout > + * @head: index relative to the start of the ring buffer at which the > + * producer (userspace) insert responses into the buffer > + * @entry_size: fault ring buffer entry size in bytes > + * @nb_entries: max capacity of the fault ring buffer > + * @offset: ring buffer offset relative to the start of the region > + * @tail: index relative to the start of the ring buffer at which the > + * consumer (kernel) finds the next item in the buffer > + */ > +struct vfio_region_dma_fault_response { > + /* Write-Only */ > + __u32 head; > + /* Read-Only */ > + __u32 entry_size; > + __u32 nb_entries; > + __u32 offset; > + __u32 tail; > +}; > + > /* -------- API for Type1 VFIO IOMMU -------- */ > > /** > -- > 2.21.3

1 0

[PATCH] dma-mapping: benchmark: fix kernel crash when dma_map_single fails
by Barry Song 08 Jan '21

08 Jan '21

if dma_map_single() fails, kernel will give the below oops since task_struct has been destroyed and we are running into the memory corruption due to use-after-free in kthread_stop(): [ 48.095310] Unable to handle kernel paging request at virtual address 000000c473548040 [ 48.095736] Mem abort info: [ 48.095864] ESR = 0x96000004 [ 48.096025] EC = 0x25: DABT (current EL), IL = 32 bits [ 48.096268] SET = 0, FnV = 0 [ 48.096401] EA = 0, S1PTW = 0 [ 48.096538] Data abort info: [ 48.096659] ISV = 0, ISS = 0x00000004 [ 48.096820] CM = 0, WnR = 0 [ 48.097079] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000104639000 [ 48.098099] [000000c473548040] pgd=0000000000000000, p4d=0000000000000000 [ 48.098832] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 48.099232] Modules linked in: [ 48.099387] CPU: 0 PID: 2 Comm: kthreadd Tainted: G W [ 48.099887] Hardware name: linux,dummy-virt (DT) [ 48.100078] pstate: 60000005 (nZCv daif -PAN -UAO -TCO BTYPE=--) [ 48.100516] pc : __kmalloc_node+0x214/0x368 [ 48.100944] lr : __kmalloc_node+0x1f4/0x368 [ 48.101458] sp : ffff800011f0bb80 [ 48.101843] x29: ffff800011f0bb80 x28: ffff0000c0098ec0 [ 48.102330] x27: 0000000000000000 x26: 00000000001d4600 [ 48.102648] x25: ffff0000c0098ec0 x24: ffff800011b6a000 [ 48.102988] x23: 00000000ffffffff x22: ffff0000c0098ec0 [ 48.103333] x21: ffff8000101d7a54 x20: 0000000000000dc0 [ 48.103657] x19: ffff0000c0001e00 x18: 0000000000000000 [ 48.104069] x17: 0000000000000000 x16: 0000000000000000 [ 48.105449] x15: 000001aa0304e7b9 x14: 00000000000003b1 [ 48.106401] x13: ffff8000122d5000 x12: ffff80001228d000 [ 48.107296] x11: ffff0000c0154340 x10: 0000000000000000 [ 48.107862] x9 : ffff80000fffffff x8 : ffff0000c473527f [ 48.108326] x7 : ffff800011e62f58 x6 : ffff0000c01c8ed8 [ 48.108778] x5 : ffff0000c0098ec0 x4 : 0000000000000000 [ 48.109223] x3 : 00000000001d4600 x2 : 0000000000000040 [ 48.109656] x1 : 0000000000000001 x0 : ff0000c473548000 [ 48.110104] Call trace: [ 48.110287] __kmalloc_node+0x214/0x368 [ 48.110493] __vmalloc_node_range+0xc4/0x298 [ 48.110805] copy_process+0x2c8/0x15c8 [ 48.111133] kernel_clone+0x5c/0x3c0 [ 48.111373] kernel_thread+0x64/0x90 [ 48.111604] kthreadd+0x158/0x368 [ 48.111810] ret_from_fork+0x10/0x30 [ 48.112336] Code: 17ffffe9 b9402a62 b94008a1 11000421 (f8626802) [ 48.112884] ---[ end trace d4890e21e75419d5 ]--- Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/dma/map_benchmark.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index b1496e744c68..1b1b8ff875cb 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -147,8 +147,10 @@ static int do_map_benchmark(struct map_benchmark_data *map) atomic64_set(&map->sum_sq_unmap, 0); atomic64_set(&map->loops, 0); - for (i = 0; i < threads; i++) + for (i = 0; i < threads; i++) { + get_task_struct(tsk[i]); wake_up_process(tsk[i]); + } msleep_interruptible(map->bparam.seconds * 1000); @@ -183,6 +185,8 @@ static int do_map_benchmark(struct map_benchmark_data *map) } out: + for (i = 0; i < threads; i++) + put_task_struct(tsk[i]); put_device(map->dev); kfree(tsk); return ret; -- 2.25.1

1 0

[PATCH v2] genirq: add IRQF_NO_AUTOEN for request_irq
by Barry Song 08 Jan '21

08 Jan '21

Many drivers don't want interrupts enabled automatically due to request_irq(). So they are handling this issue by either way of the below two: (1) irq_set_status_flags(irq, IRQ_NOAUTOEN); request_irq(dev, irq...); (2) request_irq(dev, irq...); disable_irq(irq); The code in the second way is silly and unsafe. In the small time gap between request_irq() and disable_irq(), interrupts can still come. The code in the first way is safe though we might be able to do it in the generic irq code. With this patch, drivers can request_irq with IRQF_NO_AUTOEN flag. They will need neither irq_set_status_flags() nor disable_irq(). Hundreds of drivers with this problem will be handled afterwards. Cc: Dmitry Torokhov <dmitry.torokhov(a)gmail.com> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- -v2: refuse the cases IRQF_NO_AUTOEN + IRQF_DISABLED are both set with respect to Dmitry's feedback in v1 include/linux/interrupt.h | 3 +++ kernel/irq/manage.c | 8 ++++++++ kernel/irq/settings.h | 10 ++++++++++ 3 files changed, 21 insertions(+) diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index bb8ff9083e7d..0f22d277078c 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -61,6 +61,8 @@ * interrupt handler after suspending interrupts. For system * wakeup devices users need to implement wakeup detection in * their interrupt handlers. + * IRQF_NO_AUTOEN - Don't enable IRQ automatically when users request it. Users + * will enable it explicitly by enable_irq() later. */ #define IRQF_SHARED 0x00000080 #define IRQF_PROBE_SHARED 0x00000100 @@ -74,6 +76,7 @@ #define IRQF_NO_THREAD 0x00010000 #define IRQF_EARLY_RESUME 0x00020000 #define IRQF_COND_SUSPEND 0x00040000 +#define IRQF_NO_AUTOEN 0x00080000 #define IRQF_TIMER (__IRQF_TIMER | IRQF_NO_SUSPEND | IRQF_NO_THREAD) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index ab8567f32501..2b28314e2572 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -1693,6 +1693,9 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) irqd_set(&desc->irq_data, IRQD_NO_BALANCING); } + if (new->flags & IRQF_NO_AUTOEN) + irq_settings_set_noautoen(desc); + if (irq_settings_can_autoenable(desc)) { irq_startup(desc, IRQ_RESEND, IRQ_START_COND); } else { @@ -2086,10 +2089,15 @@ int request_threaded_irq(unsigned int irq, irq_handler_t handler, * which interrupt is which (messes up the interrupt freeing * logic etc). * + * Also shared interrupts do not go well with disabling auto enable. + * The sharing interrupt might request it while it's still disabled + * and then wait for interrupts forever. + * * Also IRQF_COND_SUSPEND only makes sense for shared interrupts and * it cannot be set along with IRQF_NO_SUSPEND. */ if (((irqflags & IRQF_SHARED) && !dev_id) || + ((irqflags & IRQF_SHARED) && (irqflags & IRQF_NO_AUTOEN)) || (!(irqflags & IRQF_SHARED) && (irqflags & IRQF_COND_SUSPEND)) || ((irqflags & IRQF_NO_SUSPEND) && (irqflags & IRQF_COND_SUSPEND))) return -EINVAL; diff --git a/kernel/irq/settings.h b/kernel/irq/settings.h index 403378b9947b..a28958a9c548 100644 --- a/kernel/irq/settings.h +++ b/kernel/irq/settings.h @@ -145,6 +145,16 @@ static inline bool irq_settings_can_move_pcntxt(struct irq_desc *desc) return desc->status_use_accessors & _IRQ_MOVE_PCNTXT; } +static inline void irq_settings_clr_noautoen(struct irq_desc *desc) +{ + desc->status_use_accessors &= ~_IRQ_NOAUTOEN; +} + +static inline void irq_settings_set_noautoen(struct irq_desc *desc) +{ + desc->status_use_accessors |= _IRQ_NOAUTOEN; +} + static inline bool irq_settings_can_autoenable(struct irq_desc *desc) { return !(desc->status_use_accessors & _IRQ_NOAUTOEN); -- 2.25.1

3 2

Re: [RFC PATCH v2 07/32] hw/cxl/device: Implement basic mailbox (8.2.8.4)
by Jonathan Cameron 07 Jan '21

07 Jan '21

On Tue, 5 Jan 2021 08:52:58 -0800 Ben Widawsky <ben.widawsky(a)intel.com> wrote: > This is the beginning of implementing mailbox support for CXL 2.0 > devices. > > v2: Use register alignment helper (Ben) > Minor cleanups (Jonathan) > Rename error codes to match spec (Jonathan) > Update cap count from 1 to 2 (Jonathan) > Add infra to support CEL (Ben) > Add more of the actual mailbox handling from later patch (Ben) > > Signed-off-by: Ben Widawsky <ben.widawsky(a)intel.com> Hi Ben, I hacked support in for ARM64 to give this a spin and ran into an interesting problem around read sizes. The mailbox registers space allows 4 or 8 byte reads, but in the kernel driver (I think I have the right version from your github) you do the payload drain with memcpy_from_io() If the size of the payload is not a multiple of 8 bytes, on ARM64 that results in byte reads and an exception. This happens with some of the existing calls which happen to have non multiple of 8 payload sizes. I hacked below to allow 1 byte reads from that region but that's probably not the right fix. I found a statement in the CXL spec saying maximum read size from this register block was 8 bytes but couldn't immediately see a minimum. (I haven't looked that hard yet though!) Various approaches in kernel could also be used: 1) Change the payload drain to have specific handling for the end few bytes. 2) Pad the various structures to ensure payloads are always 8 byte multiples in length (nasty). > --- > hw/cxl/cxl-device-utils.c | 122 ++++++++++++++++++++++++- > hw/cxl/cxl-mailbox-utils.c | 173 ++++++++++++++++++++++++++++++++++++ > hw/cxl/meson.build | 1 + > include/hw/cxl/cxl.h | 3 + > include/hw/cxl/cxl_device.h | 27 +++++- > 5 files changed, 322 insertions(+), 4 deletions(-) > create mode 100644 hw/cxl/cxl-mailbox-utils.c > > diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c > index b86e5466bd..642e3c2617 100644 > --- a/hw/cxl/cxl-device-utils.c > +++ b/hw/cxl/cxl-device-utils.c > @@ -44,6 +44,108 @@ static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size) > return ldn_le_p(&retval, size); > } > > +static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned size) > +{ > + CXLDeviceState *cxl_dstate = opaque; > + > + if (cxl_device_check_register_alignment(offset, size)) { > + qemu_log_mask(LOG_UNIMP, "Unaligned register read\n"); > + return 0; > + } > + > + return ldn_le_p(cxl_dstate->mbox_reg_state + offset, size); > +} > + > +static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset, > + uint64_t value) > +{ > + switch (offset) { > + case A_CXL_DEV_MAILBOX_CTRL: > + /* fallthrough */ > + case A_CXL_DEV_MAILBOX_CAP: > + /* RO register */ > + break; > + default: > + qemu_log_mask(LOG_UNIMP, > + "%s Unexpected 32-bit access to 0x%" PRIx64 " (WI)\n", > + __func__, offset); > + break; > + } > + > + stl_le_p((uint8_t *)reg_state + offset, value); > +} > + > +static void mailbox_mem_writeq(uint8_t *reg_state, hwaddr offset, > + uint64_t value) > +{ > + switch (offset) { > + case A_CXL_DEV_MAILBOX_CMD: > + break; > + case A_CXL_DEV_BG_CMD_STS: > + /* BG not supported */ > + /* fallthrough */ > + case A_CXL_DEV_MAILBOX_STS: > + /* Read only register, will get updated by the state machine */ > + return; > + default: > + qemu_log_mask(LOG_UNIMP, > + "%s Unexpected 64-bit access to 0x%" PRIx64 " (WI)\n", > + __func__, offset); > + return; > + } > + > + stq_le_p(reg_state + offset, value); > +} > + > +static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value, > + unsigned size) > +{ > + CXLDeviceState *cxl_dstate = opaque; > + > + /* > + * Lock is needed to prevent concurrent writes as well as to prevent writes > + * coming in while the firmware is processing. Without background commands > + * or the second mailbox implemented, this serves no purpose since the > + * memory access is synchronized at a higher level (per memory region). > + */ > + RCU_READ_LOCK_GUARD(); > + > + switch (size) { > + case 4: > + if (unlikely(offset & (sizeof(uint32_t) - 1))) { > + qemu_log_mask(LOG_UNIMP, "Unaligned register read\n"); > + return; > + } > + mailbox_mem_writel(cxl_dstate->mbox_reg_state32, offset, value); > + break; > + case 8: > + if (unlikely(offset & (sizeof(uint64_t) - 1))) { > + qemu_log_mask(LOG_UNIMP, "Unaligned register read\n"); > + return; > + } > + mailbox_mem_writeq(cxl_dstate->mbox_reg_state, offset, value); > + break; > + } > + > + if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, > + DOORBELL)) > + cxl_process_mailbox(cxl_dstate); > +} > + > +static const MemoryRegionOps mailbox_ops = { > + .read = mailbox_reg_read, > + .write = mailbox_reg_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 4, Hack was to set this to 1 (and the impl below - no idea if both are needed). > + .max_access_size = 8, > + }, > + .impl = { > + .min_access_size = 4, > + .max_access_size = 8, > + }, > +}; > + > static const MemoryRegionOps dev_ops = { > .read = dev_reg_read, > .write = NULL, > @@ -83,20 +185,33 @@ void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate) > "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); > memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, > "device-status", CXL_DEVICE_REGISTERS_LENGTH); > + memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dstate, > + "mailbox", CXL_MAILBOX_REGISTERS_LENGTH); > > memory_region_add_subregion(&cxl_dstate->device_registers, 0, > &cxl_dstate->caps); > memory_region_add_subregion(&cxl_dstate->device_registers, > CXL_DEVICE_REGISTERS_OFFSET, > &cxl_dstate->device); > + memory_region_add_subregion(&cxl_dstate->device_registers, > + CXL_MAILBOX_REGISTERS_OFFSET, > + &cxl_dstate->mailbox); > } > > static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } > > +static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate) > +{ > + /* 2048 payload size, with no interrupt or background support */ > + ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, > + PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT); > + cxl_dstate->payload_size = CXL_MAILBOX_MAX_PAYLOAD_SIZE; > +} > + > void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) > { > uint32_t *cap_hdrs = cxl_dstate->caps_reg_state32; > - const int cap_count = 1; > + const int cap_count = 2; > > /* CXL Device Capabilities Array Register */ > ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); > @@ -105,4 +220,9 @@ void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) > > cxl_device_cap_init(cxl_dstate, DEVICE, 1); > device_reg_init_common(cxl_dstate); > + > + cxl_device_cap_init(cxl_dstate, MAILBOX, 2); > + mailbox_reg_init_common(cxl_dstate); > + > + assert(cxl_initialize_mailbox(cxl_dstate) == 0); > } > diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c > new file mode 100644 > index 0000000000..3a39c936de > --- /dev/null > +++ b/hw/cxl/cxl-mailbox-utils.c > @@ -0,0 +1,173 @@ > +/* > + * CXL Utility library for mailbox interface > + * > + * Copyright(C) 2020 Intel Corporation. > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See the > + * COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/cxl/cxl.h" > +#include "hw/pci/pci.h" > +#include "qemu/log.h" > +#include "qemu/uuid.h" > + > +/* > + * How to add a new command, example. The command set FOO, with cmd BAR. > + * 1. Add the command set and cmd to the enum. > + * FOO = 0x7f, > + * #define BAR 0 > + * 2. Forward declare the handler. > + * declare_mailbox_handler(FOO_BAR); > + * 3. Add the command to the cxl_cmd_set[][] > + * CXL_CMD(FOO, BAR, 0, 0), > + * 4. Implement your handler > + * define_mailbox_handler(FOO_BAR) { ... return CXL_MBOX_SUCCESS; } > + * > + * > + * Writing the handler: > + * The handler will provide the &struct cxl_cmd, the &CXLDeviceState, and the > + * in/out length of the payload. The handler is responsible for consuming the > + * payload from cmd->payload and operating upon it as necessary. It must then > + * fill the output data into cmd->payload (overwriting what was there), > + * setting the length, and returning a valid return code. > + * > + * XXX: The handler need not worry about endianess. The payload is read out of > + * a register interface that already deals with it. > + */ > + > +/* 8.2.8.4.5.1 Command Return Codes */ > +typedef enum { > + CXL_MBOX_SUCCESS = 0x0, > + CXL_MBOX_BG_STARTED = 0x1, > + CXL_MBOX_INVALID_INPUT = 0x2, > + CXL_MBOX_UNSUPPORTED = 0x3, > + CXL_MBOX_INTERNAL_ERROR = 0x4, > + CXL_MBOX_RETRY_REQUIRED = 0x5, > + CXL_MBOX_BUSY = 0x6, > + CXL_MBOX_MEDIA_DISABLED = 0x7, > + CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8, > + CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9, > + CXL_MBOX_FW_AUTH_FAILED = 0xa, > + CXL_MBOX_FW_INVALID_SLOT = 0xb, > + CXL_MBOX_FW_ROLLEDBACK = 0xc, > + CXL_MBOX_FW_REST_REQD = 0xd, > + CXL_MBOX_INVALID_HANDLE = 0xe, > + CXL_MBOX_INVALID_PA = 0xf, > + CXL_MBOX_INJECT_POISON_LIMIT = 0x10, > + CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11, > + CXL_MBOX_ABORTED = 0x12, > + CXL_MBOX_INVALID_SECURITY_STATE = 0x13, > + CXL_MBOX_INCORRECT_PASSPHRASE = 0x14, > + CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15, > + CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16, > + CXL_MBOX_MAX = 0x17 > +} ret_code; > + > +struct cxl_cmd; > +typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd, > + CXLDeviceState *cxl_dstate, uint16_t *len); > +struct cxl_cmd { > + const char *name; > + opcode_handler handler; > + ssize_t in; > + uint16_t effect; /* Reported in CEL */ > + uint8_t *payload; > +}; > + > +#define define_mailbox_handler(name) \ > + static ret_code cmd_##name(struct cxl_cmd *cmd, \ > + CXLDeviceState *cxl_dstate, uint16_t *len) > +#define declare_mailbox_handler(name) define_mailbox_handler(name) > + > +#define CXL_CMD(s, c, in, cel_effect) \ > + [s][c] = { stringify(s##_##c), cmd_##s##_##c, in, cel_effect } > + > +static struct cxl_cmd cxl_cmd_set[256][256] = {}; > + > +#undef CXL_CMD > + > +QemuUUID cel_uuid; > + > +void cxl_process_mailbox(CXLDeviceState *cxl_dstate) > +{ > + uint16_t ret = CXL_MBOX_SUCCESS; > + struct cxl_cmd *cxl_cmd; > + uint64_t status_reg; > + opcode_handler h; > + > + /* > + * current state of mailbox interface > + * mbox_cap_reg = cxl_dstate->reg_state32[R_CXL_DEV_MAILBOX_CAP]; > + * mbox_ctrl_reg = cxl_dstate->reg_state32[R_CXL_DEV_MAILBOX_CTRL]; > + * status_reg = *(uint64_t *)&cxl_dstate->reg_state[A_CXL_DEV_MAILBOX_STS]; > + */ > + uint64_t command_reg = > + *(uint64_t *)&cxl_dstate->mbox_reg_state[A_CXL_DEV_MAILBOX_CMD]; > + > + /* Check if we have to do anything */ > + if (!ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, > + DOORBELL)) { > + qemu_log_mask(LOG_UNIMP, "Corrupt internal state for firmware\n"); > + return; > + } > + > + uint8_t set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET); > + uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND); > + uint16_t len = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH); > + cxl_cmd = &cxl_cmd_set[set][cmd]; > + h = cxl_cmd->handler; > + if (!h) { > + goto handled; > + } > + > + if (len != cxl_cmd->in) { > + ret = CXL_MBOX_INVALID_PAYLOAD_LENGTH; > + } > + > + cxl_cmd->payload = cxl_dstate->mbox_reg_state + A_CXL_DEV_CMD_PAYLOAD; > + ret = (*h)(cxl_cmd, cxl_dstate, &len); > + assert(len <= cxl_dstate->payload_size); > + > +handled: > + /* > + * Set the return code > + * XXX: it's a 64b register, but we're not setting the vendor, so we can get > + * away with this > + */ > + status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret); > + > + /* > + * Set the return length > + */ > + command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET, 0); > + command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, 0); > + command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, len); > + > + stq_le_p(cxl_dstate->mbox_reg_state + A_CXL_DEV_MAILBOX_CMD, command_reg); > + stq_le_p(cxl_dstate->mbox_reg_state + A_CXL_DEV_MAILBOX_STS, status_reg); > + > + /* Tell the host we're done */ > + ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, > + DOORBELL, 0); > +} > + > +int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate) > +{ > + const char *cel_uuidstr = "0da9c0b5-bf41-4b78-8f79-96b1623b3f17"; > + > + for (int i = 0; i < 256; i++) { > + for (int j = 0; j < 256; j++) { > + if (cxl_cmd_set[i][j].handler) { > + struct cxl_cmd *c = &cxl_cmd_set[i][j]; > + > + cxl_dstate->cel_log[cxl_dstate->cel_size].opcode = (i << 8) | j; > + cxl_dstate->cel_log[cxl_dstate->cel_size].effect = c->effect; > + cxl_dstate->cel_size++; > + } > + } > + } > + > + return qemu_uuid_parse(cel_uuidstr, &cel_uuid); > +} > diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build > index 47154d6850..0eca715d10 100644 > --- a/hw/cxl/meson.build > +++ b/hw/cxl/meson.build > @@ -1,4 +1,5 @@ > softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( > 'cxl-component-utils.c', > 'cxl-device-utils.c', > + 'cxl-mailbox-utils.c', > )) > diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h > index 23f52c4cf9..362cda40de 100644 > --- a/include/hw/cxl/cxl.h > +++ b/include/hw/cxl/cxl.h > @@ -14,5 +14,8 @@ > #include "cxl_component.h" > #include "cxl_device.h" > > +#define COMPONENT_REG_BAR_IDX 0 > +#define DEVICE_REG_BAR_IDX 2 > + > #endif > > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > index 3380fc9e7a..bdf990cec2 100644 > --- a/include/hw/cxl/cxl_device.h > +++ b/include/hw/cxl/cxl_device.h > @@ -70,9 +70,10 @@ > (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) > > typedef struct cxl_device_state { > - /* Boss container and caps registers */ > + /* Main register container */ > MemoryRegion device_registers; > > + MemoryRegion device; > struct { > MemoryRegion caps; > union { > @@ -80,8 +81,19 @@ typedef struct cxl_device_state { > uint32_t caps_reg_state32[CXL_DEVICE_CAP_REG_SIZE >> 2]; > }; > }; > - MemoryRegion device; > - MemoryRegion mailbox; > + struct { > + MemoryRegion mailbox; > + uint16_t payload_size; > + union { > + uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH]; > + uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH >> 2]; > + }; > + struct { > + uint16_t opcode; > + uint16_t effect; > + } cel_log[1 << 16]; > + size_t cel_size; > + }; > > MemoryRegion *pmem; > MemoryRegion *vmem; > @@ -122,6 +134,9 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) > CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ > CXL_DEVICE_CAP_REG_SIZE) > > +int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate); > +void cxl_process_mailbox(CXLDeviceState *cxl_dstate); > + > #define cxl_device_cap_init(dstate, reg, cap_id) \ > do { \ > uint32_t *cap_hdrs = dstate->caps_reg_state32; \ > @@ -149,6 +164,12 @@ REG32(CXL_DEV_MAILBOX_CTRL, 4) > FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) > FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) > > +/* XXX: actually a 64b register */ > +REG32(CXL_DEV_MAILBOX_CMD, 8) > + FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8) > + FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8) > + FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20) > + > /* XXX: actually a 64b register */ > REG32(CXL_DEV_MAILBOX_STS, 0x10) > FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)

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Re: [PATCH net-next 1/2] {topost} net: hns3: add suspend/resume function for hns3 driver
by Salil Mehta 06 Jan '21

06 Jan '21

> From: linyunsheng > Sent: Wednesday, January 6, 2021 2:34 AM > To: zhangjiaran <zhangjiaran(a)huawei.com>; shenjian (K) <shenjian15(a)huawei.com>; > lipeng (Y) <lipeng321(a)huawei.com>; tanhuazhong <tanhuazhong(a)huawei.com>; Salil > Mehta <salil.mehta(a)huawei.com>; huangguangbin (A) <huangguangbin2(a)huawei.com>; > moyufeng <moyufeng(a)huawei.com>; chenhao (DY) <chenhao288(a)hisilicon.com> > Cc: Linuxarm <linuxarm(a)huawei.com> > Subject: Re: [PATCH net-next 1/2] {topost} net: hns3: add suspend/resume function > for hns3 driver > > On 2020/12/30 12:44, Jiaran Zhang wrote: > > To implement the system hibernation and wakeup functions, the NIC driver > > needs to support the PCI suspend and resume functions. The following > > functions need to be supported: > > 1. When the system enters the hibernation mode, the driver needs to > > implement the suspend callback function of the NIC device. The driver > > needs to mute the device, stop all RX/TX activities of the device, and > > unmap the interrupt. > > 2. When the system enters the wakeup mode (self-wakeup/wakeup > > source-triggered wakeup), the driver needs to implement the resume > > callback function of the NIC device and restore the device to the state > > before suspension. [...] > > > > diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c > b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c > > index 405e490..d1bc430 100644 > > --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c > > +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c > > @@ -2323,6 +2323,28 @@ static void hns3_shutdown(struct pci_dev *pdev) > > pci_set_power_state(pdev, PCI_D3hot); > > } > > > > +static int hns3_suspend(struct device *dev) > > It seems the i40e has the "__maybe_unused" keyword as below: > > static int __maybe_unused i40e_resume(struct device *dev) This is a good point and I saw most of the drivers which are initializing PM ops using SIMPLE_DEV_PM_OPS() are using this to avoid warning perhaps. The also checked the history of it in the GCC, interestingly it looks The __attribute((unused)) is missing from GCC documentation from GCC 6.2.0 onwards. I am not sure why. https://gcc.gnu.org/onlinedocs/gcc-6.2.0/gcc/Function-Attributes.html But below GCC 5.4.0 does have the mention of the unused attribute. https://gcc.gnu.org/onlinedocs/gcc-5.4.0/gcc/Function-Attributes.html Maybe worth checking why this is so. Salil.

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Re: [PATCH plinth/i2c-for-5.11 0/3] Add support for HiSilicon I2C controller
by John Garry 06 Jan '21

06 Jan '21

On 06/01/2021 09:37, Yicong Yang wrote: > Add driver and MAINTAINERS for HiSilicon I2C controller on Kunpeng server. Also > provide the devm_*() variants for adding the I2C adapters. How about resend with cc linuxarm(a)openeuler.org? thanks > > Yicong Yang (3): > i2c: core: add managed functions for adding i2c adapters > i2c: add support for HiSilicon I2C controller > MAINTAINERS: Add maintainer for HiSilicon I2C driver > > MAINTAINERS | 7 + > drivers/i2c/busses/Kconfig | 10 + > drivers/i2c/busses/Makefile | 1 + > drivers/i2c/busses/i2c-hisi.c | 555 ++++++++++++++++++++++++++++++++++++++++++ > drivers/i2c/i2c-core-base.c | 82 +++++++ > include/linux/i2c.h | 2 + > 6 files changed, 657 insertions(+) > create mode 100644 drivers/i2c/busses/i2c-hisi.c >

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[PATCH for-next] RDMA/hns: Add caps flag for UD inline of userspace
by Weihang Li 05 Jan '21

05 Jan '21

HIP09 supports UD inline up to size of 1024 Bytes, the caps flag is got from firmware and passed back to userspace when creating QP. Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_device.h | 1 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 3 +++ drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 1 + drivers/infiniband/hw/hns/hns_roce_qp.c | 3 +++ include/uapi/rdma/hns-abi.h | 1 + 5 files changed, 9 insertions(+) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 55d5386..87716da 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -214,6 +214,7 @@ enum { HNS_ROCE_CAP_FLAG_FRMR = BIT(8), HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), + HNS_ROCE_CAP_FLAG_UD_SQ_INL = BIT(13), HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), HNS_ROCE_CAP_FLAG_STASH = BIT(17), }; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 833e1f2..619e828 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1916,6 +1916,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->gmv_buf_pg_sz = 0; caps->gid_table_len[0] = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); + caps->flags |= HNS_ROCE_CAP_FLAG_UD_SQ_INL; + caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INL_EXT; } } @@ -5084,6 +5086,7 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, qp_attr->cur_qp_state = qp_attr->qp_state; qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; + qp_attr->cap.max_inline_data = hr_qp->max_inline_data; if (!ibqp->uobject) { qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index bdaccf8..ab685a4 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -61,6 +61,7 @@ #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 +#define HNS_ROCE_V2_MAX_SQ_INL_EXT 0x400 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32 #define HNS_ROCE_V2_UAR_NUM 256 #define HNS_ROCE_V2_PHY_UAR_NUM 1 diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index d8e2fe5..b19fcbd 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -1020,6 +1020,9 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, } if (udata) { + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_UD_SQ_INL) + resp.cap_flags |= HNS_ROCE_QP_CAP_UD_SQ_INL; + ret = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); if (ret) { diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h index 90b739d..79dba94 100644 --- a/include/uapi/rdma/hns-abi.h +++ b/include/uapi/rdma/hns-abi.h @@ -77,6 +77,7 @@ enum hns_roce_qp_cap_flags { HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0, HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1, HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2, + HNS_ROCE_QP_CAP_UD_SQ_INL = 1 << 3, }; struct hns_roce_ib_create_qp_resp { -- 2.8.1

3 2

Is it ok to use debugfs to dump some ucontext-level driver-defined info?
by liweihang 05 Jan '21

05 Jan '21

Hi all, We want to dump some hns driver-defined information that belongs to a process to keep track of current memory usage. For example, there is a ucontext-level(process-level) memory pool to store WQE which is shared by a lot of QPs, we want to record and query which QPs are using this pool and how much space each QP is using. rdmatool don't have a ucontext-level resource tracking currently, is it ok to achieve that through debugfs? This may looks like: $ echo 1 > <dbgfs_dir>/hns_roce/hns_0/<pid>/qp QPN Total(kB) SQ(kB) SGE(kB) RQ(kB) 110 6400 256 2048 4096 118 6400 256 2048 0 Or should it be achieved in rdmatool? Thanks Weihang

2 5

[PATCH] genirq: add IRQF_NO_AUTOEN for request_irq
by Barry Song 05 Jan '21

05 Jan '21

This patch originated from the discussion with Dmitry in the below thread: https://lore.kernel.org/linux-input/20210102042902.41664-1-song.bao.hua@his… there are many drivers which don't want interrupts enabled automatically due to request_irq(). So they are handling this issue by either way of the below two: (1) irq_set_status_flags(irq, IRQ_NOAUTOEN); request_irq(dev, irq...); (2) request_irq(dev, irq...); disable_irq(irq); The code in the second way is silly and unsafe. In the small time gap between request_irq and disable_irq, interrupts can still come. The code in the first way is safe though we might be able to do it in the generic irq code. I guess Dmitry also prefers genirq handles this as he said "What I would like to see is to allow passing something like IRQF_DISABLED to request_irq() so that we would not need neither irq_set_status_flags() nor disable_irq()" in the original email thread. If this one is accepted, hundreds of drivers with this problem will be handled afterwards. Cc: Dmitry Torokhov <dmitry.torokhov(a)gmail.com> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- include/linux/interrupt.h | 3 +++ kernel/irq/manage.c | 3 +++ kernel/irq/settings.h | 10 ++++++++++ 3 files changed, 16 insertions(+) diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index bb8ff9083e7d..0f22d277078c 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -61,6 +61,8 @@ * interrupt handler after suspending interrupts. For system * wakeup devices users need to implement wakeup detection in * their interrupt handlers. + * IRQF_NO_AUTOEN - Don't enable IRQ automatically when users request it. Users + * will enable it explicitly by enable_irq() later. */ #define IRQF_SHARED 0x00000080 #define IRQF_PROBE_SHARED 0x00000100 @@ -74,6 +76,7 @@ #define IRQF_NO_THREAD 0x00010000 #define IRQF_EARLY_RESUME 0x00020000 #define IRQF_COND_SUSPEND 0x00040000 +#define IRQF_NO_AUTOEN 0x00080000 #define IRQF_TIMER (__IRQF_TIMER | IRQF_NO_SUSPEND | IRQF_NO_THREAD) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index ab8567f32501..364e8b47d9ba 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -1693,6 +1693,9 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) irqd_set(&desc->irq_data, IRQD_NO_BALANCING); } + if (new->flags & IRQF_NO_AUTOEN) + irq_settings_set_noautoen(desc); + if (irq_settings_can_autoenable(desc)) { irq_startup(desc, IRQ_RESEND, IRQ_START_COND); } else { diff --git a/kernel/irq/settings.h b/kernel/irq/settings.h index 403378b9947b..a28958a9c548 100644 --- a/kernel/irq/settings.h +++ b/kernel/irq/settings.h @@ -145,6 +145,16 @@ static inline bool irq_settings_can_move_pcntxt(struct irq_desc *desc) return desc->status_use_accessors & _IRQ_MOVE_PCNTXT; } +static inline void irq_settings_clr_noautoen(struct irq_desc *desc) +{ + desc->status_use_accessors &= ~_IRQ_NOAUTOEN; +} + +static inline void irq_settings_set_noautoen(struct irq_desc *desc) +{ + desc->status_use_accessors |= _IRQ_NOAUTOEN; +} + static inline bool irq_settings_can_autoenable(struct irq_desc *desc) { return !(desc->status_use_accessors & _IRQ_NOAUTOEN); -- 2.25.1

3 2

[PATCH for-next] RDMA/hns: Create CQ with selected CQN for bank load balance
by Weihang Li 04 Jan '21

04 Jan '21

From: Yangyang Li <liyangyang20(a)huawei.com> In order to improve performance by balancing the load between different banks of cache, the CQC cache is desigend to choose one of 4 banks according to lower 2 bits of CQN. The hns driver needs to count the number of CQ on each bank and then assigns the CQ being created to the bank with the minimum load first. Signed-off-by: Yangyang Li <liyangyang20(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_cq.c | 114 +++++++++++++++++++++++----- drivers/infiniband/hw/hns/hns_roce_device.h | 10 ++- drivers/infiniband/hw/hns/hns_roce_main.c | 8 +- 3 files changed, 104 insertions(+), 28 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c index 8533fc2..00350a3 100644 --- a/drivers/infiniband/hw/hns/hns_roce_cq.c +++ b/drivers/infiniband/hw/hns/hns_roce_cq.c @@ -38,11 +38,74 @@ #include "hns_roce_hem.h" #include "hns_roce_common.h" +static u8 get_least_load_bankid_for_cq(struct hns_roce_bank *bank) +{ + u32 least_load = bank[0].inuse; + u8 bankid = 0; + u32 bankcnt; + u8 i; + + for (i = 1; i < HNS_ROCE_CQ_BANK_NUM; i++) { + bankcnt = bank[i].inuse; + if (bankcnt < least_load) { + least_load = bankcnt; + bankid = i; + } + } + + return bankid; +} + +static int alloc_cqn(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) +{ + struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; + struct hns_roce_bank *bank; + u8 bankid; + int id; + + spin_lock(&cq_table->bank_lock); + bankid = get_least_load_bankid_for_cq(cq_table->bank); + bank = &cq_table->bank[bankid]; + + id = ida_alloc_range(&bank->ida, bank->min, bank->max, GFP_ATOMIC); + if (id < 0) { + spin_unlock(&cq_table->bank_lock); + return id; + } + + /* the lower 2 bits is bankid */ + hr_cq->cqn = (id << CQ_BANKID_SHIFT) | bankid; + bank->inuse++; + spin_unlock(&cq_table->bank_lock); + + return 0; +} + +static inline u8 get_cq_bankid(unsigned long cqn) +{ + /* The lower 2 bits of CQN are used to hash to different banks */ + return (u8)(cqn & GENMASK(1, 0)); +} + +static void free_cqn(struct hns_roce_dev *hr_dev, unsigned long cqn) +{ + struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; + struct hns_roce_bank *bank; + + bank = &cq_table->bank[get_cq_bankid(cqn)]; + + ida_free(&bank->ida, cqn >> CQ_BANKID_SHIFT); + + spin_lock(&cq_table->bank_lock); + bank->inuse--; + spin_unlock(&cq_table->bank_lock); +} + static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) { + struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; struct ib_device *ibdev = &hr_dev->ib_dev; struct hns_roce_cmd_mailbox *mailbox; - struct hns_roce_cq_table *cq_table; u64 mtts[MTT_MIN_COUNT] = { 0 }; dma_addr_t dma_handle; int ret; @@ -54,13 +117,6 @@ static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) return -EINVAL; } - cq_table = &hr_dev->cq_table; - ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn); - if (ret) { - ibdev_err(ibdev, "failed to alloc CQ bitmap, ret = %d.\n", ret); - return ret; - } - /* Get CQC memory HEM(Hardware Entry Memory) table */ ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn); if (ret) { @@ -110,7 +166,6 @@ static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); err_out: - hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR); return ret; } @@ -138,7 +193,6 @@ static void free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) wait_for_completion(&hr_cq->free); hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); - hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR); } static int alloc_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq, @@ -298,11 +352,17 @@ int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, goto err_cq_buf; } + ret = alloc_cqn(hr_dev, hr_cq); + if (ret) { + ibdev_err(ibdev, "Failed to alloc CQN, err %d\n", ret); + goto err_cq_db; + } + ret = alloc_cqc(hr_dev, hr_cq); if (ret) { ibdev_err(ibdev, "failed to alloc CQ context, ret = %d.\n", ret); - goto err_cq_db; + goto err_cqn; } /* @@ -326,6 +386,8 @@ int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, err_cqc: free_cqc(hr_dev, hr_cq); +err_cqn: + free_cqn(hr_dev, hr_cq->cqn); err_cq_db: free_cq_db(hr_dev, hr_cq, udata); err_cq_buf: @@ -341,9 +403,11 @@ int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) if (hr_dev->hw->destroy_cq) hr_dev->hw->destroy_cq(ib_cq, udata); - free_cq_buf(hr_dev, hr_cq); - free_cq_db(hr_dev, hr_cq, udata); free_cqc(hr_dev, hr_cq); + free_cqn(hr_dev, hr_cq->cqn); + free_cq_db(hr_dev, hr_cq, udata); + free_cq_buf(hr_dev, hr_cq); + return 0; } @@ -402,18 +466,32 @@ void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type) complete(&hr_cq->free); } -int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev) +void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev) { struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; + unsigned int reserved_from_bot; + unsigned int i; xa_init(&cq_table->array); - return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs, - hr_dev->caps.num_cqs - 1, - hr_dev->caps.reserved_cqs, 0); + reserved_from_bot = hr_dev->caps.reserved_cqs; + + for (i = 0; i < reserved_from_bot; i++) { + cq_table->bank[get_cq_bankid(i)].inuse++; + cq_table->bank[get_cq_bankid(i)].min++; + } + + for (i = 0; i < HNS_ROCE_CQ_BANK_NUM; i++) { + ida_init(&cq_table->bank[i].ida); + cq_table->bank[i].max = hr_dev->caps.num_cqs / + HNS_ROCE_CQ_BANK_NUM - 1; + } } void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev) { - hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap); + int i; + + for (i = 0; i < HNS_ROCE_CQ_BANK_NUM; i++) + ida_destroy(&hr_dev->cq_table.bank[i].ida); } diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 55d5386..106cfef 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -119,6 +119,9 @@ #define SRQ_DB_REG 0x230 #define HNS_ROCE_QP_BANK_NUM 8 +#define HNS_ROCE_CQ_BANK_NUM 4 + +#define CQ_BANKID_SHIFT 2 /* The chip implementation of the consumer index is calculated * according to twice the actual EQ depth @@ -536,9 +539,10 @@ struct hns_roce_qp_table { }; struct hns_roce_cq_table { - struct hns_roce_bitmap bitmap; struct xarray array; struct hns_roce_hem_table table; + struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; + spinlock_t bank_lock; }; struct hns_roce_srq_table { @@ -779,7 +783,7 @@ struct hns_roce_caps { u32 max_cqes; u32 min_cqes; u32 min_wqes; - int reserved_cqs; + u32 reserved_cqs; int reserved_srqs; int num_aeq_vectors; int num_comp_vectors; @@ -1164,7 +1168,7 @@ int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); -int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); +void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c index d9179ba..2b78b1f 100644 --- a/drivers/infiniband/hw/hns/hns_roce_main.c +++ b/drivers/infiniband/hw/hns/hns_roce_main.c @@ -748,11 +748,7 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) goto err_pd_table_free; } - ret = hns_roce_init_cq_table(hr_dev); - if (ret) { - dev_err(dev, "Failed to init completion queue table.\n"); - goto err_mr_table_free; - } + hns_roce_init_cq_table(hr_dev); ret = hns_roce_init_qp_table(hr_dev); if (ret) { @@ -777,8 +773,6 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) err_cq_table_free: hns_roce_cleanup_cq_table(hr_dev); - -err_mr_table_free: hns_roce_cleanup_mr_table(hr_dev); err_pd_table_free: -- 2.8.1

3 2

[PATCH mm/zswap 0/2] Fix the compatibility of zsmalloc and zswap
by Tian Tao 25 Dec '20

25 Dec '20

patch #1 add a flag to zpool, then zswap used to determine if zpool drivers such as zbud/z3fold/zsmalloc whether can sleep in atoimc context. patch #2 set flag sleep_mapped to true indicates that zbud/z3fold can sleep in atomic context. zsmalloc didin't support sleep in atomic context, so not set that flag to true. Tian Tao (2): mm/zswap: add the flag can_sleep_mapped mm: set the sleep_mapped to true include/linux/zpool.h | 3 +++ mm/z3fold.c | 1 + mm/zbud.c | 1 + mm/zpool.c | 13 +++++++++++++ mm/zswap.c | 27 ++++++++++++++++++++++++--- 5 files changed, 42 insertions(+), 3 deletions(-) -- 2.7.4

1 2

Test
by John Garry 22 Dec '20

22 Dec '20

This is just a test, and I can imagine that we will have more of the same...

1 0

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Linuxarm