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[PATCH] genirq/msi: Make sure early activation of all PCI MSIs
by Shameer Kolothum 23 Jan '21

23 Jan '21

We currently do early activation of MSI irqs for PCI/MSI based on the MSI_FLAG_ACTIVATE_EARLY flag. Though this activates all the allocated MSIs in the case of MSI-X, it only does so for the base irq in the case of MSI. This is because, for MSI, there is only one msi_desc entry for all the 32 irqs it can support and the current implementation iterates over the msi entries and ends up activating the base irq only. The above creates an issue on platforms where the msi controller supports direct injection of vLPIs(eg: ARM GICv4 ITS). On these platforms, upon irq activation, ITS driver maps the event to an ITT entry. And for Guest pass-through to work, early mapping of all the dev MSI vectors is required. Otherwise, the vfio irq bypass manager registration will fail. eg, On a HiSilicon D06 platform with GICv4 enabled, Guest boot with zip dev pass-through reports, "vfio-pci 0000:75:00.1: irq bypass producer (token 0000000006e5176a) registration fails: 66311" and Guest boot fails. This is traced to, kvm_arch_irq_bypass_add_producer kvm_vgic_v4_set_forwarding vgic_its_resolve_lpi --> returns E_ITS_INT_UNMAPPED_INTERRUPT Hence make sure we activate all the irqs for both MSI and MSI-x cases. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi(a)huawei.com> --- It is unclear to me whether not performing the early activation of all MSI irqs was deliberate and has consequences on any other platforms. Please let me know. Thanks, Shameer --- kernel/irq/msi.c | 114 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 90 insertions(+), 24 deletions(-) diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 2c0c4d6d0f83..eec187fc32a9 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -395,6 +395,78 @@ static bool msi_check_reservation_mode(struct irq_domain *domain, return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit; } +static void msi_domain_deactivate_irq(struct irq_domain *domain, int irq) +{ + struct irq_data *irqd; + + irqd = irq_domain_get_irq_data(domain, irq); + if (irqd_is_activated(irqd)) + irq_domain_deactivate_irq(irqd); +} + +static int msi_domain_activate_irq(struct irq_domain *domain, + int irq, bool can_reserve) +{ + struct irq_data *irqd; + + irqd = irq_domain_get_irq_data(domain, irq); + if (!can_reserve) { + irqd_clr_can_reserve(irqd); + if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK) + irqd_set_msi_nomask_quirk(irqd); + } + return irq_domain_activate_irq(irqd, can_reserve); +} + +static int msi_domain_activate_msix_irqs(struct irq_domain *domain, + struct device *dev, bool can_reserve) +{ + struct msi_desc *desc; + int ret, irq; + + for_each_msi_entry(desc, dev) { + irq = desc->irq; + ret = msi_domain_activate_irq(domain, irq, can_reserve); + if (ret) + goto out; + } + return 0; + +out: + for_each_msi_entry(desc, dev) { + if (irq == desc->irq) + break; + msi_domain_deactivate_irq(domain, desc->irq); + } + return ret; +} + +static int msi_domain_activate_msi_irqs(struct irq_domain *domain, + struct device *dev, bool can_reserve) +{ + struct msi_desc *desc; + int i, ret, base, irq; + + desc = first_msi_entry(dev); + base = desc->irq; + + for (i = 0; i < desc->nvec_used; i++) { + irq = base + i; + ret = msi_domain_activate_irq(domain, irq, can_reserve); + if (ret) + goto out; + } + return 0; + +out: + for (i = 0; i < desc->nvec_used; i++) { + if (irq == base + i) + break; + msi_domain_deactivate_irq(domain, base + i); + } + return ret; +} + int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, int nvec) { @@ -443,21 +515,25 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, else dev_dbg(dev, "irq [%d-%d] for MSI\n", virq, virq + desc->nvec_used - 1); - /* - * This flag is set by the PCI layer as we need to activate - * the MSI entries before the PCI layer enables MSI in the - * card. Otherwise the card latches a random msi message. - */ - if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY)) - continue; + } - irq_data = irq_domain_get_irq_data(domain, desc->irq); - if (!can_reserve) { - irqd_clr_can_reserve(irq_data); - if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK) - irqd_set_msi_nomask_quirk(irq_data); - } - ret = irq_domain_activate_irq(irq_data, can_reserve); + /* + * This flag is set by the PCI layer as we need to activate + * the MSI entries before the PCI layer enables MSI in the + * card. Otherwise the card latches a random msi message. + * Early activation is also required when the msi controller + * supports direct injection of virtual LPIs(eg. ARM GICv4 ITS). + * Otherwise, the DevID/EventID -> LPI translation for pass-through + * devices will fail. Make sure we do activate all the allocated + * irqs for MSI and MSI-X cases. + */ + if ((info->flags & MSI_FLAG_ACTIVATE_EARLY)) { + desc = first_msi_entry(dev); + + if (desc->msi_attrib.is_msix) + ret = msi_domain_activate_msix_irqs(domain, dev, can_reserve); + else + ret = msi_domain_activate_msi_irqs(domain, dev, can_reserve); if (ret) goto cleanup; } @@ -475,16 +551,6 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, return 0; cleanup: - for_each_msi_entry(desc, dev) { - struct irq_data *irqd; - - if (desc->irq == virq) - break; - - irqd = irq_domain_get_irq_data(domain, desc->irq); - if (irqd_is_activated(irqd)) - irq_domain_deactivate_irq(irqd); - } msi_domain_free_irqs(domain, dev); return ret; } -- 2.17.1

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[dpdk-dev] [PATCH v2 0/2] Add Hisilicon kunpeng series SoC build
by Chengchang Tang 23 Jan '21

23 Jan '21

Add cross build file for kunpeng series ARM SoC and optimize the compile. Chengchang Tang (2): config: add Hisilicon kunpeng 920 SoC build config: add Hisilicon kunpeng 930 Soc build config/arm/arm64_kunpeng920_linux_gcc | 19 +++++++++++++++ config/arm/arm64_kunpeng930_linux_gcc | 19 +++++++++++++++ config/arm/meson.build | 27 ++++++++++++++++++++++ .../linux_gsg/cross_build_dpdk_for_arm64.rst | 5 ++++ 4 files changed, 70 insertions(+) create mode 100644 config/arm/arm64_kunpeng920_linux_gcc create mode 100644 config/arm/arm64_kunpeng930_linux_gcc -- 2.7.4

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[RFC] some questions for speed_capa usage
by oulijun 23 Jan '21

23 Jan '21

Hi, The 'speed_capa' will be reported in rte_eth_dev_info_get API. How should users use the field? 1) The driver reports only the capabilities supported by the NIC, and users only obtain the capabilities. Maybe, there is a case that a rate bit in 'speed_capa' is not supported by the current transmission medium, such as, copper cable optical modules and optical interface modules. 2) The field is used only to inform users of the speed_capa supported by the current transmission medium. And users set the fixed speed or auto-negotiation by using 'link_speeds' according to the field. According to the existing implementations of all drivers, it seems that both of the above behaviors exist. How should we report and use it? Thanks Lijun Ou

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[PATCH RFC 0/7] RDMA/hns: Add support for Dynamic Context Attachment
by Weihang Li 22 Jan '21

22 Jan '21

The hip09 introduces the DCA(Dynamic Context Attachment) feature which supports many RC QPs to share the WQE buffer in a memory pool. If a QP enables DCA feature, the WQE's buffer will not be allocated when creating but when the users start to post WRs. This will reduce the memory consumption when there are too many QPs are inactive. Xi Wang (7): RDMA/hns: Introduce DCA for RC QP RDMA/hns: Add method for shrinking DCA memory pool RDMA/hns: Configure DCA mode for the userspace QP RDMA/hns: Add method for attaching WQE buffer RDMA/hns: Setup the configuration of WQE addressing to QPC RDMA/hns: Add method to detach WQE buffer RDMA/hns: Add method to query WQE buffer's address drivers/infiniband/hw/hns/Makefile | 2 +- drivers/infiniband/hw/hns/hns_roce_dca.c | 1264 +++++++++++++++++++++++++++ drivers/infiniband/hw/hns/hns_roce_dca.h | 68 ++ drivers/infiniband/hw/hns/hns_roce_device.h | 32 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 223 ++++- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 3 + drivers/infiniband/hw/hns/hns_roce_main.c | 27 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 119 ++- include/uapi/rdma/hns-abi.h | 60 ++ 9 files changed, 1751 insertions(+), 47 deletions(-) create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.c create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.h -- 2.8.1

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[PATCH v2 for-next] RDMA/hns: Add caps flag for UD inline of userspace
by Weihang Li 22 Jan '21

22 Jan '21

HIP09 supports UD inline up to size of 1024 Bytes, the caps flag is got from firmware and passed back to userspace when creating QP. Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- Changes since v1: - Avoid overwriting some fields in set_default_caps(). - Link: https://patchwork.kernel.org/project/linux-rdma/patch/1609810615-50515-1-gi… drivers/infiniband/hw/hns/hns_roce_device.h | 1 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 18 +++++++++++------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 1 + drivers/infiniband/hw/hns/hns_roce_qp.c | 3 +++ include/uapi/rdma/hns-abi.h | 1 + 5 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 55d5386..87716da 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -214,6 +214,7 @@ enum { HNS_ROCE_CAP_FLAG_FRMR = BIT(8), HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), + HNS_ROCE_CAP_FLAG_UD_SQ_INL = BIT(13), HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), HNS_ROCE_CAP_FLAG_STASH = BIT(17), }; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 833e1f2..1454cd9 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1800,7 +1800,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; - caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; caps->num_uars = HNS_ROCE_V2_UAR_NUM; caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; @@ -1817,7 +1816,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; - caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; @@ -1825,7 +1823,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; - caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; caps->reserved_lkey = 0; caps->reserved_pds = 0; @@ -1871,11 +1868,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; caps->pkey_table_len[0] = 1; - caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; - caps->aeqe_size = HNS_ROCE_AEQE_SIZE; - caps->ceqe_size = HNS_ROCE_CEQE_SIZE; caps->local_ca_ack_delay = 0; caps->max_mtu = IB_MTU_4096; @@ -1897,7 +1891,6 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->cqc_timer_buf_pg_sz = 0; caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; - caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; caps->sccc_ba_pg_sz = 0; caps->sccc_buf_pg_sz = 0; caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; @@ -1916,6 +1909,16 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->gmv_buf_pg_sz = 0; caps->gid_table_len[0] = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); + caps->flags |= HNS_ROCE_CAP_FLAG_UD_SQ_INL; + caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INL_EXT; + } else { + caps->aeqe_size = HNS_ROCE_AEQE_SIZE; + caps->ceqe_size = HNS_ROCE_CEQE_SIZE; + caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; + caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; + caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; + caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; + caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; } } @@ -5084,6 +5087,7 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, qp_attr->cur_qp_state = qp_attr->qp_state; qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; + qp_attr->cap.max_inline_data = hr_qp->max_inline_data; if (!ibqp->uobject) { qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index bdaccf8..ab685a4 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -61,6 +61,7 @@ #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 +#define HNS_ROCE_V2_MAX_SQ_INL_EXT 0x400 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32 #define HNS_ROCE_V2_UAR_NUM 256 #define HNS_ROCE_V2_PHY_UAR_NUM 1 diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index d8e2fe5..b19fcbd 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -1020,6 +1020,9 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, } if (udata) { + if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_UD_SQ_INL) + resp.cap_flags |= HNS_ROCE_QP_CAP_UD_SQ_INL; + ret = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); if (ret) { diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h index 90b739d..79dba94 100644 --- a/include/uapi/rdma/hns-abi.h +++ b/include/uapi/rdma/hns-abi.h @@ -77,6 +77,7 @@ enum hns_roce_qp_cap_flags { HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0, HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1, HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2, + HNS_ROCE_QP_CAP_UD_SQ_INL = 1 << 3, }; struct hns_roce_ib_create_qp_resp { -- 2.8.1

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[PATCH] perf metricgroup: Fix for metrics containing duration_time
by John Garry 22 Jan '21

22 Jan '21

Metrics containing duration_time cause a segfault: $./perf stat -v -M L1D_Cache_Fill_BW sleep 1 Using CPUID GenuineIntel-6-3D-4 metric expr 64 * l1d.replacement / 1000000000 / duration_time for L1D_Cache_Fill_BW found event duration_time found event l1d.replacement adding {l1d.replacement}:W,duration_time l1d.replacement -> cpu/umask=0x1,(null)=0x1e8483,event=0x51/ Segmentation fault In commit c2337d67199a ("perf metricgroup: Fix metrics using aliases covering multiple PMUs"), the logic in find_evsel_group() when iter'ing events was changed to not only select events in same group, but also for aliased PMUs. Checking whether events were for aliased PMUs was done by comparing the event PMU name. This was not safe for duration_time event, which has no associated PMU (and no PMU name), so fix by checking if the event PMU name is set also. Fixes: c2337d67199a ("perf metricgroup: Fix metrics using aliases covering multiple PMUs") Reported-by: Joakim Zhang <qiangqing.zhang(a)nxp.com> Signed-off-by: John Garry <john.garry(a)huawei.com> diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 2e60ee170abc..e6d3452031e5 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -162,6 +162,14 @@ static bool contains_event(struct evsel **metric_events, int num_events, return false; } +static bool evsel_same_pmu(struct evsel *ev1, struct evsel *ev2) +{ + if (!ev1->pmu_name || !ev2->pmu_name) + return false; + + return !strcmp(ev1->pmu_name, ev2->pmu_name); +} + /** * Find a group of events in perf_evlist that correspond to those from a parsed * metric expression. Note, as find_evsel_group is called in the same order as @@ -280,8 +288,7 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist, */ if (!has_constraint && ev->leader != metric_events[i]->leader && - !strcmp(ev->leader->pmu_name, - metric_events[i]->leader->pmu_name)) + evsel_same_pmu(ev->leader, metric_events[i]->leader)) break; if (!strcmp(metric_events[i]->name, ev->name)) { set_bit(ev->idx, evlist_used); -- 2.26.2

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[PATCH for-next 0/3] RDMA/hns: Refactor codes about memory
by Weihang Li 22 Jan '21

22 Jan '21

This series refactors memory related codes, including MR, MTR(Memory Translate Region) and MPT(Memory Protection Table). Lang Cheng (2): RDMA/hns: Optimize the MR registration process RDMA/hns: Use new interface to set MPT related fields Xi Wang (1): RDMA/hns: Refactor the MTR creation flow drivers/infiniband/hw/hns/hns_roce_common.h | 22 ++ drivers/infiniband/hw/hns/hns_roce_cq.c | 1 - drivers/infiniband/hw/hns/hns_roce_device.h | 4 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 77 +++--- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 39 +++ drivers/infiniband/hw/hns/hns_roce_mr.c | 404 +++++++++++----------------- drivers/infiniband/hw/hns/hns_roce_qp.c | 1 - drivers/infiniband/hw/hns/hns_roce_srq.c | 2 - 8 files changed, 258 insertions(+), 292 deletions(-) -- 2.8.1

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[PATCH] mm/zswap: fix variable 'entry' is uninitialized when used
by Tian Tao 21 Jan '21

21 Jan '21

the entry has not been initialized when it is used, so allocate PAGE_SIZE Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> Reported-by: kernel test robot <lkp(a)intel.com> --- mm/zswap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/zswap.c b/mm/zswap.c index 6e0bb61..4b7b6ad 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -944,7 +944,7 @@ static int zswap_writeback_entry(struct zpool *pool, unsigned long handle) if (!zpool_can_sleep_mapped(pool)) { - tmp = kmalloc(entry->length, GFP_ATOMIC); + tmp = kmalloc(PAGE_SIZE, GFP_ATOMIC); if (!tmp) return -ENOMEM; } -- 2.7.4

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[PATCH net-next] net: hns3: debugfs add dump tm info of nodes, priority and qset
by Huazhong Tan 21 Jan '21

21 Jan '21

From: Guangbin Huang <huangguangbin2(a)huawei.com> To increase methods to dump more tm info, adds three debugfs commands to dump tm info of nodes, priority and qset. And a new tm file of debugfs is created for only dumping tm info. Unlike previous debugfs commands, to dump each tm information, user needs to enter two commands now. The first command writes parameters to tm and the second command reads info from tm. For examples, to dump tm info of priority 0, user needs to enter follow two commands: 1. echo dump priority 0 > tm 2. cat tm The reason for adding new tm file is because we accepted Jakub Kicinski's opinion as link https://lkml.org/lkml/2020/9/29/2101. And in order to avoid generating too many files, we implement write ops to allow user to input parameters. However, If there are two or more users concurrently write parameters to tm, parameters of the latest command will overwrite previous commands, this concurrency problem will confuse users, but now there is no good method to fix it. Signed-off-by: Guangbin Huang <huangguangbin2(a)huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong(a)huawei.com> --- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 9 + drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 118 ++++++++++ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 6 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 1 + .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 251 +++++++++++++++++++++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 1 + .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 23 ++ 8 files changed, 411 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index a7daf6d..39b8ac7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -247,6 +247,10 @@ struct hnae3_vector_info { int vector; }; +enum hnae3_dbg_module_type { + HNAE3_DBG_MODULE_TYPE_TM, +}; + #define HNAE3_RING_TYPE_B 0 #define HNAE3_RING_TYPE_TX 0 #define HNAE3_RING_TYPE_RX 1 @@ -465,6 +469,8 @@ struct hnae3_ae_dev { * Delete clsflower rule * cls_flower_active * Check if any cls flower rule exist + * dbg_read_cmd + * Execute debugfs read command. */ struct hnae3_ae_ops { int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); @@ -620,6 +626,8 @@ struct hnae3_ae_ops { int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, u16 flow_id, struct flow_keys *fkeys); int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf); + int (*dbg_read_cmd)(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len); pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); bool (*get_hw_reset_stat)(struct hnae3_handle *handle); bool (*ae_dev_resetting)(struct hnae3_handle *handle); @@ -757,6 +765,7 @@ struct hnae3_handle { u8 netdev_flags; struct dentry *hnae3_dbgfs; + int dbgfs_type; /* Network interface message level enabled bits */ u32 msg_enable; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c index 9d4e9c0..e2b6924 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c @@ -12,6 +12,10 @@ static struct dentry *hns3_dbgfs_root; +#define HNS3_HELP_INFO "help" + +#define HNS3_DBG_MODULE_NAME_TM "tm" + static int hns3_dbg_queue_info(struct hnae3_handle *h, const char *cmd_buf) { @@ -338,6 +342,23 @@ static void hns3_dbg_help(struct hnae3_handle *h) dev_info(&h->pdev->dev, "%s", printf_buf); } +static void hns3_dbg_tm_help(struct hnae3_handle *h, char *buf, int len) +{ + struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + int pos; + + pos = scnprintf(buf, len, "available commands:\n"); + + if (!hns3_is_phys_func(h->pdev)) + return; + + if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) + pos += scnprintf(buf + pos, len - pos, "dump nodes\n"); + + pos += scnprintf(buf + pos, len - pos, "dump priority <pri id>\n"); + pos += scnprintf(buf + pos, len - pos, "dump qset <qset id>\n"); +} + static void hns3_dbg_dev_caps(struct hnae3_handle *h) { struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); @@ -484,6 +505,93 @@ static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer, return count; } +static ssize_t hns3_dbg_tm_read(struct file *filp, char __user *buffer, + size_t count, loff_t *ppos) +{ + struct hnae3_handle *handle = filp->private_data; + const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hns3_nic_priv *priv = handle->priv; + char *cmd_buf, *read_buf; + ssize_t size = 0; + int ret = 0; + + if (strncmp(filp->f_path.dentry->d_iname, HNS3_DBG_MODULE_NAME_TM, + strlen(HNS3_DBG_MODULE_NAME_TM)) != 0) + return -EINVAL; + + if (!priv->dbg_in_msg.tm) + return -EINVAL; + + read_buf = kzalloc(HNS3_DBG_READ_LEN, GFP_KERNEL); + if (!read_buf) + return -ENOMEM; + + cmd_buf = priv->dbg_in_msg.tm; + handle->dbgfs_type = HNAE3_DBG_MODULE_TYPE_TM; + + if (strncmp(cmd_buf, HNS3_HELP_INFO, strlen(HNS3_HELP_INFO)) == 0) + hns3_dbg_tm_help(handle, read_buf, HNS3_DBG_READ_LEN); + else if (ops->dbg_read_cmd) + ret = ops->dbg_read_cmd(handle, cmd_buf, read_buf, + HNS3_DBG_READ_LEN); + + if (ret) { + dev_info(priv->dev, "unknown command\n"); + goto out; + } + + size = simple_read_from_buffer(buffer, count, ppos, read_buf, + strlen(read_buf)); +out: + kfree(read_buf); + return size; +} + +static ssize_t hns3_dbg_tm_write(struct file *filp, const char __user *buffer, + size_t count, loff_t *ppos) +{ + struct hnae3_handle *handle = filp->private_data; + struct hns3_nic_priv *priv = handle->priv; + char *cmd_buf, *cmd_buf_tmp; + int uncopied_bytes; + + if (*ppos != 0) + return 0; + + /* Judge if the instance is being reset. */ + if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || + test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) + return 0; + + if (count > HNS3_DBG_WRITE_LEN) + return -ENOSPC; + + kfree(priv->dbg_in_msg.tm); + priv->dbg_in_msg.tm = NULL; + + cmd_buf = kzalloc(count + 1, GFP_KERNEL); + if (!cmd_buf) + return count; + + uncopied_bytes = copy_from_user(cmd_buf, buffer, count); + if (uncopied_bytes) { + kfree(cmd_buf); + return -EFAULT; + } + + cmd_buf[count] = '\0'; + + cmd_buf_tmp = strchr(cmd_buf, '\n'); + if (cmd_buf_tmp) { + *cmd_buf_tmp = '\0'; + count = cmd_buf_tmp - cmd_buf + 1; + } + + priv->dbg_in_msg.tm = cmd_buf; + + return count; +} + static const struct file_operations hns3_dbg_cmd_fops = { .owner = THIS_MODULE, .open = simple_open, @@ -491,6 +599,13 @@ static const struct file_operations hns3_dbg_cmd_fops = { .write = hns3_dbg_cmd_write, }; +static const struct file_operations hns3_dbg_tm_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = hns3_dbg_tm_read, + .write = hns3_dbg_tm_write, +}; + void hns3_dbg_init(struct hnae3_handle *handle) { const char *name = pci_name(handle->pdev); @@ -499,6 +614,9 @@ void hns3_dbg_init(struct hnae3_handle *handle) debugfs_create_file("cmd", 0600, handle->hnae3_dbgfs, handle, &hns3_dbg_cmd_fops); + + debugfs_create_file(HNS3_DBG_MODULE_NAME_TM, 0600, handle->hnae3_dbgfs, + handle, &hns3_dbg_tm_fops); } void hns3_dbg_uninit(struct hnae3_handle *handle) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h index 0a7b606..76dd30d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h @@ -490,6 +490,10 @@ struct hns3_enet_tqp_vector { unsigned long last_jiffies; } ____cacheline_internodealigned_in_smp; +struct hns3_dbg_input_msg { + char *tm; +}; + struct hns3_nic_priv { struct hnae3_handle *ae_handle; struct net_device *netdev; @@ -510,6 +514,8 @@ struct hns3_nic_priv { struct hns3_enet_coalesce tx_coal; struct hns3_enet_coalesce rx_coal; + + struct hns3_dbg_input_msg dbg_in_msg; }; union l3_hdr_info { diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h index edfadb5..f861bdb 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h @@ -160,6 +160,7 @@ enum hclge_opcode_type { HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, + HCLGE_OPC_TM_NODES = 0x0816, HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, HCLGE_OPC_QSET_DFX_STS = 0x0844, HCLGE_OPC_PRI_DFX_STS = 0x0845, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c index 8f6dea5..1f13a5b 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c @@ -800,6 +800,224 @@ static void hclge_dbg_dump_tm_map(struct hclge_dev *hdev, cmd, ret); } +static void hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len) +{ + struct hclge_tm_nodes_cmd *nodes; + struct hclge_desc desc; + int pos = 0; + int ret; + + if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) { + dev_err(&hdev->pdev->dev, "unsupported command!\n"); + return; + } + + hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to dump tm nodes, ret = %d\n", ret); + return; + } + + nodes = (struct hclge_tm_nodes_cmd *)desc.data; + + pos += scnprintf(buf + pos, len - pos, "PG base_id: %u\n", + nodes->pg_base_id); + pos += scnprintf(buf + pos, len - pos, "PG number: %u\n", + nodes->pg_num); + pos += scnprintf(buf + pos, len - pos, "PRI base_id: %u\n", + nodes->pri_base_id); + pos += scnprintf(buf + pos, len - pos, "PRI number: %u\n", + nodes->pri_num); + pos += scnprintf(buf + pos, len - pos, "QSET base_id: %u\n", + le16_to_cpu(nodes->qset_base_id)); + pos += scnprintf(buf + pos, len - pos, "QSET number: %u\n", + le16_to_cpu(nodes->qset_num)); + pos += scnprintf(buf + pos, len - pos, "QUEUE base_id: %u\n", + le16_to_cpu(nodes->queue_base_id)); + pos += scnprintf(buf + pos, len - pos, "QUEUE number: %u\n", + le16_to_cpu(nodes->queue_num)); +} + +static int hclge_dbg_dump_tm_pri_sch(struct hclge_dev *hdev, u8 pri_id, + char *buf, int len) +{ + struct hclge_priority_weight_cmd *priority_weight; + struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode; + enum hclge_opcode_type cmd; + struct hclge_desc desc; + int pos = 0; + int ret; + + cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + pri_sch_mode = (struct hclge_pri_sch_mode_cfg_cmd *)desc.data; + pri_sch_mode->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_sch_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "PRI schedule mode: %s\n", + (pri_sch_mode->sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK) ? + "dwrr" : "sp"); + + cmd = HCLGE_OPC_TM_PRI_WEIGHT; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + priority_weight = (struct hclge_priority_weight_cmd *)desc.data; + priority_weight->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_sch_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "PRI dwrr: %u\n", + priority_weight->dwrr); + + return pos; + +err_tm_pri_sch_cmd_send: + dev_err(&hdev->pdev->dev, + "failed to dump tm priority(0x%x), ret = %d\n", cmd, ret); + + return pos; +} + +static void hclge_dbg_dump_tm_pri_shaping(struct hclge_dev *hdev, u8 pri_id, + char *buf, int len) +{ + struct hclge_pri_shapping_cmd *shap_cfg_cmd; + u8 ir_u, ir_b, ir_s, bs_b, bs_s; + enum hclge_opcode_type cmd; + struct hclge_desc desc; + u32 shapping_para; + int pos = 0; + int ret; + + cmd = HCLGE_OPC_TM_PRI_C_SHAPPING; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; + shap_cfg_cmd->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_shaping_cmd_send; + + shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para); + ir_b = hclge_tm_get_field(shapping_para, IR_B); + ir_u = hclge_tm_get_field(shapping_para, IR_U); + ir_s = hclge_tm_get_field(shapping_para, IR_S); + bs_b = hclge_tm_get_field(shapping_para, BS_B); + bs_s = hclge_tm_get_field(shapping_para, BS_S); + pos += scnprintf(buf + pos, len - pos, + "PRI_C ir_b:%u ir_u:%u ir_s:%u bs_b:%u bs_s:%u\n", + ir_b, ir_u, ir_s, bs_b, bs_s); + pos += scnprintf(buf + pos, len - pos, "PRI_C flag: %#x\n", + shap_cfg_cmd->flag); + pos += scnprintf(buf + pos, len - pos, "PRI_C pri_rate: %u(Mbps)\n", + le32_to_cpu(shap_cfg_cmd->pri_rate)); + + cmd = HCLGE_OPC_TM_PRI_P_SHAPPING; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; + shap_cfg_cmd->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_pri_shaping_cmd_send; + + shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para); + ir_b = hclge_tm_get_field(shapping_para, IR_B); + ir_u = hclge_tm_get_field(shapping_para, IR_U); + ir_s = hclge_tm_get_field(shapping_para, IR_S); + bs_b = hclge_tm_get_field(shapping_para, BS_B); + bs_s = hclge_tm_get_field(shapping_para, BS_S); + pos += scnprintf(buf + pos, len - pos, + "PRI_P ir_b:%u ir_u:%u ir_s:%u bs_b:%u bs_s:%u\n", + ir_b, ir_u, ir_s, bs_b, bs_s); + pos += scnprintf(buf + pos, len - pos, "PRI_P flag: %#x\n", + shap_cfg_cmd->flag); + pos += scnprintf(buf + pos, len - pos, "PRI_P pri_rate: %u(Mbps)\n", + le32_to_cpu(shap_cfg_cmd->pri_rate)); + + return; + +err_tm_pri_shaping_cmd_send: + dev_err(&hdev->pdev->dev, + "failed to dump tm priority(0x%x), ret = %d\n", cmd, ret); +} + +static void hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, const char *cmd_buf, + char *buf, int len) +{ + int ret, pos; + u8 pri_id; + + ret = kstrtou8(cmd_buf, 0, &pri_id); + pri_id = (ret != 0) ? 0 : pri_id; + + pos = scnprintf(buf, len, "priority id: %u\n", pri_id); + + pos += hclge_dbg_dump_tm_pri_sch(hdev, pri_id, buf + pos, len - pos); + hclge_dbg_dump_tm_pri_shaping(hdev, pri_id, buf + pos, len - pos); +} + +static void hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, const char *cmd_buf, + char *buf, int len) +{ + struct hclge_qs_sch_mode_cfg_cmd *qs_sch_mode; + struct hclge_qs_weight_cmd *qs_weight; + struct hclge_qs_to_pri_link_cmd *map; + enum hclge_opcode_type cmd; + struct hclge_desc desc; + int ret, pos; + u16 qset_id; + + ret = kstrtou16(cmd_buf, 0, &qset_id); + qset_id = (ret != 0) ? 0 : qset_id; + + pos = scnprintf(buf, len, "qset id: %u\n", qset_id); + + cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK; + map = (struct hclge_qs_to_pri_link_cmd *)desc.data; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + map->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_qset_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "QS map pri id: %u\n", + map->priority); + pos += scnprintf(buf + pos, len - pos, "QS map link_vld: %u\n", + map->link_vld); + + cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + qs_sch_mode = (struct hclge_qs_sch_mode_cfg_cmd *)desc.data; + qs_sch_mode->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_qset_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "QS schedule mode: %s\n", + (qs_sch_mode->sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK) ? + "dwrr" : "sp"); + + cmd = HCLGE_OPC_TM_QS_WEIGHT; + hclge_cmd_setup_basic_desc(&desc, cmd, true); + qs_weight = (struct hclge_qs_weight_cmd *)desc.data; + qs_weight->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + goto err_tm_qset_cmd_send; + + pos += scnprintf(buf + pos, len - pos, "QS dwrr: %u\n", + qs_weight->dwrr); + + return; + +err_tm_qset_cmd_send: + dev_err(&hdev->pdev->dev, "failed to dump tm qset(0x%x), ret = %d\n", + cmd, ret); +} + static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev) { struct hclge_cfg_pause_param_cmd *pause_param; @@ -1591,3 +1809,36 @@ int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf) return 0; } + +static int hclge_dbg_read_cmd_tm(struct hnae3_handle *handle, + const char *cmd_buf, char *buf, int len) +{ +#define DUMP_TM_NODE "dump nodes" +#define DUMP_TM_PRI "dump priority" +#define DUMP_TM_QSET "dump qset" + + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + if (strncmp(cmd_buf, DUMP_TM_NODE, strlen(DUMP_TM_NODE)) == 0) + hclge_dbg_dump_tm_nodes(hdev, buf, len); + else if (strncmp(cmd_buf, DUMP_TM_PRI, strlen(DUMP_TM_PRI)) == 0) + hclge_dbg_dump_tm_pri(hdev, &cmd_buf[sizeof(DUMP_TM_PRI)], + buf, len); + else if (strncmp(cmd_buf, DUMP_TM_QSET, strlen(DUMP_TM_QSET)) == 0) + hclge_dbg_dump_tm_qset(hdev, &cmd_buf[sizeof(DUMP_TM_QSET)], + buf, len); + else + return -EINVAL; + + return 0; +} + +int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len) +{ + if (handle->dbgfs_type == HNAE3_DBG_MODULE_TYPE_TM) + return hclge_dbg_read_cmd_tm(handle, cmd_buf, buf, len); + + return -EINVAL; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index c242883..16ccb1a 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -11850,6 +11850,7 @@ static const struct hnae3_ae_ops hclge_ops = { .enable_fd = hclge_enable_fd, .add_arfs_entry = hclge_add_fd_entry_by_arfs, .dbg_run_cmd = hclge_dbg_run_cmd, + .dbg_read_cmd = hclge_dbg_read_cmd, .handle_hw_ras_error = hclge_handle_hw_ras_error, .get_hw_reset_stat = hclge_get_hw_reset_stat, .ae_dev_resetting = hclge_ae_dev_resetting, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index ca46bc9..32e5f82 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -1006,6 +1006,8 @@ int hclge_vport_start(struct hclge_vport *vport); void hclge_vport_stop(struct hclge_vport *vport); int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf); +int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len); u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); int hclge_notify_client(struct hclge_dev *hdev, enum hnae3_reset_notify_type type); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h index 5498d73..4fd7e4f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h @@ -65,6 +65,18 @@ struct hclge_priority_weight_cmd { u8 dwrr; }; +struct hclge_pri_sch_mode_cfg_cmd { + u8 pri_id; + u8 rev[3]; + u8 sch_mode; +}; + +struct hclge_qs_sch_mode_cfg_cmd { + __le16 qs_id; + u8 rev[2]; + u8 sch_mode; +}; + struct hclge_qs_weight_cmd { __le16 qs_id; u8 dwrr; @@ -173,6 +185,17 @@ struct hclge_shaper_ir_para { u8 ir_s; /* IR_S parameter of IR shaper */ }; +struct hclge_tm_nodes_cmd { + u8 pg_base_id; + u8 pri_base_id; + __le16 qset_base_id; + __le16 queue_base_id; + u8 pg_num; + u8 pri_num; + __le16 qset_num; + __le16 queue_num; +}; + #define hclge_tm_set_field(dest, string, val) \ hnae3_set_field((dest), \ (HCLGE_TM_SHAP_##string##_MSK), \ -- 2.7.4

2 6

[PATCH v2 0/8] rasdaemon: add support for memory_failure events,
by Shiju Jose 20 Jan '21

20 Jan '21

Add support for the memory_failure trace event in the rasdaemon and add improvements & support for the vendor specific errors in the util/ras-mc-ctl.in. Changes: v1 -> v2 1. Fix the feedback by Mauro for the fix patch for the exception in the ras-mc-ctl.in. 2. Rebased and grouped the previous v1 rasdaemon patches posted. Shiju Jose (8): rasdaemon: add support for memory_failure events rasdaemon: ras-mc-ctl: Modify ARM processor error summary log rasdaemon: ras-mc-ctl: Add memory failure events rasdaemon: ras-mc-ctl: Fix for exception when an event is not enabled rasdaemon: ras-mc-ctl: Add support for the vendor-specific errors rasdaemon: ras-mc-ctl: Add support for HiSilicon Kunpeng920 errors rasdaemon: ras-mc-ctl: Add support for HiSilicon Kunpeng9xx common errors rasdaemon: Modify confiure.ac for Hisilicon Kunpeng errors .travis.yml | 2 +- Makefile.am | 7 +- configure.ac | 20 +- ras-events.c | 15 + ras-events.h | 1 + ras-memory-failure-handler.c | 179 +++++++++ ras-memory-failure-handler.h | 25 ++ ras-record.c | 70 ++++ ras-record.h | 13 + ras-report.c | 68 ++++ ras-report.h | 2 + util/ras-mc-ctl.in | 737 +++++++++++++++++++++++++---------- 12 files changed, 927 insertions(+), 212 deletions(-) create mode 100644 ras-memory-failure-handler.c create mode 100644 ras-memory-failure-handler.h -- 2.17.1

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