在 2021/3/23 16:07, Ruifeng Wang 写道:
-----Original Message----- From: dev dev-bounces@dpdk.org On Behalf Of Lijun Ou Sent: Wednesday, March 10, 2021 9:36 AM To: thomas@monjalon.net; ferruh.yigit@intel.com Cc: dev@dpdk.org; linuxarm@openeuler.org Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon kunpeng920 implementer
Here addes Kunpeng920 config back which was deleted.
Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous variables")
Signed-off-by: Chengchang Tang tangchengchang@huawei.com Signed-off-by: Lijun Ou oulijun@huawei.com
V1->V2:
- rewrite patch title.
- split the patch into two.
config/arm/meson.build | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/config/arm/meson.build b/config/arm/meson.build index 00bc461..3826900 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -133,6 +133,25 @@ implementer_cavium = { } }
+implementer_hisilicon = {
- 'description': 'Hisilicon',
- 'flags': [
['RTE_USE_C11_MEM_MODEL', true],['RTE_CACHE_LINE_SIZE', 128],Just want to double check. One Kunpeng920 box I can access have cache line size 64B.
I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For kunpeng920, L1/L2 cache size is 64B，L3 is 128B
Thanks.
['RTE_MAX_NUMA_NODES', 4]- ],
- 'part_number_config': {
'0xd01': {'machine_args': ['-march=armv8.2-a+crypto','-mtune=tsv110'],'flag': [['RTE_MACHINE', '"kunpeng920"'],['RTE_MAX_LCORE', 128],['RTE_ARM_FEATURE_ATOMICS', true]]}- }
+}
- implementer_ampere = { 'description': 'Ampere Computing', 'flags': [
@@ -190,6 +209,7 @@ implementers = { 'generic': implementer_generic, '0x41': implementer_arm, '0x43': implementer_cavium,
- '0x48': implementer_hisilicon, '0x50': implementer_ampere, '0x51': implementer_qualcomm, '0x56': implementer_marvell,
-- 2.7.4
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