From: Huisong Li lihuisong@huawei.com

pkt_len_errors and l2_errors in Rx datapath indicate that driver needs to discard received packets. And driver does not discard packets for l3/l4/ol3/ol4_csum_errors in Rx datapath and others stats in Tx datapatch. Therefore, it is necessary for improving code readability and maintainability to encapsulate error stats and dfx stats.

Signed-off-by: Huisong Li lihuisong@huawei.com Signed-off-by: Lijun Ou oulijun@huawei.com --- drivers/net/hns3/hns3_rxtx.c | 30 ++--- drivers/net/hns3/hns3_rxtx.h | 134 ++++++++++--------- drivers/net/hns3/hns3_rxtx_vec_neon.h | 2 +- drivers/net/hns3/hns3_stats.c | 243 ++++++++++++++++++++++------------ drivers/net/hns3/hns3_stats.h | 9 +- 5 files changed, 251 insertions(+), 167 deletions(-)

diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 0badfc9..3d5f74f 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -1792,12 +1792,8 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, rxq->io_head_reg = (volatile void *)((char *)rxq->io_base + HNS3_RING_RX_HEAD_REG); rxq->rx_buf_len = rx_buf_size; - rxq->l2_errors = 0; - rxq->pkt_len_errors = 0; - rxq->l3_csum_errors = 0; - rxq->l4_csum_errors = 0; - rxq->ol3_csum_errors = 0; - rxq->ol4_csum_errors = 0; + memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats)); + memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats));

/* CRC len set here is used for amending packet length */ if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) @@ -2622,12 +2618,8 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, HNS3_RING_TX_TAIL_REG); txq->min_tx_pkt_len = hw->min_tx_pkt_len; txq->tso_mode = hw->tso_mode; - txq->over_length_pkt_cnt = 0; - txq->exceed_limit_bd_pkt_cnt = 0; - txq->exceed_limit_bd_reassem_fail = 0; - txq->unsupported_tunnel_pkt_cnt = 0; - txq->queue_full_cnt = 0; - txq->pkt_padding_fail_cnt = 0; + memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats)); + rte_spinlock_lock(&hw->lock); dev->data->tx_queues[idx] = txq; rte_spinlock_unlock(&hw->lock); @@ -3350,7 +3342,7 @@ hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id, if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) { /* Fill in tunneling parameters if necessary */ if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) { - txq->unsupported_tunnel_pkt_cnt++; + txq->dfx_stats.unsupported_tunnel_pkt_cnt++; return -EINVAL; }

@@ -3380,17 +3372,17 @@ hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg, * driver support, the packet will be ignored. */ if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) { - txq->over_length_pkt_cnt++; + txq->dfx_stats.over_length_pkt_cnt++; return -EINVAL; }

max_non_tso_bd_num = txq->max_non_tso_bd_num; if (unlikely(nb_buf > max_non_tso_bd_num)) { - txq->exceed_limit_bd_pkt_cnt++; + txq->dfx_stats.exceed_limit_bd_pkt_cnt++; ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt, max_non_tso_bd_num); if (ret) { - txq->exceed_limit_bd_reassem_fail++; + txq->dfx_stats.exceed_limit_bd_reassem_fail++; return ret; } *m_seg = new_pkt; @@ -3528,7 +3520,7 @@ hns3_xmit_pkts_simple(void *tx_queue, nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts); if (unlikely(nb_pkts == 0)) { if (txq->tx_bd_ready == 0) - txq->queue_full_cnt++; + txq->dfx_stats.queue_full_cnt++; return 0; }

@@ -3580,7 +3572,7 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) nb_buf = tx_pkt->nb_segs;

if (nb_buf > txq->tx_bd_ready) { - txq->queue_full_cnt++; + txq->dfx_stats.queue_full_cnt++; if (nb_tx == 0) return 0;

@@ -3601,7 +3593,7 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) rte_pktmbuf_pkt_len(tx_pkt); appended = rte_pktmbuf_append(tx_pkt, add_len); if (appended == NULL) { - txq->pkt_padding_fail_cnt++; + txq->dfx_stats.pkt_padding_fail_cnt++; break; }

diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 6538848..8a0c981 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -266,6 +266,18 @@ struct hns3_entry { struct rte_mbuf *mbuf; };

+struct hns3_rx_dfx_stats { + uint64_t l3_csum_errors; + uint64_t l4_csum_errors; + uint64_t ol3_csum_errors; + uint64_t ol4_csum_errors; +}; + +struct hns3_rx_bd_errors_stats { + uint64_t l2_errors; + uint64_t pkt_len_errors; +}; + struct hns3_rx_queue { void *io_base; volatile void *io_head_reg; @@ -312,12 +324,10 @@ struct hns3_rx_queue { bool pvid_sw_discard_en; bool enabled; /* indicate if Rx queue has been enabled */

- uint64_t l2_errors; - uint64_t pkt_len_errors; - uint64_t l3_csum_errors; - uint64_t l4_csum_errors; - uint64_t ol3_csum_errors; - uint64_t ol4_csum_errors; + /* DFX statistics that driver does not need to discard packets */ + struct hns3_rx_dfx_stats dfx_stats; + /* Error statistics that driver needs to discard packets */ + struct hns3_rx_bd_errors_stats err_stats;

struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM]; uint16_t bulk_mbuf_num; @@ -328,6 +338,57 @@ struct hns3_rx_queue { struct rte_mbuf fake_mbuf; /* fake mbuf used with vector rx */ };

+/* + * The following items are used for the abnormal errors statistics in + * the Tx datapath. When upper level application calls the + * rte_eth_tx_burst API function to send multiple packets at a time with + * burst mode based on hns3 network engine, there are some abnormal + * conditions that cause the driver to fail to operate the hardware to + * send packets correctly. + * Note: When using burst mode to call the rte_eth_tx_burst API function + * to send multiple packets at a time. When the first abnormal error is + * detected, add one to the relevant error statistics item, and then + * exit the loop of sending multiple packets of the function. That is to + * say, even if there are multiple packets in which abnormal errors may + * be detected in the burst, the relevant error statistics in the driver + * will only be increased by one. + * The detail description of the Tx abnormal errors statistic items as + * below: + * - over_length_pkt_cnt + * Total number of greater than HNS3_MAX_FRAME_LEN the driver + * supported. + * + * - exceed_limit_bd_pkt_cnt + * Total number of exceeding the hardware limited bd which process + * a packet needed bd numbers. + * + * - exceed_limit_bd_reassem_fail + * Total number of exceeding the hardware limited bd fail which + * process a packet needed bd numbers and reassemble fail. + * + * - unsupported_tunnel_pkt_cnt + * Total number of unsupported tunnel packet. The unsupported tunnel + * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet + * with MPLS-in-UDP RFC 7510 header. + * + * - queue_full_cnt + * Total count which the available bd numbers in current bd queue is + * less than the bd numbers with the pkt process needed. + * + * - pkt_padding_fail_cnt + * Total count which the packet length is less than minimum packet + * length(struct hns3_tx_queue::min_tx_pkt_len) supported by + * hardware in Tx direction and fail to be appended with 0. + */ +struct hns3_tx_dfx_stats { + uint64_t over_length_pkt_cnt; + uint64_t exceed_limit_bd_pkt_cnt; + uint64_t exceed_limit_bd_reassem_fail; + uint64_t unsupported_tunnel_pkt_cnt; + uint64_t queue_full_cnt; + uint64_t pkt_padding_fail_cnt; +}; + struct hns3_tx_queue { void *io_base; volatile void *io_tail_reg; @@ -411,54 +472,7 @@ struct hns3_tx_queue { bool pvid_sw_shift_en; bool enabled; /* indicate if Tx queue has been enabled */

- /* - * The following items are used for the abnormal errors statistics in - * the Tx datapath. When upper level application calls the - * rte_eth_tx_burst API function to send multiple packets at a time with - * burst mode based on hns3 network engine, there are some abnormal - * conditions that cause the driver to fail to operate the hardware to - * send packets correctly. - * Note: When using burst mode to call the rte_eth_tx_burst API function - * to send multiple packets at a time. When the first abnormal error is - * detected, add one to the relevant error statistics item, and then - * exit the loop of sending multiple packets of the function. That is to - * say, even if there are multiple packets in which abnormal errors may - * be detected in the burst, the relevant error statistics in the driver - * will only be increased by one. - * The detail description of the Tx abnormal errors statistic items as - * below: - * - over_length_pkt_cnt - * Total number of greater than HNS3_MAX_FRAME_LEN the driver - * supported. - * - * - exceed_limit_bd_pkt_cnt - * Total number of exceeding the hardware limited bd which process - * a packet needed bd numbers. - * - * - exceed_limit_bd_reassem_fail - * Total number of exceeding the hardware limited bd fail which - * process a packet needed bd numbers and reassemble fail. - * - * - unsupported_tunnel_pkt_cnt - * Total number of unsupported tunnel packet. The unsupported tunnel - * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet - * with MPLS-in-UDP RFC 7510 header. - * - * - queue_full_cnt - * Total count which the available bd numbers in current bd queue is - * less than the bd numbers with the pkt process needed. - * - * - pkt_padding_fail_cnt - * Total count which the packet length is less than minimum packet - * length(struct hns3_tx_queue::min_tx_pkt_len) supported by - * hardware in Tx direction and fail to be appended with 0. - */ - uint64_t over_length_pkt_cnt; - uint64_t exceed_limit_bd_pkt_cnt; - uint64_t exceed_limit_bd_reassem_fail; - uint64_t unsupported_tunnel_pkt_cnt; - uint64_t queue_full_cnt; - uint64_t pkt_padding_fail_cnt; + struct hns3_tx_dfx_stats dfx_stats; };

#define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \ @@ -511,9 +525,9 @@ hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,

if (unlikely((l234_info & L2E_TRUNC_ERR_FLAG) || rxm->pkt_len == 0)) { if (l234_info & BIT(HNS3_RXD_L2E_B)) - rxq->l2_errors++; + rxq->err_stats.l2_errors++; else - rxq->pkt_len_errors++; + rxq->err_stats.pkt_len_errors++; return -EINVAL; }

@@ -525,24 +539,24 @@ hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,

if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) { rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD; - rxq->l3_csum_errors++; + rxq->dfx_stats.l3_csum_errors++; tmp |= HNS3_L3_CKSUM_ERR; }

if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) { rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD; - rxq->l4_csum_errors++; + rxq->dfx_stats.l4_csum_errors++; tmp |= HNS3_L4_CKSUM_ERR; }

if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) { - rxq->ol3_csum_errors++; + rxq->dfx_stats.ol3_csum_errors++; tmp |= HNS3_OUTER_L3_CKSUM_ERR; }

if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) { rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD; - rxq->ol4_csum_errors++; + rxq->dfx_stats.ol4_csum_errors++; tmp |= HNS3_OUTER_L4_CKSUM_ERR; } } diff --git a/drivers/net/hns3/hns3_rxtx_vec_neon.h b/drivers/net/hns3/hns3_rxtx_vec_neon.h index 54addbf..a693b4b 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_neon.h +++ b/drivers/net/hns3/hns3_rxtx_vec_neon.h @@ -42,7 +42,7 @@ hns3_xmit_fixed_burst_vec(void *__restrict tx_queue,

nb_commit = RTE_MIN(txq->tx_bd_ready, nb_pkts); if (unlikely(nb_commit == 0)) { - txq->queue_full_cnt++; + txq->dfx_stats.queue_full_cnt++; return 0; } nb_tx = nb_commit; diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 62a712b..419d7e2 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -262,34 +262,38 @@ static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = {

/* The statistic of errors in Rx BD */ static const struct hns3_xstats_name_offset hns3_rx_bd_error_strings[] = { - {"RX_PKT_LEN_ERRORS", + {"PKT_LEN_ERRORS", HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(pkt_len_errors)}, - {"L2_RX_ERRORS", - HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l2_errors)}, - {"RX_L3_CHECKSUM_ERRORS", - HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l3_csum_errors)}, - {"RX_L4_CHECKSUM_ERRORS", - HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l4_csum_errors)}, - {"RX_OL3_CHECKSUM_ERRORS", - HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(ol3_csum_errors)}, - {"RX_OL4_CHECKSUM_ERRORS", - HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(ol4_csum_errors)} + {"L2_ERRORS", + HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l2_errors)} };

-/* The statistic of the Tx errors */ -static const struct hns3_xstats_name_offset hns3_tx_errors_strings[] = { - {"TX_OVER_LENGTH_PKT_CNT", - HNS3_TX_ERROR_STATS_FIELD_OFFSET(over_length_pkt_cnt)}, - {"TX_EXCEED_LIMITED_BD_PKT_CNT", - HNS3_TX_ERROR_STATS_FIELD_OFFSET(exceed_limit_bd_pkt_cnt)}, - {"TX_EXCEED_LIMITED_BD_PKT_REASSEMBLE_FAIL_CNT", - HNS3_TX_ERROR_STATS_FIELD_OFFSET(exceed_limit_bd_reassem_fail)}, - {"TX_UNSUPPORTED_TUNNEL_PKT_CNT", - HNS3_TX_ERROR_STATS_FIELD_OFFSET(unsupported_tunnel_pkt_cnt)}, - {"TX_QUEUE_FULL_CNT", - HNS3_TX_ERROR_STATS_FIELD_OFFSET(queue_full_cnt)}, - {"TX_SHORT_PKT_PAD_FAIL_CNT", - HNS3_TX_ERROR_STATS_FIELD_OFFSET(pkt_padding_fail_cnt)} +/* The dfx statistic in Rx datapath */ +static const struct hns3_xstats_name_offset hns3_rxq_dfx_stats_strings[] = { + {"L3_CHECKSUM_ERRORS", + HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l3_csum_errors)}, + {"L4_CHECKSUM_ERRORS", + HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l4_csum_errors)}, + {"OL3_CHECKSUM_ERRORS", + HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol3_csum_errors)}, + {"OL4_CHECKSUM_ERRORS", + HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol4_csum_errors)} +}; + +/* The dfx statistic in Tx datapath */ +static const struct hns3_xstats_name_offset hns3_txq_dfx_stats_strings[] = { + {"OVER_LENGTH_PKT_CNT", + HNS3_TXQ_DFX_STATS_FIELD_OFFSET(over_length_pkt_cnt)}, + {"EXCEED_LIMITED_BD_PKT_CNT", + HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_pkt_cnt)}, + {"EXCEED_LIMITED_BD_PKT_REASSEMBLE_FAIL_CNT", + HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_reassem_fail)}, + {"UNSUPPORTED_TUNNEL_PKT_CNT", + HNS3_TXQ_DFX_STATS_FIELD_OFFSET(unsupported_tunnel_pkt_cnt)}, + {"QUEUE_FULL_CNT", + HNS3_TXQ_DFX_STATS_FIELD_OFFSET(queue_full_cnt)}, + {"SHORT_PKT_PAD_FAIL_CNT", + HNS3_TXQ_DFX_STATS_FIELD_OFFSET(pkt_padding_fail_cnt)} };

/* The statistic of rx queue */ @@ -314,8 +318,11 @@ static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = { #define HNS3_NUM_RX_BD_ERROR_XSTATS (sizeof(hns3_rx_bd_error_strings) / \ sizeof(hns3_rx_bd_error_strings[0]))

-#define HNS3_NUM_TX_ERRORS_XSTATS (sizeof(hns3_tx_errors_strings) / \ - sizeof(hns3_tx_errors_strings[0])) +#define HNS3_NUM_RXQ_DFX_XSTATS (sizeof(hns3_rxq_dfx_stats_strings) / \ + sizeof(hns3_rxq_dfx_stats_strings[0])) + +#define HNS3_NUM_TXQ_DFX_XSTATS (sizeof(hns3_txq_dfx_stats_strings) / \ + sizeof(hns3_txq_dfx_stats_strings[0]))

#define HNS3_NUM_RX_QUEUE_STATS (sizeof(hns3_rx_queue_strings) / \ sizeof(hns3_rx_queue_strings[0])) @@ -519,7 +526,8 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) for (i = 0; i != num; ++i) { rxq = eth_dev->data->rx_queues[i]; if (rxq) { - cnt = rxq->l2_errors + rxq->pkt_len_errors; + cnt = rxq->err_stats.l2_errors + + rxq->err_stats.pkt_len_errors; rte_stats->q_errors[i] = cnt; rte_stats->q_ipackets[i] = stats->rcb_rx_ring_pktnum[i] - cnt; @@ -584,11 +592,11 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) * Clear soft stats of rx error packet which will be dropped * in driver. */ - for (i = 0; i < eth_dev->data->nb_rx_queues; ++i) { + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq) { - rxq->pkt_len_errors = 0; - rxq->l2_errors = 0; + rxq->err_stats.pkt_len_errors = 0; + rxq->err_stats.l2_errors = 0; } }

@@ -621,21 +629,24 @@ static int hns3_xstats_calc_num(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; - int bderr_stats = dev->data->nb_rx_queues * HNS3_NUM_RX_BD_ERROR_XSTATS; - int tx_err_stats = dev->data->nb_tx_queues * HNS3_NUM_TX_ERRORS_XSTATS; - int rx_queue_stats = dev->data->nb_rx_queues * HNS3_NUM_RX_QUEUE_STATS; - int tx_queue_stats = dev->data->nb_tx_queues * HNS3_NUM_TX_QUEUE_STATS; + uint16_t nb_rx_q = dev->data->nb_rx_queues; + uint16_t nb_tx_q = dev->data->nb_tx_queues; + int bderr_stats = nb_rx_q * HNS3_NUM_RX_BD_ERROR_XSTATS; + int rx_dfx_stats = nb_rx_q * HNS3_NUM_RXQ_DFX_XSTATS; + int tx_dfx_stats = nb_tx_q * HNS3_NUM_TXQ_DFX_XSTATS; + int rx_queue_stats = nb_rx_q * HNS3_NUM_RX_QUEUE_STATS; + int tx_queue_stats = nb_tx_q * HNS3_NUM_TX_QUEUE_STATS;

if (hns->is_vf) - return bderr_stats + tx_err_stats + rx_queue_stats + - tx_queue_stats + HNS3_NUM_RESET_XSTATS; + return bderr_stats + rx_dfx_stats + tx_dfx_stats + + rx_queue_stats + tx_queue_stats + HNS3_NUM_RESET_XSTATS; else - return bderr_stats + tx_err_stats + rx_queue_stats + - tx_queue_stats + HNS3_FIX_NUM_STATS; + return bderr_stats + rx_dfx_stats + tx_dfx_stats + + rx_queue_stats + tx_queue_stats + HNS3_FIX_NUM_STATS; }

static void -hns3_get_queue_stats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, +hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, int *count) { struct hns3_adapter *hns = dev->data->dev_private; @@ -683,6 +694,63 @@ hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err) } }

+static void +hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + struct hns3_rx_dfx_stats *dfx_stats; + struct hns3_rx_queue *rxq; + uint16_t i, j; + char *val; + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = (struct hns3_rx_queue *)dev->data->rx_queues[i]; + if (rxq == NULL) + continue; + + dfx_stats = &rxq->dfx_stats; + for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) { + val = (char *)dfx_stats + + hns3_rxq_dfx_stats_strings[j].offset; + xstats[*count].value = *(uint64_t *)val; + xstats[*count].id = *count; + (*count)++; + } + } +} + +static void +hns3_txq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + struct hns3_tx_dfx_stats *dfx_stats; + struct hns3_tx_queue *txq; + uint16_t i, j; + char *val; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = (struct hns3_tx_queue *)dev->data->tx_queues[i]; + if (txq == NULL) + continue; + + dfx_stats = &txq->dfx_stats; + for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) { + val = (char *)dfx_stats + + hns3_txq_dfx_stats_strings[j].offset; + xstats[*count].value = *(uint64_t *)val; + xstats[*count].id = *count; + (*count)++; + } + } +} + +static void +hns3_tqp_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + hns3_rxq_dfx_stats_get(dev, xstats, count); + hns3_txq_dfx_stats_get(dev, xstats, count); +} /* * Retrieve extended(tqp | Mac) statistics of an Ethernet device. * @param dev @@ -705,8 +773,8 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, struct hns3_hw *hw = &hns->hw; struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; + struct hns3_rx_bd_errors_stats *rx_err_stats; struct hns3_rx_queue *rxq; - struct hns3_tx_queue *txq; uint16_t i, j; char *addr; int count; @@ -758,26 +826,49 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, for (j = 0; j < dev->data->nb_rx_queues; j++) { for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) { rxq = dev->data->rx_queues[j]; - addr = (char *)rxq + hns3_rx_bd_error_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; + if (rxq) { + rx_err_stats = &rxq->err_stats; + addr = (char *)rx_err_stats + + hns3_rx_bd_error_strings[i].offset; + xstats[count].value = *(uint64_t *)addr; + xstats[count].id = count; + count++; + } } }

- /* Get the Tx errors stats */ - for (j = 0; j < dev->data->nb_tx_queues; j++) { - for (i = 0; i < HNS3_NUM_TX_ERRORS_XSTATS; i++) { - txq = dev->data->tx_queues[j]; - addr = (char *)txq + hns3_tx_errors_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; + hns3_tqp_dfx_stats_get(dev, xstats, &count); + hns3_queue_stats_get(dev, xstats, &count); + + return count; +} + +static void +hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + uint32_t *count) +{ + uint16_t i, j; + + for (j = 0; j < dev->data->nb_rx_queues; j++) { + for (i = 0; i < HNS3_NUM_RXQ_DFX_XSTATS; i++) { + snprintf(xstats_names[*count].name, + sizeof(xstats_names[*count].name), + "rx_q%u_%s", j, + hns3_rxq_dfx_stats_strings[i].name); + (*count)++; } }

- hns3_get_queue_stats(dev, xstats, &count); - return count; + for (j = 0; j < dev->data->nb_tx_queues; j++) { + for (i = 0; i < HNS3_NUM_TXQ_DFX_XSTATS; i++) { + snprintf(xstats_names[*count].name, + sizeof(xstats_names[*count].name), + "tx_q%u_%s", j, + hns3_txq_dfx_stats_strings[i].name); + (*count)++; + } + } }

/* @@ -845,27 +936,19 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), - "rx_q%u%s", j, + "rx_q%u_%s", j, hns3_rx_bd_error_strings[i].name); count++; } }

- for (j = 0; j < dev->data->nb_tx_queues; j++) { - for (i = 0; i < HNS3_NUM_TX_ERRORS_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "tx_q%u%s", j, - hns3_tx_errors_strings[i].name); - count++; - } - } + hns3_tqp_dfx_stats_name_get(dev, xstats_names, &count);

for (j = 0; j < dev->data->nb_rx_queues; j++) { for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), - "rx_q%u%s", j, hns3_rx_queue_strings[i].name); + "rx_q%u_%s", j, hns3_rx_queue_strings[i].name); count++; } } @@ -874,7 +957,7 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), - "tx_q%u%s", j, hns3_tx_queue_strings[i].name); + "tx_q%u_%s", j, hns3_tx_queue_strings[i].name); count++; } } @@ -1043,30 +1126,22 @@ hns3_tqp_dfx_stats_clear(struct rte_eth_dev *dev) { struct hns3_rx_queue *rxq; struct hns3_tx_queue *txq; - int i; + uint16_t i;

/* Clear Rx dfx stats */ - for (i = 0; i < dev->data->nb_rx_queues; ++i) { + for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; - if (rxq) { - rxq->l3_csum_errors = 0; - rxq->l4_csum_errors = 0; - rxq->ol3_csum_errors = 0; - rxq->ol4_csum_errors = 0; - } + if (rxq) + memset(&rxq->dfx_stats, 0, + sizeof(struct hns3_rx_dfx_stats)); }

/* Clear Tx dfx stats */ - for (i = 0; i < dev->data->nb_tx_queues; ++i) { + for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; - if (txq) { - txq->over_length_pkt_cnt = 0; - txq->exceed_limit_bd_pkt_cnt = 0; - txq->exceed_limit_bd_reassem_fail = 0; - txq->unsupported_tunnel_pkt_cnt = 0; - txq->queue_full_cnt = 0; - txq->pkt_padding_fail_cnt = 0; - } + if (txq) + memset(&txq->dfx_stats, 0, + sizeof(struct hns3_tx_dfx_stats)); } }

diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 9fcd5f9..12842cd 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -127,10 +127,13 @@ struct hns3_reset_stats; (offsetof(struct hns3_reset_stats, f))

#define HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(f) \ - (offsetof(struct hns3_rx_queue, f)) + (offsetof(struct hns3_rx_bd_errors_stats, f))

-#define HNS3_TX_ERROR_STATS_FIELD_OFFSET(f) \ - (offsetof(struct hns3_tx_queue, f)) +#define HNS3_RXQ_DFX_STATS_FIELD_OFFSET(f) \ + (offsetof(struct hns3_rx_dfx_stats, f)) + +#define HNS3_TXQ_DFX_STATS_FIELD_OFFSET(f) \ + (offsetof(struct hns3_tx_dfx_stats, f))

int hns3_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats); int hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,

Heres uses errno array instead of switch-case for refactor the hns3_cmd_convert_err_code function. Besides, we add a type for ROH(RDMA Over HCCS) check cmdq return error in Kunpeng930 NIC hardware.

Signed-off-by: Lijun Ou oulijun@huawei.com --- drivers/net/hns3/hns3_cmd.c | 54 ++++++++++++++++++++++----------------------- drivers/net/hns3/hns3_cmd.h | 1 + 2 files changed, 27 insertions(+), 28 deletions(-)

diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index f58f4f7..4c301cb 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -247,34 +247,32 @@ hns3_is_special_opcode(uint16_t opcode) static int hns3_cmd_convert_err_code(uint16_t desc_ret) { - switch (desc_ret) { - case HNS3_CMD_EXEC_SUCCESS: - return 0; - case HNS3_CMD_NO_AUTH: - return -EPERM; - case HNS3_CMD_NOT_SUPPORTED: - return -EOPNOTSUPP; - case HNS3_CMD_QUEUE_FULL: - return -EXFULL; - case HNS3_CMD_NEXT_ERR: - return -ENOSR; - case HNS3_CMD_UNEXE_ERR: - return -ENOTBLK; - case HNS3_CMD_PARA_ERR: - return -EINVAL; - case HNS3_CMD_RESULT_ERR: - return -ERANGE; - case HNS3_CMD_TIMEOUT: - return -ETIME; - case HNS3_CMD_HILINK_ERR: - return -ENOLINK; - case HNS3_CMD_QUEUE_ILLEGAL: - return -ENXIO; - case HNS3_CMD_INVALID: - return -EBADR; - default: - return -EREMOTEIO; - } + static const struct { + uint16_t imp_errcode; + int linux_errcode; + } hns3_cmdq_status[] = { + {HNS3_CMD_EXEC_SUCCESS, 0}, + {HNS3_CMD_NO_AUTH, -EPERM}, + {HNS3_CMD_NOT_SUPPORTED, -EOPNOTSUPP}, + {HNS3_CMD_QUEUE_FULL, -EXFULL}, + {HNS3_CMD_NEXT_ERR, -ENOSR}, + {HNS3_CMD_UNEXE_ERR, -ENOTBLK}, + {HNS3_CMD_PARA_ERR, -EINVAL}, + {HNS3_CMD_RESULT_ERR, -ERANGE}, + {HNS3_CMD_TIMEOUT, -ETIME}, + {HNS3_CMD_HILINK_ERR, -ENOLINK}, + {HNS3_CMD_QUEUE_ILLEGAL, -ENXIO}, + {HNS3_CMD_INVALID, -EBADR}, + {HNS3_CMD_ROH_CHECK_FAIL, -EINVAL} + }; + + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(hns3_cmdq_status); i++) + if (hns3_cmdq_status[i].imp_errcode == desc_ret) + return hns3_cmdq_status[i].linux_errcode; + + return -EREMOTEIO; }

static int diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index e40293b..6152f6e 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -52,6 +52,7 @@ enum hns3_cmd_return_status { HNS3_CMD_HILINK_ERR = 9, HNS3_CMD_QUEUE_ILLEGAL = 10, HNS3_CMD_INVALID = 11, + HNS3_CMD_ROH_CHECK_FAIL = 12 };

enum hns3_cmd_status {

From: Chengchang Tang tangchengchang@huawei.com

This patch reconstruct the Rx interrupt map to reduce the cyclic complexity and improve readability and maintainability.

Signed-off-by: Chengchang Tang tangchengchang@huawei.com Signed-off-by: Lijun Ou oulijun@huawei.com --- drivers/net/hns3/hns3_ethdev.c | 59 +++++++++++++++++++-------------------- drivers/net/hns3/hns3_ethdev_vf.c | 55 ++++++++++++++++++------------------ 2 files changed, 56 insertions(+), 58 deletions(-)

diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 7c51e83..f3ce639 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -4782,27 +4782,28 @@ hns3_map_rx_interrupt(struct rte_eth_dev *dev) uint16_t q_id; int ret;

- if (dev->data->dev_conf.intr_conf.rxq == 0) + /* + * hns3 needs a separate interrupt to be used as event interrupt which + * could not be shared with task queue pair, so KERNEL drivers need + * support multiple interrupt vectors. + */ + if (dev->data->dev_conf.intr_conf.rxq == 0 || + !rte_intr_cap_multiple(intr_handle)) return 0;

- /* disable uio/vfio intr/eventfd mapping */ rte_intr_disable(intr_handle); + intr_vector = hw->used_rx_queues; + /* creates event fd for each intr vector when MSIX is used */ + if (rte_intr_efd_enable(intr_handle, intr_vector)) + return -EINVAL;

- /* check and configure queue intr-vector mapping */ - if (rte_intr_cap_multiple(intr_handle) || - !RTE_ETH_DEV_SRIOV(dev).active) { - intr_vector = hw->used_rx_queues; - /* creates event fd for each intr vector when MSIX is used */ - if (rte_intr_efd_enable(intr_handle, intr_vector)) - return -EINVAL; - } - if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { + if (intr_handle->intr_vec == NULL) { intr_handle->intr_vec = rte_zmalloc("intr_vec", hw->used_rx_queues * sizeof(int), 0); if (intr_handle->intr_vec == NULL) { - hns3_err(hw, "Failed to allocate %u rx_queues" - " intr_vec", hw->used_rx_queues); + hns3_err(hw, "failed to allocate %u rx_queues intr_vec", + hw->used_rx_queues); ret = -ENOMEM; goto alloc_intr_vec_error; } @@ -4812,28 +4813,26 @@ hns3_map_rx_interrupt(struct rte_eth_dev *dev) vec = RTE_INTR_VEC_RXTX_OFFSET; base = RTE_INTR_VEC_RXTX_OFFSET; } - if (rte_intr_dp_is_en(intr_handle)) { - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - ret = hns3_bind_ring_with_vector(hw, vec, true, - HNS3_RING_TYPE_RX, - q_id); - if (ret) - goto bind_vector_error; - intr_handle->intr_vec[q_id] = vec; - if (vec < base + intr_handle->nb_efd - 1) - vec++; - } + + for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { + ret = hns3_bind_ring_with_vector(hw, vec, true, + HNS3_RING_TYPE_RX, q_id); + if (ret) + goto bind_vector_error; + intr_handle->intr_vec[q_id] = vec; + /* + * If there are not enough efds (e.g. not enough interrupt), + * remaining queues will be bond to the last interrupt. + */ + if (vec < base + intr_handle->nb_efd - 1) + vec++; } rte_intr_enable(intr_handle); return 0;

bind_vector_error: - rte_intr_efd_disable(intr_handle); - if (intr_handle->intr_vec) { - free(intr_handle->intr_vec); - intr_handle->intr_vec = NULL; - } - return ret; + rte_free(intr_handle->intr_vec); + intr_handle->intr_vec = NULL; alloc_intr_vec_error: rte_intr_efd_disable(intr_handle); return ret; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 37135d7..3a1d4cb 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2085,21 +2085,22 @@ hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) uint16_t q_id; int ret;

- if (dev->data->dev_conf.intr_conf.rxq == 0) + /* + * hns3 needs a separate interrupt to be used as event interrupt which + * could not be shared with task queue pair, so KERNEL drivers need + * support multiple interrupt vectors. + */ + if (dev->data->dev_conf.intr_conf.rxq == 0 || + !rte_intr_cap_multiple(intr_handle)) return 0;

- /* disable uio/vfio intr/eventfd mapping */ rte_intr_disable(intr_handle); + intr_vector = hw->used_rx_queues; + /* It creates event fd for each intr vector when MSIX is used */ + if (rte_intr_efd_enable(intr_handle, intr_vector)) + return -EINVAL;

- /* check and configure queue intr-vector mapping */ - if (rte_intr_cap_multiple(intr_handle) || - !RTE_ETH_DEV_SRIOV(dev).active) { - intr_vector = hw->used_rx_queues; - /* It creates event fd for each intr vector when MSIX is used */ - if (rte_intr_efd_enable(intr_handle, intr_vector)) - return -EINVAL; - } - if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { + if (intr_handle->intr_vec == NULL) { intr_handle->intr_vec = rte_zmalloc("intr_vec", hw->used_rx_queues * sizeof(int), 0); @@ -2115,28 +2116,26 @@ hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) vec = RTE_INTR_VEC_RXTX_OFFSET; base = RTE_INTR_VEC_RXTX_OFFSET; } - if (rte_intr_dp_is_en(intr_handle)) { - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - ret = hns3vf_bind_ring_with_vector(hw, vec, true, - HNS3_RING_TYPE_RX, - q_id); - if (ret) - goto vf_bind_vector_error; - intr_handle->intr_vec[q_id] = vec; - if (vec < base + intr_handle->nb_efd - 1) - vec++; - } + + for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { + ret = hns3vf_bind_ring_with_vector(hw, vec, true, + HNS3_RING_TYPE_RX, q_id); + if (ret) + goto vf_bind_vector_error; + intr_handle->intr_vec[q_id] = vec; + /* + * If there are not enough efds (e.g. not enough interrupt), + * remaining queues will be bond to the last interrupt. + */ + if (vec < base + intr_handle->nb_efd - 1) + vec++; } rte_intr_enable(intr_handle); return 0;

vf_bind_vector_error: - rte_intr_efd_disable(intr_handle); - if (intr_handle->intr_vec) { - free(intr_handle->intr_vec); - intr_handle->intr_vec = NULL; - } - return ret; + free(intr_handle->intr_vec); + intr_handle->intr_vec = NULL; vf_alloc_intr_vec_error: rte_intr_efd_disable(intr_handle); return ret;

Here encapsulate the process code of the imp reset report and global reset report into function in order to reduce the complexity of the hns3_check_event_cause function.

Signed-off-by: Lijun Ou oulijun@huawei.com --- drivers/net/hns3/hns3_ethdev.c | 69 +++++++++++++++++++++++++++--------------- 1 file changed, 45 insertions(+), 24 deletions(-)

diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index f3ce639..817d1dc 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -123,6 +123,47 @@ hns3_pf_enable_irq0(struct hns3_hw *hw) }

static enum hns3_evt_cause +hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, + uint32_t *vec_val) +{ + struct hns3_hw *hw = &hns->hw; + + rte_atomic16_set(&hw->reset.disable_cmd, 1); + hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); + *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); + if (!is_delay) { + hw->reset.stats.imp_cnt++; + hns3_warn(hw, "IMP reset detected, clear reset status"); + } else { + hns3_schedule_delayed_reset(hns); + hns3_warn(hw, "IMP reset detected, don't clear reset status"); + } + + return HNS3_VECTOR0_EVENT_RST; +} + +static enum hns3_evt_cause +hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, + uint32_t *vec_val) +{ + struct hns3_hw *hw = &hns->hw; + + rte_atomic16_set(&hw->reset.disable_cmd, 1); + hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); + *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); + if (!is_delay) { + hw->reset.stats.global_cnt++; + hns3_warn(hw, "Global reset detected, clear reset status"); + } else { + hns3_schedule_delayed_reset(hns); + hns3_warn(hw, + "Global reset detected, don't clear reset status"); + } + + return HNS3_VECTOR0_EVENT_RST; +} + +static enum hns3_evt_cause hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) { struct hns3_hw *hw = &hns->hw; @@ -131,12 +172,14 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) uint32_t hw_err_src_reg; uint32_t val; enum hns3_evt_cause ret; + bool is_delay;

/* fetch the events from their corresponding regs */ vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);

+ is_delay = clearval == NULL ? true : false; /* * Assumption: If by any chance reset and mailbox events are reported * together then we will only process reset event and defer the @@ -145,35 +188,13 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) * from H/W just for the mailbox. */ if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ - rte_atomic16_set(&hw->reset.disable_cmd, 1); - hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); - val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); - if (clearval) { - hw->reset.stats.imp_cnt++; - hns3_warn(hw, "IMP reset detected, clear reset status"); - } else { - hns3_schedule_delayed_reset(hns); - hns3_warn(hw, "IMP reset detected, don't clear reset status"); - } - - ret = HNS3_VECTOR0_EVENT_RST; + ret = hns3_proc_imp_reset_event(hns, is_delay, &val); goto out; }

/* Global reset */ if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { - rte_atomic16_set(&hw->reset.disable_cmd, 1); - hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); - val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); - if (clearval) { - hw->reset.stats.global_cnt++; - hns3_warn(hw, "Global reset detected, clear reset status"); - } else { - hns3_schedule_delayed_reset(hns); - hns3_warn(hw, "Global reset detected, don't clear reset status"); - } - - ret = HNS3_VECTOR0_EVENT_RST; + ret = hns3_proc_global_reset_event(hns, is_delay, &val); goto out; }

From: Chengchang Tang tangchengchang@huawei.com

For Kunpeng930, the NIC engine support 1280 tqps being taken over by a PF. In this case, a maximum of 1281 interrupt resources are also supported in this PF. To support the maximum number of queues, several patches are made. But the interrupt related modification are missing. So, in RX interrupt mode, a large number of queues will be aggregted into one interrupt due to insufficient interrupts. It will lead to waste of interrupt resources and reduces usability.

To utilize all these interrupt resources, related IMP command has been extended. And, the I/O address of the extended interrupt resources are different from the existing ones. So, a function used for calculating the address offset has been added.

Fixes: 76d794566d43 ("net/hns3: maximize queue number") Fixes: 27911a6e62e5 ("net/hns3: add Rx interrupts compatibility") Cc: stable@dpdk.org

Signed-off-by: Chengchang Tang tangchengchang@huawei.com --- drivers/net/hns3/hns3_cmd.h | 8 ++++++-- drivers/net/hns3/hns3_ethdev.c | 17 +++++++++-------- drivers/net/hns3/hns3_regs.c | 2 +- drivers/net/hns3/hns3_regs.h | 24 +++++++++++++++--------- drivers/net/hns3/hns3_rxtx.c | 28 +++++++++++++++++++++++----- drivers/net/hns3/hns3_rxtx.h | 1 + 6 files changed, 55 insertions(+), 25 deletions(-)

diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 6152f6e..dc97a1a 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -776,12 +776,16 @@ enum hns3_int_gl_idx { #define HNS3_TQP_ID_M GENMASK(12, 2) #define HNS3_INT_GL_IDX_S 13 #define HNS3_INT_GL_IDX_M GENMASK(14, 13) +#define HNS3_TQP_INT_ID_L_S 0 +#define HNS3_TQP_INT_ID_L_M GENMASK(7, 0) +#define HNS3_TQP_INT_ID_H_S 8 +#define HNS3_TQP_INT_ID_H_M GENMASK(15, 8) struct hns3_ctrl_vector_chain_cmd { - uint8_t int_vector_id; + uint8_t int_vector_id; /* the low order of the interrupt id */ uint8_t int_cause_num; uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD]; uint8_t vfid; - uint8_t rsv; + uint8_t int_vector_id_h; /* the high order of the interrupt id */ };

struct hns3_config_max_frm_size_cmd { diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 2a5689c..4356860 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2232,7 +2232,7 @@ hns3_check_dcb_cfg(struct rte_eth_dev *dev) }

static int -hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap, +hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, enum hns3_ring_type queue_type, uint16_t queue_id) { struct hns3_cmd_desc desc; @@ -2241,13 +2241,15 @@ hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap, enum hns3_cmd_status status; enum hns3_opcode_type op; uint16_t tqp_type_and_id = 0; - const char *op_str; uint16_t type; uint16_t gl;

- op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; + op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; hns3_cmd_setup_basic_desc(&desc, op, false); - req->int_vector_id = vector_id; + req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M, + HNS3_TQP_INT_ID_L_S); + req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M, + HNS3_TQP_INT_ID_H_S);

if (queue_type == HNS3_RING_TYPE_RX) gl = HNS3_RING_GL_RX; @@ -2263,11 +2265,10 @@ hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap, gl); req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); req->int_cause_num = 1; - op_str = mmap ? "Map" : "Unmap"; status = hns3_cmd_send(hw, &desc, 1); if (status) { hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.", - op_str, queue_id, req->int_vector_id, status); + en ? "Map" : "Unmap", queue_id, vector_id, status); return status; }

@@ -4797,8 +4798,8 @@ hns3_map_rx_interrupt(struct rte_eth_dev *dev) struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; - uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; + uint16_t base = RTE_INTR_VEC_ZERO_OFFSET; + uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET; uint32_t intr_vector; uint16_t q_id; int ret; diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index f2cb465..8afe132 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -301,7 +301,7 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)

reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t); for (j = 0; j < hw->intr_tqps_num; j++) { - reg_offset = HNS3_TQP_INTR_REG_SIZE * j; + reg_offset = hns3_get_tqp_intr_reg_offset(j); for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] + reg_offset); diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h index 81a0af5..39fc5d1 100644 --- a/drivers/net/hns3/hns3_regs.h +++ b/drivers/net/hns3/hns3_regs.h @@ -95,15 +95,21 @@ #define HNS3_MIN_EXTEND_QUEUE_ID 1024

/* bar registers for tqp interrupt */ -#define HNS3_TQP_INTR_CTRL_REG 0x20000 -#define HNS3_TQP_INTR_GL0_REG 0x20100 -#define HNS3_TQP_INTR_GL1_REG 0x20200 -#define HNS3_TQP_INTR_GL2_REG 0x20300 -#define HNS3_TQP_INTR_RL_REG 0x20900 -#define HNS3_TQP_INTR_TX_QL_REG 0x20e00 -#define HNS3_TQP_INTR_RX_QL_REG 0x20f00 - -#define HNS3_TQP_INTR_REG_SIZE 4 +#define HNS3_TQP_INTR_REG_BASE 0x20000 +#define HNS3_TQP_INTR_EXT_REG_BASE 0x30000 +#define HNS3_TQP_INTR_CTRL_REG 0 +#define HNS3_TQP_INTR_GL0_REG 0x100 +#define HNS3_TQP_INTR_GL1_REG 0x200 +#define HNS3_TQP_INTR_GL2_REG 0x300 +#define HNS3_TQP_INTR_RL_REG 0x900 +#define HNS3_TQP_INTR_TX_QL_REG 0xe00 +#define HNS3_TQP_INTR_RX_QL_REG 0xf00 +#define HNS3_TQP_INTR_RL_EN_B 6 + +#define HNS3_MIN_EXT_TQP_INTR_ID 64 +#define HNS3_TQP_INTR_LOW_ORDER_OFFSET 0x4 +#define HNS3_TQP_INTR_HIGH_ORDER_OFFSET 0x1000 + #define HNS3_TQP_INTR_GL_MAX 0x1FE0 #define HNS3_TQP_INTR_GL_DEFAULT 20 #define HNS3_TQP_INTR_GL_UNIT_1US BIT(31) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 30f1e06..1991b4e 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -834,6 +834,24 @@ hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id, return ret; }

+uint32_t +hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id) +{ + uint32_t reg_offset; + + /* Need an extend offset to config queues > 64 */ + if (tqp_intr_id < HNS3_MIN_EXT_TQP_INTR_ID) + reg_offset = HNS3_TQP_INTR_REG_BASE + + tqp_intr_id * HNS3_TQP_INTR_LOW_ORDER_OFFSET; + else + reg_offset = HNS3_TQP_INTR_EXT_REG_BASE + + tqp_intr_id / HNS3_MIN_EXT_TQP_INTR_ID * + HNS3_TQP_INTR_HIGH_ORDER_OFFSET + + tqp_intr_id % HNS3_MIN_EXT_TQP_INTR_ID * + HNS3_TQP_INTR_LOW_ORDER_OFFSET; + + return reg_offset; +}

void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id, @@ -847,7 +865,7 @@ hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id, if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX) return;

- addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE; + addr = offset[gl_idx] + hns3_get_tqp_intr_reg_offset(queue_id); if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US) value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US; else @@ -864,7 +882,7 @@ hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value) if (rl_value > HNS3_TQP_INTR_RL_MAX) return;

- addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE; + addr = HNS3_TQP_INTR_RL_REG + hns3_get_tqp_intr_reg_offset(queue_id); value = HNS3_RL_USEC_TO_REG(rl_value); if (value > 0) value |= HNS3_TQP_INTR_RL_ENABLE_MASK; @@ -885,10 +903,10 @@ hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value) if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE) return;

- addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE; + addr = HNS3_TQP_INTR_TX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id); hns3_write_dev(hw, addr, ql_value);

- addr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE; + addr = HNS3_TQP_INTR_RX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id); hns3_write_dev(hw, addr, ql_value); }

@@ -897,7 +915,7 @@ hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en) { uint32_t addr, value;

- addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE; + addr = HNS3_TQP_INTR_CTRL_REG + hns3_get_tqp_intr_reg_offset(queue_id); value = en ? 1 : 0;

hns3_write_dev(hw, addr, value); diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 331b507..8f5ae5c 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -680,6 +680,7 @@ int hns3_tx_burst_mode_get(struct rte_eth_dev *dev, const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev); void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev); void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev); +uint32_t hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id); void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id, uint8_t gl_idx, uint16_t gl_value); void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,

Fixe some error comments and remove some meaningless comments.

Signed-off-by: Lijun Ou oulijun@huawei.com --- drivers/net/hns3/hns3_flow.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/net/hns3/hns3_flow.c b/drivers/net/hns3/hns3_flow.c index 8a5179d..f2bff1e 100644 --- a/drivers/net/hns3/hns3_flow.c +++ b/drivers/net/hns3/hns3_flow.c @@ -91,9 +91,9 @@ net_addr_to_host(uint32_t *dst, const rte_be32_t *src, size_t len) /* * This function is used to find rss general action. * 1. As we know RSS is used to spread packets among several queues, the flow - * API provide the struct rte_flow_action_rss, user could config it's field + * API provide the struct rte_flow_action_rss, user could config its field * sush as: func/level/types/key/queue to control RSS function. - * 2. The flow API also support queue region configuration for hns3. It was + * 2. The flow API also supports queue region configuration for hns3. It was * implemented by FDIR + RSS in hns3 hardware, user can create one FDIR rule * which action is RSS queues region. * 3. When action is RSS, we use the following rule to distinguish: @@ -128,11 +128,11 @@ hns3_find_rss_general_action(const struct rte_flow_item pattern[], rss = act->conf; if (have_eth && rss->conf.queue_num) { /* - * Patter have ETH and action's queue_num > 0, indicate this is + * Pattern have ETH and action's queue_num > 0, indicate this is * queue region configuration. * Because queue region is implemented by FDIR + RSS in hns3 - * hardware, it need enter FDIR process, so here return NULL to - * avoid enter RSS process. + * hardware, it needs to enter FDIR process, so here return NULL + * to avoid enter RSS process. */ return NULL; } @@ -405,7 +405,6 @@ hns3_handle_actions(struct rte_eth_dev *dev, return 0; }

-/* Parse to get the attr and action info of flow director rule. */ static int hns3_check_attr(const struct rte_flow_attr *attr, struct rte_flow_error *error) { @@ -782,7 +781,7 @@ hns3_parse_sctp(const struct rte_flow_item *item, struct hns3_fdir_rule *rule, }

/* - * Check items before tunnel, save inner configs to outer configs,and clear + * Check items before tunnel, save inner configs to outer configs, and clear * inner configs. * The key consists of two parts: meta_data and tuple keys. * Meta data uses 15 bits, including vlan_num(2bit), des_port(12bit) and tunnel @@ -1473,10 +1472,8 @@ hns3_hw_rss_hash_set(struct hns3_hw *hw, struct rte_flow_action_rss *rss_config) if (ret) return ret;

- /* Update algorithm of hw */ hw->rss_info.conf.func = rss_config->func;

- /* Set flow type supported */ tuple = &hw->rss_info.rss_tuple_sets; ret = hns3_set_rss_tuple_by_rss_hf(hw, tuple, rss_config->types); if (ret) @@ -1561,7 +1558,7 @@ hns3_config_rss_filter(struct rte_eth_dev *dev, if (rss_flow_conf.queue_num) { /* * Due the content of queue pointer have been reset to - * 0, the rss_info->conf.queue should be set NULL + * 0, the rss_info->conf.queue should be set to NULL */ rss_info->conf.queue = NULL; rss_info->conf.queue_num = 0; @@ -1727,7 +1724,7 @@ hns3_flow_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, /* * Create or destroy a flow rule. * Theorically one rule can match more than one filters. - * We will let it use the filter which it hitt first. + * We will let it use the filter which it hit first. * So, the sequence matters. */ static struct rte_flow *

Here uses %d as printing output for enumeration member.

Signed-off-by: Lijun Ou oulijun@huawei.com --- drivers/net/hns3/hns3_flow.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/hns3/hns3_flow.c b/drivers/net/hns3/hns3_flow.c index e9d0a0b..3e387ac 100644 --- a/drivers/net/hns3/hns3_flow.c +++ b/drivers/net/hns3/hns3_flow.c @@ -1447,7 +1447,7 @@ hns3_parse_rss_algorithm(struct hns3_hw *hw, enum rte_eth_hash_function *func, *hash_algo = HNS3_RSS_HASH_ALGO_SYMMETRIC_TOEP; break; default: - hns3_err(hw, "Invalid RSS algorithm configuration(%u)", + hns3_err(hw, "Invalid RSS algorithm configuration(%d)", algo_func); return -EINVAL; }