Hi Pu Wen,
On 2020/3/31 11:20, Pu Wen wrote:
As a new x86 CPU Vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture between AMD and Haiguang Information Technology Co., Ltd., and aims at providing high performance x86 processor for China server market.
The first generation Hygon's processor(Dhyana) originates from AMD technology and shares most of the architecture with AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/PCIE Device Vendor ID (0x1D94)/Family series number (Family 18h).
To enable the support of Linux kernel to Hygon's CPU, we added a new vendor type (X86_VENDOR_HYGON, with value of 9) in arch/x86/include/ asm/processor.h, and shared most of kernel support codes with AMD family 17h.
As Hygon will negotiate with AMD to make sure that only Hygon will use family 18h, so try to minimize code modification and share most codes with AMD under this consideration.
This patch series have been applied and tested successfully on Hygon Dhyana SoC silicon. Also tested on AMD EPYC (Family 17h) processor, it works fine and makes no harm to the existing codes.
This patch series are created for the current branch openEuler-1.0-LTS.
Thanks a lot for your patchset, I took a detail look at this patchset, and it looks good to me, I'm pretty happy that this patchset was backported from mainline kernel and you are the maintainer.
For this patchset,
Reviewed-by: Hanjun Guo guohanjun@huawei.com
BTW, do we need updates for compiler, glibc and other usersapce package to recognize Hygon processor or performance optimization? if yes, you can send those patches to openEuler as well.
And I kindly invite you to create a new SIG for Hygon processor in openEuler [1].
Thanks Hanjun
[1]: https://openeuler.org/zh/sig.html
References: [1] Linux kernel patches for Hygon Dhyana, merged in 4.20: https://git.kernel.org/tip/c9661c1e80b609cd038db7c908e061f0535804ef [2] MSR and CPUID definition: https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0F...
Pu Wen (22): x86/cpu: Create Hygon Dhyana architecture support file x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on Dhyana x86/events: Add Hygon Dhyana support to PMU infrastructure x86/alternative: Init ideal_nops for Hygon Dhyana x86/amd_nb: Check vendor in AMD-only functions x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge x86/apic: Add Hygon Dhyana support x86/bugs: Add Hygon Dhyana to the respective mitigation machinery x86/mce: Add Hygon Dhyana support to the MCA infrastructure x86/kvm: Add Hygon Dhyana support to KVM x86/xen: Add Hygon Dhyana support to Xen ACPI: Add Hygon Dhyana support cpufreq: Add Hygon Dhyana support EDAC, amd64: Add Hygon Dhyana support tools/cpupower: Add Hygon Dhyana support hwmon: (k10temp) Add Hygon Dhyana support x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors i2c-piix4: Add Hygon Dhyana SMBus support x86/amd_nb: Make hygon_nb_misc_ids static NTB: Add Hygon Device ID
Documentation/i2c/busses/i2c-piix4 | 2 + MAINTAINERS | 6 + arch/x86/Kconfig.cpu | 14 + arch/x86/events/amd/core.c | 4 + arch/x86/events/amd/uncore.c | 20 +- arch/x86/events/core.c | 4 + arch/x86/include/asm/amd_nb.h | 3 + arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/include/asm/kvm_emulate.h | 4 + arch/x86/include/asm/mce.h | 2 + arch/x86/include/asm/processor.h | 3 +- arch/x86/include/asm/virtext.h | 5 +- arch/x86/kernel/alternative.c | 4 + arch/x86/kernel/amd_nb.c | 49 ++- arch/x86/kernel/apic/apic.c | 7 + arch/x86/kernel/apic/probe_32.c | 1 + arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/bugs.c | 4 +- arch/x86/kernel/cpu/cacheinfo.c | 31 +- arch/x86/kernel/cpu/common.c | 4 + arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/hygon.c | 413 ++++++++++++++++++ arch/x86/kernel/cpu/mce/core.c | 20 +- arch/x86/kernel/cpu/mce/severity.c | 3 +- arch/x86/kernel/cpu/mtrr/cleanup.c | 3 +- arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- arch/x86/kernel/cpu/perfctr-watchdog.c | 2 + arch/x86/kernel/smpboot.c | 4 +- arch/x86/kvm/emulate.c | 11 +- arch/x86/pci/amd_bus.c | 6 +- arch/x86/xen/pmu.c | 12 +- drivers/acpi/acpi_pad.c | 1 + drivers/acpi/processor_idle.c | 1 + drivers/cpufreq/acpi-cpufreq.c | 5 + drivers/cpufreq/amd_freq_sensitivity.c | 9 +- drivers/edac/amd64_edac.c | 10 +- drivers/edac/mce_amd.c | 4 +- drivers/hwmon/k10temp.c | 3 +- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-piix4.c | 15 +- drivers/ntb/hw/amd/ntb_hw_amd.c | 1 + include/linux/pci_ids.h | 2 + tools/power/cpupower/utils/cpufreq-info.c | 6 +- tools/power/cpupower/utils/helpers/amd.c | 4 +- tools/power/cpupower/utils/helpers/cpuid.c | 8 +- tools/power/cpupower/utils/helpers/helpers.h | 2 +- tools/power/cpupower/utils/helpers/misc.c | 2 +- .../utils/idle_monitor/mperf_monitor.c | 3 +- 48 files changed, 668 insertions(+), 55 deletions(-) create mode 100644 arch/x86/kernel/cpu/hygon.c
Hi Hanjun Guo,
On 2020/3/31 19:24, Hanjun Guo wrote:
Thanks a lot for your patchset, I took a detail look at this patchset, and it looks good to me, I'm pretty happy that this patchset was backported from mainline kernel and you are the maintainer.
For this patchset,
Reviewed-by: Hanjun Guo guohanjun@huawei.com
Thanks.
BTW, do we need updates for compiler, glibc and other usersapce package to recognize Hygon processor or performance optimization? if yes, you can
The current version compiler, glibc and other usersapce programs can run on Hygon processor. We also developed some patches for glibc, hwloc, llvm and so on to enabled some specified functionalities for Hygon processor. Some of them are already upstream.
send those patches to openEuler as well.
Is there any repository for these usersapce programs, how can we send those patches for openEuler?
And I kindly invite you to create a new SIG for Hygon processor in openEuler [1].
Thanks for the invitation. We'll create it later.
On 2020/4/1 23:23, Pu Wen wrote:
Hi Hanjun Guo,
On 2020/3/31 19:24, Hanjun Guo wrote:
Thanks a lot for your patchset, I took a detail look at this patchset, and it looks good to me, I'm pretty happy that this patchset was backported from mainline kernel and you are the maintainer.
For this patchset,
Reviewed-by: Hanjun Guo guohanjun@huawei.com
Thanks.
BTW, do we need updates for compiler, glibc and other usersapce package to recognize Hygon processor or performance optimization? if yes, you can
The current version compiler, glibc and other usersapce programs can run on Hygon processor. We also developed some patches for glibc, hwloc, llvm and so on to enabled some specified functionalities for Hygon processor. Some of them are already upstream.
send those patches to openEuler as well.
Is there any repository for these usersapce programs, how can we send those patches for openEuler?
It's here: https://gitee.com/organizations/src-openeuler/projects for glibc: https://gitee.com/src-openeuler/glibc
Those repositories are not friendly for developers, but you can send the pull request after you patches are ready.
And I kindly invite you to create a new SIG for Hygon processor in openEuler [1].
Thanks for the invitation. We'll create it later.
Great.
Thanks Hanjun
Applied to kernel-4.19.
在 2020/3/31 19:24, Hanjun Guo via Kernel 写道:
Hi Pu Wen,
On 2020/3/31 11:20, Pu Wen wrote:
As a new x86 CPU Vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture between AMD and Haiguang Information Technology Co., Ltd., and aims at providing high performance x86 processor for China server market.
The first generation Hygon's processor(Dhyana) originates from AMD technology and shares most of the architecture with AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/PCIE Device Vendor ID (0x1D94)/Family series number (Family 18h).
To enable the support of Linux kernel to Hygon's CPU, we added a new vendor type (X86_VENDOR_HYGON, with value of 9) in arch/x86/include/ asm/processor.h, and shared most of kernel support codes with AMD family 17h.
As Hygon will negotiate with AMD to make sure that only Hygon will use family 18h, so try to minimize code modification and share most codes with AMD under this consideration.
This patch series have been applied and tested successfully on Hygon Dhyana SoC silicon. Also tested on AMD EPYC (Family 17h) processor, it works fine and makes no harm to the existing codes.
This patch series are created for the current branch openEuler-1.0-LTS.
Thanks a lot for your patchset, I took a detail look at this patchset, and it looks good to me, I'm pretty happy that this patchset was backported from mainline kernel and you are the maintainer.
For this patchset,
Reviewed-by: Hanjun Guo guohanjun@huawei.com
BTW, do we need updates for compiler, glibc and other usersapce package to recognize Hygon processor or performance optimization? if yes, you can send those patches to openEuler as well.
And I kindly invite you to create a new SIG for Hygon processor in openEuler [1].
Thanks Hanjun
References: [1] Linux kernel patches for Hygon Dhyana, merged in 4.20: https://git.kernel.org/tip/c9661c1e80b609cd038db7c908e061f0535804ef [2] MSR and CPUID definition: https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0F...
Pu Wen (22): x86/cpu: Create Hygon Dhyana architecture support file x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on Dhyana x86/events: Add Hygon Dhyana support to PMU infrastructure x86/alternative: Init ideal_nops for Hygon Dhyana x86/amd_nb: Check vendor in AMD-only functions x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge x86/apic: Add Hygon Dhyana support x86/bugs: Add Hygon Dhyana to the respective mitigation machinery x86/mce: Add Hygon Dhyana support to the MCA infrastructure x86/kvm: Add Hygon Dhyana support to KVM x86/xen: Add Hygon Dhyana support to Xen ACPI: Add Hygon Dhyana support cpufreq: Add Hygon Dhyana support EDAC, amd64: Add Hygon Dhyana support tools/cpupower: Add Hygon Dhyana support hwmon: (k10temp) Add Hygon Dhyana support x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors i2c-piix4: Add Hygon Dhyana SMBus support x86/amd_nb: Make hygon_nb_misc_ids static NTB: Add Hygon Device ID
Documentation/i2c/busses/i2c-piix4 | 2 + MAINTAINERS | 6 + arch/x86/Kconfig.cpu | 14 + arch/x86/events/amd/core.c | 4 + arch/x86/events/amd/uncore.c | 20 +- arch/x86/events/core.c | 4 + arch/x86/include/asm/amd_nb.h | 3 + arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/include/asm/kvm_emulate.h | 4 + arch/x86/include/asm/mce.h | 2 + arch/x86/include/asm/processor.h | 3 +- arch/x86/include/asm/virtext.h | 5 +- arch/x86/kernel/alternative.c | 4 + arch/x86/kernel/amd_nb.c | 49 ++- arch/x86/kernel/apic/apic.c | 7 + arch/x86/kernel/apic/probe_32.c | 1 + arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/bugs.c | 4 +- arch/x86/kernel/cpu/cacheinfo.c | 31 +- arch/x86/kernel/cpu/common.c | 4 + arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/hygon.c | 413 ++++++++++++++++++ arch/x86/kernel/cpu/mce/core.c | 20 +- arch/x86/kernel/cpu/mce/severity.c | 3 +- arch/x86/kernel/cpu/mtrr/cleanup.c | 3 +- arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- arch/x86/kernel/cpu/perfctr-watchdog.c | 2 + arch/x86/kernel/smpboot.c | 4 +- arch/x86/kvm/emulate.c | 11 +- arch/x86/pci/amd_bus.c | 6 +- arch/x86/xen/pmu.c | 12 +- drivers/acpi/acpi_pad.c | 1 + drivers/acpi/processor_idle.c | 1 + drivers/cpufreq/acpi-cpufreq.c | 5 + drivers/cpufreq/amd_freq_sensitivity.c | 9 +- drivers/edac/amd64_edac.c | 10 +- drivers/edac/mce_amd.c | 4 +- drivers/hwmon/k10temp.c | 3 +- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-piix4.c | 15 +- drivers/ntb/hw/amd/ntb_hw_amd.c | 1 + include/linux/pci_ids.h | 2 + tools/power/cpupower/utils/cpufreq-info.c | 6 +- tools/power/cpupower/utils/helpers/amd.c | 4 +- tools/power/cpupower/utils/helpers/cpuid.c | 8 +- tools/power/cpupower/utils/helpers/helpers.h | 2 +- tools/power/cpupower/utils/helpers/misc.c | 2 +- .../utils/idle_monitor/mperf_monitor.c | 3 +- 48 files changed, 668 insertions(+), 55 deletions(-) create mode 100644 arch/x86/kernel/cpu/hygon.c
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