- Virt - mailweb.openeuler.org

Virt SIG 12月例会
by openEuler conference 16 Dec '25

16 Dec '25

您好！ Virt 邀请您参加 2025-12-19 14:15 召开的Tencent会议(自动录制) 会议主题：Virt SIG 12月例会会议链接：https://meeting.tencent.com/dm/qwLCg5mLFQyG 会议纪要：https://etherpad.openeuler.org/p/Virt-meetings 更多资讯尽在：https://www.openeuler.org/zh/ Hello! Virt invites you to attend the Tencent conference(auto recording) will be held at 2025-12-19 14:15, The subject of the conference is Virt SIG 12月例会 You can join the meeting at https://meeting.tencent.com/dm/qwLCg5mLFQyG Add topics at https://etherpad.openeuler.org/p/Virt-meetings More information: https://www.openeuler.org/en/

1 0

[PATCH] hw/intc: fix the issue of vNMI not supporting live migration
by Jinqian Yang 21 Nov '25

21 Nov '25

GICD_INMIRn marks SPI as NMI. GICR_INMIR0 marks SGI and PPI as NMI. If GICR_INMIR0 or GICD_INMIRn is not migrated, the vNMI state will be lost on the destination side. Additionally, use a subsection to avoid migration failure when the remote QEMU does not have GICR_INMIR0 support. When migrating from a QEMU that saves GICR_INMIR0 or GICD_INMIRn state to one that does not, the migration will fail with a graceful error message. When migrating from a QEMU that does not save GICR_INMIR0 or GICD_INMIRn state to one that does, the migration will succeed, but the vNMI state will be lost on the destination side since the source did not save it. Sign-off-by: Jinqian Yang <yangjinqian1(a)huawei.com> --- hw/intc/arm_gicv3_common.c | 33 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_kvm.c | 27 ++++++++++++++++++++++++ hw/intc/gicv3_internal.h | 4 ++++ include/hw/intc/arm_gicv3_common.h | 4 ++++ 4 files changed, 68 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 5667d9f40b..9a1fa2ff62 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -164,6 +164,24 @@ const VMStateDescription vmstate_gicv3_gicv4 = { } }; +static bool gicv3_nmi_needed(void *opaque) +{ + GICv3CPUState *cs = opaque; + + return cs->gic->nmi_support; +} + +const VMStateDescription vmstate_gicv3_gicr_nmi = { + .name = "arm_gicv3_cpu/gicr_nmi", + .version_id = 1, + .minimum_version_id = 1, + .needed = gicv3_nmi_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(gicr_inmir0, GICv3CPUState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3_cpu = { .name = "arm_gicv3_cpu", .version_id = 1, @@ -196,6 +214,7 @@ static const VMStateDescription vmstate_gicv3_cpu = { &vmstate_gicv3_cpu_virt, &vmstate_gicv3_cpu_sre_el1, &vmstate_gicv3_gicv4, + &vmstate_gicv3_gicr_nmi, NULL } }; @@ -238,6 +257,17 @@ const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = { } }; +const VMStateDescription vmstate_gicv3_gicd_nmi = { + .name = "arm_gicv3/gicd_nmi", + .version_id = 1, + .minimum_version_id = 1, + .needed = gicv3_nmi_needed, + .fields = (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(gicd_inmir, GICv3State, GICV3_BMP_SIZE), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3 = { .name = "arm_gicv3", .version_id = 1, @@ -266,6 +296,7 @@ static const VMStateDescription vmstate_gicv3 = { }, .subsections = (const VMStateDescription * []) { &vmstate_gicv3_gicd_no_migration_shift_bug, + &vmstate_gicv3_gicd_nmi, NULL } }; @@ -554,6 +585,7 @@ static void arm_gicv3_common_reset_hold(Object *obj) cs->edge_trigger = 0xffff; cs->gicr_igrpmodr0 = 0; cs->gicr_nsacr = 0; + cs->gicr_inmir0 = 0; memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); cs->hppi.prio = 0xff; @@ -585,6 +617,7 @@ static void arm_gicv3_common_reset_hold(Object *obj) memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority)); memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter)); memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr)); + memset(s->gicd_inmir, 0, sizeof(s->gicd_inmir)); /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must * write these to get sane behaviour and we need not populate the * pointer cache here; however having the cache be different for diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index dd2a60fa20..ba6d09a5b9 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -397,6 +397,9 @@ static void kvm_arm_gicv3_put(GICv3State *s) reg = c->gicr_iactiver0; kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, true); + reg = c->gicr_inmir0; + kvm_gicr_access(s, GICR_INMIR0, ncpu, &reg, true); + for (i = 0; i < GIC_INTERNAL; i += 4) { reg = c->gicr_ipriorityr[i] | (c->gicr_ipriorityr[i + 1] << 8) | @@ -561,6 +564,8 @@ static void kvm_arm_gicv3_get(GICv3State *s) c->gicr_ipendr0 = reg; kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, false); c->gicr_iactiver0 = reg; + kvm_gicr_access(s, GICR_INMIR0, ncpu, &reg, false); + c->gicr_inmir0 = reg; for (i = 0; i < GIC_INTERNAL; i += 4) { kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, false); @@ -809,6 +814,22 @@ static void kvm_gicv3_init_cpu_reginfo(CPUState *cs) define_arm_cp_regs(ARM_CPU(cs), gicv3_cpuif_reginfo); } +static bool kvm_gicv3_check_nmi(GICv3State *s) +{ + uint32_t typer = 0; + + if (kvm_device_access(s->dev_fd, + KVM_DEV_ARM_VGIC_GRP_DIST_REGS, + KVM_VGIC_ATTR(GICD_TYPER, 0), + &typer, + false, + NULL)) { + return false; + } + + return (typer & GICD_TYPER_NMI) != 0; +} + static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) { GICv3State *s = KVM_ARM_GICV3(dev); @@ -918,6 +939,12 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { qemu_add_vm_change_state_handler(vm_change_state_handler, s); } + + if (kvm_gicv3_check_nmi(s)) { + s->nmi_support = true; + } else { + s->nmi_support = false; + } } static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 0bed0f6e2a..938c7c5472 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -52,6 +52,7 @@ #define GICD_SGIR 0x0F00 #define GICD_CPENDSGIR 0x0F10 #define GICD_SPENDSGIR 0x0F20 +#define GICD_INMIR 0x0F80 #define GICD_IROUTER 0x6000 #define GICD_IDREGS 0xFFD0 @@ -68,6 +69,8 @@ #define GICD_CTLR_E1NWF (1U << 7) #define GICD_CTLR_RWP (1U << 31) +#define GICD_TYPER_NMI (1U << 9) + #define GICD_TYPER_LPIS_SHIFT 17 /* 16 bits EventId */ @@ -109,6 +112,7 @@ #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) +#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) /* VLPI redistributor registers, offsets from VLPI_base */ #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index b5f8ba17ff..48694fd757 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -173,6 +173,7 @@ struct GICv3CPUState { uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ uint32_t gicr_igrpmodr0; uint32_t gicr_nsacr; + uint32_t gicr_inmir0; uint8_t gicr_ipriorityr[GIC_INTERNAL]; /* VLPI_base page registers */ uint64_t gicr_vpropbaser; @@ -279,11 +280,14 @@ struct GICv3State { */ GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ]; uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)]; + uint32_t gicd_inmir[GICV3_BMP_SIZE]; Notifier cpu_update_notifier; GICv3CPUState *cpu; /* List of all ITSes connected to this GIC */ GPtrArray *itslist; + + bool nmi_support; }; #define GICV3_BITMAP_ACCESSORS(BMP) \ -- 2.33.0

1 0

Virt SIG 11月例会
by openEuler conference 18 Nov '25

18 Nov '25

您好！ Virt 邀请您参加 2025-11-28 14:15 召开的WeLink会议(自动录制) 会议主题：Virt SIG 11月例会会议链接：https://meeting.huaweicloud.com:36443/#/j/989673357 会议纪要：https://etherpad.openeuler.org/p/Virt-meetings 更多资讯尽在：https://www.openeuler.org/zh/ Hello! Virt invites you to attend the WeLink conference(auto recording) will be held at 2025-11-28 14:15, The subject of the conference is Virt SIG 11月例会 You can join the meeting at https://meeting.huaweicloud.com:36443/#/j/989673357 Add topics at https://etherpad.openeuler.org/p/Virt-meetings More information: https://www.openeuler.org/en/

1 0

[PATCH qemu-8.2.0] hw/intc: fix the issue of vNMI not supporting live migration
by Jinqian Yang 05 Nov '25

05 Nov '25

Add the migration of GICR_INMIR0. vNMI migration for SPI is not supported, only supports SGI and PPI in guest. Sign-off-by: Jinqian Yang <yangjinqian1(a)huawei.com> --- hw/intc/arm_gicv3_common.c | 20 ++++++++++++++++++++ hw/intc/arm_gicv3_kvm.c | 22 ++++++++++++++++++++++ hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 3 +++ 4 files changed, 46 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 5667d9f40b..8bf4d15fd3 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -164,6 +164,24 @@ const VMStateDescription vmstate_gicv3_gicv4 = { } }; +static bool gicv3_inmir_needed(void *opaque) +{ + GICv3CPUState *cs = opaque; + + return cs->gic->inmir_support; +} + +const VMStateDescription vmstate_gicv3_cpu_inmir = { + .name = "arm_gicv3_cpu/inmir", + .version_id = 1, + .minimum_version_id = 1, + .needed = gicv3_inmir_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(gicr_inmir0, GICv3CPUState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3_cpu = { .name = "arm_gicv3_cpu", .version_id = 1, @@ -196,6 +214,7 @@ static const VMStateDescription vmstate_gicv3_cpu = { &vmstate_gicv3_cpu_virt, &vmstate_gicv3_cpu_sre_el1, &vmstate_gicv3_gicv4, + &vmstate_gicv3_cpu_inmir, NULL } }; @@ -554,6 +573,7 @@ static void arm_gicv3_common_reset_hold(Object *obj) cs->edge_trigger = 0xffff; cs->gicr_igrpmodr0 = 0; cs->gicr_nsacr = 0; + cs->gicr_inmir0 = 0; memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); cs->hppi.prio = 0xff; diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index dd2a60fa20..77e82e6e2a 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -397,6 +397,9 @@ static void kvm_arm_gicv3_put(GICv3State *s) reg = c->gicr_iactiver0; kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, true); + reg = c->gicr_inmir0; + kvm_gicr_access(s, GICR_INMIR0, ncpu, &reg, true); + for (i = 0; i < GIC_INTERNAL; i += 4) { reg = c->gicr_ipriorityr[i] | (c->gicr_ipriorityr[i + 1] << 8) | @@ -561,6 +564,8 @@ static void kvm_arm_gicv3_get(GICv3State *s) c->gicr_ipendr0 = reg; kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, false); c->gicr_iactiver0 = reg; + kvm_gicr_access(s, GICR_INMIR0, ncpu, &reg, false); + c->gicr_inmir0 = reg; for (i = 0; i < GIC_INTERNAL; i += 4) { kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, false); @@ -809,6 +814,17 @@ static void kvm_gicv3_init_cpu_reginfo(CPUState *cs) define_arm_cp_regs(ARM_CPU(cs), gicv3_cpuif_reginfo); } +static bool kvm_gicv3_check_inmir(GICv3State *s, int cpu) +{ + uint32_t value = 0; + return !kvm_device_access(s->dev_fd, + KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, + KVM_VGIC_ATTR(GICR_INMIR0, cpu), + &value, + false, + NULL) && value != 0; +} + static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) { GICv3State *s = KVM_ARM_GICV3(dev); @@ -918,6 +934,12 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { qemu_add_vm_change_state_handler(vm_change_state_handler, s); } + + if (kvm_gicv3_check_inmir(s, 0)) { + s->inmir_support = true; + } else { + s->inmir_support = false; + } } static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 0bed0f6e2a..2b982716d6 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -109,6 +109,7 @@ #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) +#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) /* VLPI redistributor registers, offsets from VLPI_base */ #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index b5f8ba17ff..4b8012bd89 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -173,6 +173,7 @@ struct GICv3CPUState { uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ uint32_t gicr_igrpmodr0; uint32_t gicr_nsacr; + uint32_t gicr_inmir0; uint8_t gicr_ipriorityr[GIC_INTERNAL]; /* VLPI_base page registers */ uint64_t gicr_vpropbaser; @@ -284,6 +285,8 @@ struct GICv3State { GICv3CPUState *cpu; /* List of all ITSes connected to this GIC */ GPtrArray *itslist; + + bool inmir_support; }; #define GICV3_BITMAP_ACCESSORS(BMP) \ -- 2.33.0

1 0

Virt SIG例会
by openEuler conference 13 Oct '25

13 Oct '25

您好！ Virt 邀请您参加 2025-10-17 14:30 召开的WeLink会议(自动录制) 会议主题：Virt SIG例会会议链接：https://meeting.huaweicloud.com:36443/#/j/985088574 会议纪要：https://etherpad.openeuler.org/p/Virt-meetings 更多资讯尽在：https://www.openeuler.org/zh/ Hello! Virt invites you to attend the WeLink conference(auto recording) will be held at 2025-10-17 14:30, The subject of the conference is Virt SIG例会 You can join the meeting at https://meeting.huaweicloud.com:36443/#/j/985088574 Add topics at https://etherpad.openeuler.org/p/Virt-meetings More information: https://www.openeuler.org/en/

1 0

[PATCH] hw/vfio/migration: Fix vfio migration isn't aborted in a corner case
by Jinqian Yang 28 Sep '25

28 Sep '25

From: Kunkun Jiang <jiangkunkun(a)huawei.com> In the final stage of vfio migration, the destination VM will execute vm_start vfio_vmstate_change vfio_migration_set_state At this time, vfio_migration_set_state may return failure. For example, the device is in the reset process due to some hardware problems. In this case, the vfio migration should be aborted, but the current logic does not abort. Instead, it continues to execute, which will cause Unpredictable impact. This patch fixes this case. Signed-off-by: Kunkun Jiang <jiangkunkun(a)huawei.com> --- hw/vfio/migration.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index b81cb7e23b..8c27298477 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -720,7 +720,7 @@ static void vfio_vmstate_change_prepare(void *opaque, bool running, static void vfio_vmstate_change(void *opaque, bool running, RunState state) { VFIODevice *vbasedev = opaque; - enum vfio_device_mig_state new_state; + enum vfio_device_mig_state new_state, pre_state; int ret; if (running) { @@ -733,6 +733,8 @@ static void vfio_vmstate_change(void *opaque, bool running, RunState state) VFIO_DEVICE_STATE_STOP; } + pre_state = vbasedev->migration->device_state; + /* * If setting the device in new_state fails, the device should be reset. * To do so, use ERROR state as a recover state. @@ -747,6 +749,10 @@ static void vfio_vmstate_change(void *opaque, bool running, RunState state) if (migrate_get_current()->to_dst_file) { qemu_file_set_error(migrate_get_current()->to_dst_file, ret); } + + if (pre_state == VFIO_DEVICE_STATE_RESUMING) { + exit(EXIT_FAILURE); + } } trace_vfio_vmstate_change(vbasedev->name, running, RunState_str(state), -- 2.33.0

1 0

Virt SIG 例会
by openEuler conference 22 Sep '25

22 Sep '25

您好！ Virt 邀请您参加 2025-09-26 14:30 召开的WeLink会议(自动录制) 会议主题：Virt SIG 例会会议链接：https://meeting.huaweicloud.com:36443/#/j/969737091 会议纪要：https://etherpad.openeuler.org/p/Virt-meetings 更多资讯尽在：https://www.openeuler.org/zh/ Hello! Virt invites you to attend the WeLink conference(auto recording) will be held at 2025-09-26 14:30, The subject of the conference is Virt SIG 例会 You can join the meeting at https://meeting.huaweicloud.com:36443/#/j/969737091 Add topics at https://etherpad.openeuler.org/p/Virt-meetings More information: https://www.openeuler.org/en/

1 0

[PATCH] hw/arm/virt: Introduce a IPIV machine option
by Jinqian Yang 18 Sep '25

18 Sep '25

Add the ipiv switch in the "-machine" to allow the guest to more flexibly choose whether to enable ipiv. Signed-off-by: Jinqian Yang <yangjinqian1(a)huawei.com> --- hw/arm/virt.c | 20 ++++++++++++++++++++ include/hw/arm/virt.h | 1 + target/arm/kvm.c | 9 +++++++-- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d8890e319f..576ee0afd0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3054,6 +3054,20 @@ static void virt_set_its(Object *obj, bool value, Error **errp) vms->its = value; } +static bool virt_get_ipiv(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->ipiv; +} + +static void virt_set_ipiv(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->ipiv = value; +} + static void virt_get_dtb_randomness(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -4158,6 +4172,12 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "x-target-impl-cpus", "Describe target cpu impl in the format midr1:revidr1-midr2:revidr2" "Maximum 4 midr:revidr pair is supported"); + + object_class_property_add_bool(oc, "ipiv", + virt_get_ipiv, + virt_set_ipiv); + object_class_property_set_description(oc, "ipiv", + "Set on/off to enable/disable IPIV"); } static char *virt_get_kvm_type(Object *obj, Error **errp G_GNUC_UNUSED) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index fee7c27e0c..a54b0057fb 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -225,6 +225,7 @@ struct VirtMachineState { bool cpu_hotplug_enabled; bool ras; bool mte; + bool ipiv; OnOffAuto dtb_randomness; bool pmu; int smmu_accel_count; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 96b0784b90..d79b667e8c 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -338,10 +338,15 @@ int kvm_arch_get_default_type(MachineState *ms) return fixed_ipa ? 0 : size; } -static void kvm_update_ipiv_cap(KVMState *s) +static void kvm_update_ipiv_cap(MachineState *ms, KVMState *s) { + VirtMachineState *vms = VIRT_MACHINE(ms); int ret; + if (!vms->ipiv) { + return; + } + if (!kvm_check_extension(s, KVM_CAP_ARM_HISI_IPIV)) { return; } @@ -428,7 +433,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } kvm_arm_init_debug(s); - kvm_update_ipiv_cap(s); + kvm_update_ipiv_cap(ms, s); ret = kvm_arm_rme_init(ms); if (ret) { -- 2.33.0

1 0

[PATCH qemu-8.2.0 00/30] Cross-Generation Live Migration
by Jinqian Yang 04 Sep '25

04 Sep '25

Part1: rework id register storage Cornelia Huck ----------------------------------------------------------------- Patch#1 arm/cpu: Add sysreg definitions in cpu-sysregs.h Patch#2 arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Patch#3 arm/cpu: Store aa64isar1/2 into the idregs array Patch#4 arm/cpu: Store aa64pfr0/1 into the idregs array Patch#5 arm/cpu: Store aa64mmfr0-2 into the idregs array Patch#6 arm/cpu: Store aa64dfr0/1 into the idregs array Patch#7 arm/cpu: Store aa64dfr0/1 into the idregs array Patch#8 arm/cpu: Store aa64smfr0 into the idregs array Patch#9 arm/cpu: Store id_isar0-7 into the idregs array Patch#10 arm/cpu: Store id_pfr0/1/2 into the idregs array Patch#11 arm/cpu: Store id_mmfr0-5 into the idregs array Patch#12 arm/cpu: Add sysreg generation scripts Patch#13 arm/cpu: switch to a generated cpu-sysregs.h.inc Part2: Introduce a customizable aarch64 KVM host model ----------------------------------------------------------------- Patch#14 arm/kvm: use fd instead of fdarray[2] Patch#15 arm/cpu: Add infra to handle generated ID register definitions Patch#16 arm/cpu: Add sysreg properties generation Patch#17 arm/cpu: Add generated sysreg properties Patch#18 kvm: kvm_get_writable_id_regs Patch#19 arm/cpu: accessors for writable id registers Patch#20 arm/kvm: Allow reading all the writable ID registers Patch#21 arm/kvm: write back modified ID regs to KVM Patch#22 arm/cpu: more customization for the kvm host cpu model Patch#23 arm-qmp-cmds: introspection for ID register props Patch#24 arm/cpu-features: document ID reg properties Patch#25 arm/cpu: manually make IDR/REVIDR/AIDR writable Patch#26 arm/cpu: enable MIDR writable Part3: Errata management for VM Live migration ----------------------------------------------------------------- Patch#27 target/arm/kvm: Add SMMC hypercall definitions Patch#28 hw/arm/virt: Initial support to set target_impl CPUs Patch#29 target/arm/kvm: Use PSCI_VERSIOn for version info Patch#30 target/arm/kvm: Set DISCOVER_IMPL_* hypercalls Cornelia Huck (7): arm/cpu: switch to a generated cpu-sysregs.h.inc arm/kvm: use fd instead of fdarray[2] arm/cpu: Add generated sysreg properties kvm: kvm_get_writable_id_regs arm/cpu: accessors for writable id registers arm-qmp-cmds: introspection for ID register props arm/cpu-features: document ID reg properties Eric Auger (17): arm/cpu: Add sysreg definitions in cpu-sysregs.h arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays arm/cpu: Store aa64isar1/2 into the idregs array arm/cpu: Store aa64pfr0/1 into the idregs array arm/cpu: Store aa64mmfr0-2 into the idregs array arm/cpu: Store aa64dfr0/1 into the idregs array arm/cpu: Store aa64smfr0 into the idregs array arm/cpu: Store id_isar0-7 into the idregs array arm/cpu: Store id_pfr0/1/2 into the idregs array arm/cpu: Store id_dfr0/1 into the idregs array arm/cpu: Store id_mmfr0-5 into the idregs array arm/cpu: Add sysreg generation scripts arm/cpu: Add infra to handle generated ID register definitions arm/cpu: Add sysreg properties generation arm/kvm: Allow reading all the writable ID registers arm/kvm: write back modified ID regs to KVM arm/cpu: more customization for the kvm host cpu model Qingtong Jia (2): arm/cpu: manually make IDR/REVIDR/AIDR writable arm/cpu: enable MIDR writable Shameer Kolothum (4): target/arm/kvm: Add SMMC hypercall definitions hw/arm/virt: Initial support to set target_impl CPUs target/arm/kvm: Use PSCI_VERSIOn for version info target/arm/kvm: Set DISCOVER_IMPL_* hypercalls MAINTAINERS | 1 + accel/kvm/kvm-all.c | 7 + docs/system/arm/cpu-features.rst | 104 +++- hw/arm/virt.c | 65 ++- hw/intc/armv7m_nvic.c | 27 +- include/hw/boards.h | 3 + scripts/arm-gen-cpu-sysregs-header.awk | 40 ++ scripts/gen-cpu-sysreg-properties.awk | 346 +++++++++++ scripts/update-aarch64-sysreg-code.sh | 35 ++ target/arm/arm-qmp-cmds.c | 19 + target/arm/cpu-custom.h | 60 ++ target/arm/cpu-features.h | 295 +++++----- target/arm/cpu-sysreg-properties.c | 764 +++++++++++++++++++++++++ target/arm/cpu-sysregs.h | 48 ++ target/arm/cpu-sysregs.h.inc | 55 ++ target/arm/cpu.c | 124 ++-- target/arm/cpu.h | 126 +++- target/arm/cpu64.c | 202 ++++--- target/arm/helper.c | 66 +-- target/arm/hvf/hvf.c | 23 +- target/arm/internals.h | 6 +- target/arm/kvm-rme.c | 5 +- target/arm/kvm.c | 188 +++++- target/arm/kvm64.c | 365 +++++++++--- target/arm/kvm_arm.h | 46 +- target/arm/meson.build | 1 + target/arm/ptw.c | 6 +- target/arm/tcg/cpu32.c | 498 ++++++++-------- target/arm/tcg/cpu64.c | 455 +++++++-------- target/arm/trace-events | 8 + 30 files changed, 3035 insertions(+), 953 deletions(-) create mode 100755 scripts/arm-gen-cpu-sysregs-header.awk create mode 100755 scripts/gen-cpu-sysreg-properties.awk create mode 100755 scripts/update-aarch64-sysreg-code.sh create mode 100644 target/arm/cpu-custom.h create mode 100644 target/arm/cpu-sysreg-properties.c create mode 100644 target/arm/cpu-sysregs.h create mode 100644 target/arm/cpu-sysregs.h.inc -- 2.33.0

1 30

[PATCH qemu-8.2 0/1] hw/intc: fix the issue of vNMI not supporting live migration
by Jinqian Yang 28 Aug '25

28 Aug '25

Jinqian Yang (1): hw/intc: fix the issue of vNMI not supporting live migration hw/intc/arm_gicv3_common.c | 2 ++ hw/intc/arm_gicv3_kvm.c | 5 +++++ hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 1 + 4 files changed, 9 insertions(+) -- 2.33.0

1 0