[Virt] [PATCH 0/6] Add RISC-V vm migration support

This series adds RISC-V vm migration support.

Yifei Jiang (6): target/riscv: raise exception to HS mode at get_physical_address target/riscv: Add sifive_plic vmstate target/riscv: Support riscv cpu vmstate target/riscv: Add kvm_riscv_get/put_regs_timer target/riscv: Implement virtual time adjusting with vm state changing target/riscv: Support virtual time context synchronization

hw/riscv/sifive_plic.c | 24 +++++++++- include/hw/riscv/sifive_plic.h | 1 + target/riscv/cpu.c | 31 +++++++++++- target/riscv/cpu.h | 7 +++ target/riscv/cpu_helper.c | 12 ++++- target/riscv/kvm.c | 86 ++++++++++++++++++++++++++++++++++ 6 files changed, 156 insertions(+), 5 deletions(-)