Currently, host cpu is inherited simply.
Signed-off-by: Yifei Jiang jiangyifei@huawei.com Signed-off-by: Yipeng Yin yinyipeng1@huawei.com --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 1 + 2 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73af94efb..b7de444fb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -192,6 +192,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); }
+static void riscv_host_cpu_init(Object *obj) +{ +} + #endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -603,10 +607,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif };
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df6d95b16..f69f38df7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -40,6 +40,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))