The ZIP hardware design is compatible with the old BD, eliminating the need for uadk adaptation. Therefore, the special processing for v5 has been removed. In stateful decompression, the hardware reports its context state in ctx_core_status (the low 9 bits of dw30/isize). When ctx_core_status is non-zero while neither input is consumed nor output produced, the hardware needs the request to be resent. Return WD_EAGAIN to the user so that the request can be retried. Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com> --- drv/hisi_comp.c | 24 ++++++++++++++++++------ v1/drv/hisi_zip_udrv.c | 17 +++++++++++++++-- v1/drv/hisi_zip_udrv.h | 1 + 3 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drv/hisi_comp.c b/drv/hisi_comp.c index c75e734..b798811 100644 --- a/drv/hisi_comp.c +++ b/drv/hisi_comp.c @@ -60,6 +60,7 @@ #define HZ_DECOMP_END 0x13 #define HZ_CTX_ST_MASK 0x000f +#define HZ_CTX_CORE_STATUS_MASK 0x1ff #define HZ_CTX_BFINAL_MASK 0x80 #define HZ_CTX_STORE_MASK 0x7ffff #define HZ_LSTBLK_MASK 0x0100 @@ -81,6 +82,7 @@ #define max_in_data_size(outl) ((__u32)(((__u64)(outl) << 3) / 9) & 0xfffffffc) #define HZ_MAX_SIZE (8 * 1024 * 1024) +#define LZ4_MAX_SIZE ((__u32)0x100000) #define HW_CTX_SIZE 0x10000 #define RSV_OFFSET 64 @@ -726,15 +728,12 @@ static int check_lz4_msg(struct wd_comp_msg *msg, enum wd_buff_type buf_type) return -WD_EINVAL; } - if (buf_type != WD_FLAT_BUF) - return 0; - - if (unlikely(msg->req.src_len == 0 || msg->req.src_len > HZ_MAX_SIZE)) { - WD_ERR("invalid: lz4 input size can't be zero or more than 8M size max!\n"); + if (unlikely(msg->req.src_len == 0 || msg->req.src_len > LZ4_MAX_SIZE)) { + WD_ERR("invalid: lz4 input size can't be zero or more than 1M size max!\n"); return -WD_EINVAL; } - if (unlikely(msg->avail_out > HZ_MAX_SIZE)) + if (unlikely(msg->avail_out > HZ_MAX_SIZE && buf_type == WD_FLAT_BUF)) msg->avail_out = HZ_MAX_SIZE; return 0; @@ -1672,6 +1671,7 @@ static int parse_zip_sqe(struct hisi_qp *qp, struct hisi_zip_sqe *sqe, struct wd_comp_msg *msg) { __u32 buf_type = (sqe->dw9 & HZ_BUF_TYPE_MASK) >> BUF_TYPE_SHIFT; + __u16 ctx_core_status = sqe->isize & HZ_CTX_CORE_STATUS_MASK; __u32 ctx_win_len = sqe->ctx_dw2 & CTX_WIN_LEN_MASK; __u16 ctx_st = sqe->ctx_dw0 & HZ_CTX_ST_MASK; __u16 lstblk = sqe->dw3 & HZ_LSTBLK_MASK; @@ -1731,6 +1731,18 @@ static int parse_zip_sqe(struct hisi_qp *qp, struct hisi_zip_sqe *sqe, (sqe->ctx_dw0 & HZ_CTX_BFINAL_MASK) && (sqe->ctx_dw1 & HZ_CTX_STORE_MASK)) recv_msg->req.status = WD_EAGAIN; + /* + * The ctx_core_status reflects the hardware context state. + * In stateful decompression, if it is non-zero while neither + * input is consumed nor output produced, the hardware + * needs the request to be resent with more input and output, + * so report WD_EAGAIN to the user. + */ + if (!recv_msg->req.status && recv_msg->stream_mode == WD_COMP_STATEFUL && + recv_msg->req.op_type == WD_DIR_DECOMPRESS && ctx_core_status && + !recv_msg->in_cons && !recv_msg->produced) + recv_msg->req.status = WD_EAGAIN; + /* * It need to analysis the data cache by hardware. * If the cache data is a complete huffman block, diff --git a/v1/drv/hisi_zip_udrv.c b/v1/drv/hisi_zip_udrv.c index b73a929..96604cd 100644 --- a/v1/drv/hisi_zip_udrv.c +++ b/v1/drv/hisi_zip_udrv.c @@ -447,7 +447,7 @@ int qm_parse_zip_sqe(void *hw_msg, const struct qm_queue_info *info, qm_parse_zip_sqe_set_status(recv_msg, status, lstblk, ctx_st); if (ctx_st == HW_DECOMPING_NO_SPACE && recv_msg->in_size == recv_msg->in_cons && ctx_bfinal && (sqe->ctx_dw1 & HZ_CTX_STORE_MASK)) - recv_msg->status = WCRYPTO_DECOMP_BLK_NOSTART; + recv_msg->status = WCRYPTO_DECOMP_END_NOSPACE; return 1; } @@ -850,6 +850,7 @@ int qm_parse_zip_sqe_v3(void *hw_msg, const struct qm_queue_info *info, { struct wcrypto_comp_msg *recv_msg = info->req_cache[i]; struct hisi_zip_sqe_v3 *sqe = hw_msg; + __u16 ctx_core_status = sqe->isize & HZ_CTX_CORE_STATUS_MASK; __u16 ctx_bfinal = sqe->ctx_dw0 & HZ_CTX_BFINAL_MASK; __u32 ctx_win_len = sqe->ctx_dw2 & CTX_WIN_LEN_MASK; __u16 ctx_st = sqe->ctx_dw0 & HZ_CTX_ST_MASK; @@ -912,7 +913,19 @@ int qm_parse_zip_sqe_v3(void *hw_msg, const struct qm_queue_info *info, qm_parse_zip_sqe_set_status(recv_msg, status, lstblk, ctx_st); if (ctx_st == HW_DECOMPING_NO_SPACE && recv_msg->in_size == recv_msg->in_cons && ctx_bfinal && (sqe->ctx_dw1 & HZ_CTX_STORE_MASK)) - recv_msg->status = WCRYPTO_DECOMP_BLK_NOSTART; + recv_msg->status = WCRYPTO_DECOMP_END_NOSPACE; + + /* + * The ctx_core_status reflects the hardware context state. + * In stateful decompression, if it is non-zero while neither + * input is consumed nor output produced, the hardware + * needs the request to be resent with more input and output, + * so report WD_EAGAIN to the user. + */ + if (!recv_msg->status && recv_msg->stream_mode == WCRYPTO_COMP_STATEFUL && + recv_msg->op_type == WCRYPTO_INFLATE && ctx_core_status && + !recv_msg->in_cons && !recv_msg->produced) + recv_msg->status = WD_EAGAIN; /* * It need to analysis the data cache by hardware. diff --git a/v1/drv/hisi_zip_udrv.h b/v1/drv/hisi_zip_udrv.h index 1037f43..f1abb5e 100644 --- a/v1/drv/hisi_zip_udrv.h +++ b/v1/drv/hisi_zip_udrv.h @@ -120,6 +120,7 @@ struct hisi_zip_sqe_v3 { #define HZ_REF_VTYPE_SHIFT 12 #define HZ_BLK_SIZE_SHIFT 16 #define HZ_CTX_ST_MASK 0x000f +#define HZ_CTX_CORE_STATUS_MASK 0x1ff #define HZ_CTX_BFINAL_MASK 0x80 #define HZ_CTX_STORE_MASK 0x7ffff #define HZ_LSTBLK_MASK 0x0100 -- 2.43.0