January 2024 - Kernel - mailweb.openeuler.org

openEuler Kernel SIG双周例会
by openEuler conference 10 Jan '24

10 Jan '24

您好！ Kernel SIG 邀请您参加 2024-01-12 14:00 召开的WeLink会议(自动录制) 会议主题：openEuler Kernel SIG双周例会会议内容： 1. 进展update 2. 议题征集中（新增议题可直接回复本邮件申报，也可填至会议看板）会议链接：https://bmeeting.huaweicloud.com:36443/#/j/983665981 会议纪要：https://etherpad.openeuler.org/p/Kernel-meetings 温馨提醒：建议接入会议后修改参会人的姓名，也可以使用您在gitee.com的ID 更多资讯尽在：https://openeuler.org/zh/ Hello! openEuler Kernel SIG invites you to attend the WeLink conference(auto recording) will be held at 2024-01-12 14:00, The subject of the conference is openEuler Kernel SIG双周例会, Summary: 1. 进展update 2. 议题征集中（新增议题可直接回复本邮件申报，也可填至会议看板） You can join the meeting at https://bmeeting.huaweicloud.com:36443/#/j/983665981. Add topics at https://etherpad.openeuler.org/p/Kernel-meetings. Note: You are advised to change the participant name after joining the conference or use your ID at gitee.com. More information: https://openeuler.org/en/

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[PATCH OLK-6.6 0/4] Add L3T and LPDDRC pmu
by Chen Jun 10 Jan '24

10 Jan '24

Chen Jun (4): perf: hisi: Make irq shared perf: hisi: Fix read sccl_id and ccl_id error in some platform perf: hisi: Add support for HiSilicon SoC L3T PMU perf: hisi: Add support for HiSilicon SoC LPDDRC PMU arch/arm64/configs/openeuler_defconfig | 2 + drivers/perf/hisilicon/Kconfig | 18 + drivers/perf/hisilicon/Makefile | 2 + drivers/perf/hisilicon/hisi_uncore_l3t_pmu.c | 403 +++++++++++++++++ .../perf/hisilicon/hisi_uncore_lpddrc_pmu.c | 408 ++++++++++++++++++ drivers/perf/hisilicon/hisi_uncore_pmu.c | 46 +- drivers/perf/hisilicon/hisi_uncore_pmu.h | 2 + 7 files changed, 870 insertions(+), 11 deletions(-) create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3t_pmu.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_lpddrc_pmu.c -- 2.17.1

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[PATCH OLK-6.6 1/3] KVM: arm64: Probe Hisi CPU TYPE from ACPI/DTB
by lishusen 10 Jan '24

10 Jan '24

From: Zenghui Yu <yuzenghui(a)huawei.com> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8TN8N CVE: NA ---------------------------------------------------- Parse ACPI/DTB to get where the hypervisor is running. Signed-off-by: Zenghui Yu <yuzenghui(a)huawei.com> Signed-off-by: Yanan Wang <wangyanan55(a)huawei.com> Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> Signed-off-by: lishusen <lishusen2(a)huawei.com> --- arch/arm64/include/asm/hisi_cpu_model.h | 19 ++++++ arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/arm.c | 6 ++ arch/arm64/kvm/hisi_cpu_model.c | 83 +++++++++++++++++++++++++ 5 files changed, 110 insertions(+) create mode 100644 arch/arm64/include/asm/hisi_cpu_model.h create mode 100644 arch/arm64/kvm/hisi_cpu_model.c diff --git a/arch/arm64/include/asm/hisi_cpu_model.h b/arch/arm64/include/asm/hisi_cpu_model.h new file mode 100644 index 000000000000..f686a7591e8f --- /dev/null +++ b/arch/arm64/include/asm/hisi_cpu_model.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright(c) 2019 Huawei Technologies Co., Ltd + */ + +#ifndef __HISI_CPU_MODEL_H__ +#define __HISI_CPU_MODEL_H__ + +enum hisi_cpu_type { + HI_1612, + HI_1616, + HI_1620, + UNKNOWN_HI_TYPE +}; + +extern enum hisi_cpu_type hi_cpu_type; + +void probe_hisi_cpu_type(void); +#endif /* __HISI_CPU_MODEL_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index af06ccb7ee34..5154085849fa 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -27,6 +27,7 @@ #include <asm/fpsimd.h> #include <asm/kvm.h> #include <asm/kvm_asm.h> +#include <asm/hisi_cpu_model.h> #define __KVM_HAVE_ARCH_INTC_INITIALIZED diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index c0c050e53157..86c6ded87eeb 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -15,6 +15,7 @@ kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ guest.o debug.o reset.o sys_regs.o stacktrace.o \ vgic-sys-reg-v3.o fpsimd.o pkvm.o \ arch_timer.o trng.o vmid.o emulate-nested.o nested.o \ + hisi_cpu_model.o \ vgic/vgic.o vgic/vgic-init.o \ vgic/vgic-irqfd.o vgic/vgic-v2.o \ vgic/vgic-v3.o vgic/vgic-v4.o \ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 4866b3f7b4ea..9d57a57283b3 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -56,6 +56,9 @@ DECLARE_KVM_NVHE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); static bool vgic_present, kvm_arm_initialised; +/* Hisi cpu type enum */ +enum hisi_cpu_type hi_cpu_type = UNKNOWN_HI_TYPE; + static DEFINE_PER_CPU(unsigned char, kvm_hyp_initialized); DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use); @@ -2415,6 +2418,9 @@ static __init int kvm_arm_init(void) return err; } + /* Probe the Hisi CPU type */ + probe_hisi_cpu_type(); + in_hyp_mode = is_kernel_in_hyp_mode(); if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) || diff --git a/arch/arm64/kvm/hisi_cpu_model.c b/arch/arm64/kvm/hisi_cpu_model.c new file mode 100644 index 000000000000..4d5a099bc27a --- /dev/null +++ b/arch/arm64/kvm/hisi_cpu_model.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright(c) 2019 Huawei Technologies Co., Ltd + */ + +#include <linux/acpi.h> +#include <linux/of.h> +#include <linux/init.h> +#include <linux/kvm_host.h> + +#ifdef CONFIG_ACPI + +/* ACPI Hisi oem table id str */ +const char *oem_str[] = { + "HIP06", /* Hisi 1612 */ + "HIP07", /* Hisi 1616 */ + "HIP08" /* Hisi 1620 */ +}; + +/* + * Get Hisi oem table id. + */ +static void acpi_get_hw_cpu_type(void) +{ + struct acpi_table_header *table; + acpi_status status; + int i, str_size = ARRAY_SIZE(oem_str); + + /* Get oem table id from ACPI table header */ + status = acpi_get_table(ACPI_SIG_DSDT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err("Failed to get ACPI table: %s\n", + acpi_format_exception(status)); + return; + } + + for (i = 0; i < str_size; ++i) { + if (!strncmp(oem_str[i], table->oem_table_id, 5)) { + hi_cpu_type = i; + return; + } + } +} + +#else +static void acpi_get_hw_cpu_type(void) {} +#endif + +/* of Hisi cpu model str */ +const char *of_model_str[] = { + "Hi1612", + "Hi1616" +}; + +static void of_get_hw_cpu_type(void) +{ + const char *cpu_type; + int ret, i, str_size = ARRAY_SIZE(of_model_str); + + ret = of_property_read_string(of_root, "model", &cpu_type); + if (ret < 0) { + pr_err("Failed to get Hisi cpu model by OF.\n"); + return; + } + + for (i = 0; i < str_size; ++i) { + if (strstr(cpu_type, of_model_str[i])) { + hi_cpu_type = i; + return; + } + } +} + +void probe_hisi_cpu_type(void) +{ + if (!acpi_disabled) + acpi_get_hw_cpu_type(); + else + of_get_hw_cpu_type(); + + if (hi_cpu_type == UNKNOWN_HI_TYPE) + pr_warn("UNKNOWN Hisi cpu type.\n"); +} -- 2.33.0

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[PATH OLK-6.6 0/3] sync vgic-its from 5.10 to 6.6
by jiaqingtong 10 Jan '24

10 Jan '24

sync vgic-its from 5.10 to 6.6 depent on GICv4,test on 6.6 mainline with NIC PCI passthrough Heyi Guo (1): KVM: arm64: vgic-its: Flush pending LPIs when nuking DT Xiangyou Xie (2): KVM: arm/arm64: vgic-its: Introduce multiple LPI translation caches KVM: arm/arm64: vgic-its: Do not execute invalidate MSI-LPI translation cache on movi command arch/arm64/kvm/vgic/vgic-init.c | 8 +- arch/arm64/kvm/vgic/vgic-its.c | 255 +++++++++++++++++++++----------- include/kvm/arm_vgic.h | 13 +- 3 files changed, 183 insertions(+), 93 deletions(-) base-commit: ade260241330687a9006159f604a00deac794776 -- 2.43.GIT

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[PATCH OLK-6.6 v7 0/5] block: Add config to show info about opening a mounted device for write
by Li Lingfeng 10 Jan '24

10 Jan '24

v1->v2: 1) Replace BLK_DEV_DUMPINFO with BLK_DEV_WRITE_MOUNTED_QUIET, which is logically opposite; 2) Make BLK_DEV_WRITE_MOUNTED_QUIET dependent on BLK_DEV_WRITE_MOUNTED, and decide whether to set bd_writers by BLK_DEV_WRITE_MOUNTED_QUIET; 3) Move bdev_dump_info() into bdev_may_open(); 4) Add the cmdline interface to control whether to show info; 5) Pass the state of "writes blocked" to part0 when mounting a partition. v2->v3: Add restriction for modifying bd_writers. v3->v4: 1) Count bd_writers regardless of whether bdev_allow_write_mounted is set; 2) Expand the meaning of bdev_allow_write_mounted; 3) Add config option to detect writing to part0 while partitions mounted; 4) Add bd_mounters to record the number of times that part0 or partition is mounted; 5) Show info about opening a lower device for write while upper-layers mounted. v4->v5: Move introduction of bd_mounters to patch1. v5->v6: Delete redundant conflict judgment. v6->v7: 1) Replace BLK_DEV_WRITE_MOUNTED_QUIET with BLK_DEV_WRITE_MOUNTED_DUMP. 2) Remove restriction for setting bdev_allow_write_mounted by cmdline. Li Lingfeng (5): block: Count writers and mounters regardless of whether bdev_allow_write_mounted is set block: Expand the meaning of bdev_allow_write_mounted block: Add config option to detect writing to part0 while partitions mounted block: Add config option to show info about opening a mounted device for write block: Show info about opening a lower device for write while upper-layers mounted block/Kconfig | 17 +++++++ block/bdev.c | 95 ++++++++++++++++++++++++++++++++------- include/linux/blk_types.h | 1 + 3 files changed, 98 insertions(+), 15 deletions(-) -- 2.31.1

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[PATCH OLK-6.6 0/2] cgroup: Support iocost for cgroup v1
by Li Nan 10 Jan '24

10 Jan '24

Li Nan (2): cgroup: Support iocost for cgroup v1 openeuler_defconfig: enable iocost in openeuler_defconfig for x86 and arm64 block/blk-iocost.c | 27 ++++++++++++++++++++++++++ arch/arm64/configs/openeuler_defconfig | 4 +++- arch/x86/configs/openeuler_defconfig | 4 +++- block/Kconfig | 10 ++++++++++ 4 files changed, 43 insertions(+), 2 deletions(-) -- 2.39.2

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[PATCH OLK-6.6 1/3] KVM: arm64: Adjust entry/exit and trap related tracepoints
by lishusen 10 Jan '24

10 Jan '24

virt inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4IZPY CVE: NA ------------------------------------------------- Currently, we use trace_kvm_exit() to report exception type (e.g., "IRQ", "TRAP") and exception class (ESR_ELx's bit[31:26]) together. But hardware only saves the exit class to ESR_ELx on synchronous exceptions, not on asynchronous exceptions. When the guest exits due to external interrupts, we will get tracing output like: "kvm_exit: IRQ: HSR_EC: 0x0000 (UNKNOWN), PC: 0xffff87259e30" Obviously, "HSR_EC" here is meaningless. This patch splits "exit" and "trap" events by adding two tracepoints explicitly in handle_trap_exceptions(). Let trace_kvm_exit() report VM exit events, and trace_kvm_trap_exit() report VM trap events. These tracepoints are adjusted also in preparation for supporting 'perf kvm stat' on arm64. Signed-off-by: Zenghui Yu <yuzenghui(a)huawei.com> Reviewed-by: Hailiang Zhang <zhang.zhanghailiang(a)huawei.com> Signed-off-by: Zenghui Yu <yuzenghui(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> Link: https://lore.kernel.org/r/1560330526-15468-3-git-send-email-yuzenghui@huawe… Link: https://gitee.com/openeuler/kernel/commit/14b85d8d7d2d Reviewed-by: Yanan Wang <wangyanan55(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> Signed-off-by: lishusen <lishusen2(a)huawei.com> --- arch/arm64/kvm/arm.c | 4 ++-- arch/arm64/kvm/handle_exit.c | 3 +++ arch/arm64/kvm/trace_arm.h | 21 +++++++++--------- arch/arm64/kvm/trace_handle_exit.h | 35 ++++++++++++++++++++++++++++++ 4 files changed, 51 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 70fc3d00f82c..db1ea653a471 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1029,7 +1029,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) /************************************************************** * Enter the guest */ - trace_kvm_entry(*vcpu_pc(vcpu)); + trace_kvm_entry(vcpu->vcpu_id, *vcpu_pc(vcpu)); guest_timing_enter_irqoff(); ret = kvm_arm_vcpu_enter_exit(vcpu); @@ -1086,7 +1086,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) local_irq_enable(); - trace_kvm_exit(ret, kvm_vcpu_trap_get_class(vcpu), *vcpu_pc(vcpu)); + trace_kvm_exit(vcpu->vcpu_id, ret, *vcpu_pc(vcpu)); /* Exit types that need handling before we can be preempted */ handle_exit_early(vcpu, ret); diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 617ae6dea5d5..a8e370435e54 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -309,7 +309,10 @@ static int handle_trap_exceptions(struct kvm_vcpu *vcpu) exit_handle_fn exit_handler; exit_handler = kvm_get_exit_handler(vcpu); + trace_kvm_trap_enter(vcpu->vcpu_id, + kvm_vcpu_trap_get_class(vcpu)); handled = exit_handler(vcpu); + trace_kvm_trap_exit(vcpu->vcpu_id); } return handled; diff --git a/arch/arm64/kvm/trace_arm.h b/arch/arm64/kvm/trace_arm.h index 8ad53104934d..4a87477e2261 100644 --- a/arch/arm64/kvm/trace_arm.h +++ b/arch/arm64/kvm/trace_arm.h @@ -13,40 +13,41 @@ * Tracepoints for entry/exit to guest */ TRACE_EVENT(kvm_entry, - TP_PROTO(unsigned long vcpu_pc), - TP_ARGS(vcpu_pc), + TP_PROTO(unsigned int vcpu_id, unsigned long vcpu_pc), + TP_ARGS(vcpu_id, vcpu_pc), TP_STRUCT__entry( + __field( unsigned int, vcpu_id ) __field( unsigned long, vcpu_pc ) ), TP_fast_assign( + __entry->vcpu_id = vcpu_id; __entry->vcpu_pc = vcpu_pc; ), - TP_printk("PC: 0x%016lx", __entry->vcpu_pc) + TP_printk("VCPU %u: PC=0x%016lx", __entry->vcpu_id, __entry->vcpu_pc) ); TRACE_EVENT(kvm_exit, - TP_PROTO(int ret, unsigned int esr_ec, unsigned long vcpu_pc), - TP_ARGS(ret, esr_ec, vcpu_pc), + TP_PROTO(unsigned int vcpu_id, int ret, unsigned long vcpu_pc), + TP_ARGS(vcpu_id, ret, vcpu_pc), TP_STRUCT__entry( + __field( unsigned int, vcpu_id ) __field( int, ret ) - __field( unsigned int, esr_ec ) __field( unsigned long, vcpu_pc ) ), TP_fast_assign( + __entry->vcpu_id = vcpu_id; __entry->ret = ARM_EXCEPTION_CODE(ret); - __entry->esr_ec = ARM_EXCEPTION_IS_TRAP(ret) ? esr_ec : 0; __entry->vcpu_pc = vcpu_pc; ), - TP_printk("%s: HSR_EC: 0x%04x (%s), PC: 0x%016lx", + TP_printk("VCPU %u: exit_type=%s, PC=0x%016lx", + __entry->vcpu_id, __print_symbolic(__entry->ret, kvm_arm_exception_type), - __entry->esr_ec, - __print_symbolic(__entry->esr_ec, kvm_arm_exception_class), __entry->vcpu_pc) ); diff --git a/arch/arm64/kvm/trace_handle_exit.h b/arch/arm64/kvm/trace_handle_exit.h index 064a58c19f48..cda43f243f7e 100644 --- a/arch/arm64/kvm/trace_handle_exit.h +++ b/arch/arm64/kvm/trace_handle_exit.h @@ -8,6 +8,41 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm +TRACE_EVENT(kvm_trap_enter, + TP_PROTO(unsigned int vcpu_id, unsigned int esr_ec), + TP_ARGS(vcpu_id, esr_ec), + + TP_STRUCT__entry( + __field(unsigned int, vcpu_id) + __field(unsigned int, esr_ec) + ), + + TP_fast_assign( + __entry->vcpu_id = vcpu_id; + __entry->esr_ec = esr_ec; + ), + + TP_printk("VCPU %u: HSR_EC=0x%04x (%s)", + __entry->vcpu_id, + __entry->esr_ec, + __print_symbolic(__entry->esr_ec, kvm_arm_exception_class)) +); + +TRACE_EVENT(kvm_trap_exit, + TP_PROTO(unsigned int vcpu_id), + TP_ARGS(vcpu_id), + + TP_STRUCT__entry( + __field(unsigned int, vcpu_id) + ), + + TP_fast_assign( + __entry->vcpu_id = vcpu_id; + ), + + TP_printk("VCPU %u", __entry->vcpu_id) +); + TRACE_EVENT(kvm_wfx_arm64, TP_PROTO(unsigned long vcpu_pc, bool is_wfe), TP_ARGS(vcpu_pc, is_wfe), -- 2.33.0

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[PATCH OLK-6.6] sched/core: Change depends of SCHED_CORE
by Xia Fukun 09 Jan '24

09 Jan '24

From: Lin Shengwang <linshengwang1(a)huawei.com> hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8UVUS CVE: NA -------------------------------------------------------------------------- Due to the conflict between Core Scheduling and SMT expeller, so SCHED_CORE and QOS_SCHED_SMT_EXPELLER are mutually exclusive. Signed-off-by: Lin Shengwang <linshengwang1(a)huawei.com> Signed-off-by: Xia Fukun <xiafukun(a)huawei.com> --- kernel/Kconfig.preempt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/Kconfig.preempt b/kernel/Kconfig.preempt index c2f1fd95a821..dc2a630f200a 100644 --- a/kernel/Kconfig.preempt +++ b/kernel/Kconfig.preempt @@ -117,7 +117,7 @@ config PREEMPT_DYNAMIC config SCHED_CORE bool "Core Scheduling for SMT" - depends on SCHED_SMT + depends on SCHED_SMT && !QOS_SCHED_SMT_EXPELLER help This option permits Core Scheduling, a means of coordinated task selection across SMT siblings. When enabled -- see -- 2.34.1

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[PATCH OLK-6.6 v4 0/8] introduce smart_grid zone
by Yipeng Zou 09 Jan '24

09 Jan '24

The patch sets include two parts: 1. patch 1~3: Rebase smart_grid from OLK-5.10 to OLK-6.6 2. patch 4~7: introduce smart_grid zone qos and cpufreq Since V3: 1. fix some review comments Since V2: 1. move new sysctl form sysctl.c to fair.c 2. add smart_grid cmdline Since V1: 1. Don't init smart_grid cpufreq with dynamic_affinity disable. 2. Forbid smart_grid cgroup interface with dynamic_affinity disable. Hui Tang (1): sched: Introduce smart grid scheduling strategy for cfs Wang ShaoBo (2): sched: smart grid: init sched_grid_qos structure on QOS purpose config: enable CONFIG_QOS_SCHED_SMART_GRID by default Yipeng Zou (5): sched: introduce smart grid qos zone smart_grid: introduce /proc/pid/smart_grid_level smart_grid: introduce smart_grid_strategy_ctrl sysctl smart_grid: cpufreq: introduce smart_grid cpufreq control smart_grid: introduce smart_grid cmdline arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + drivers/cpufreq/cpufreq.c | 244 +++++++++++ fs/proc/array.c | 16 + fs/proc/base.c | 84 ++++ include/linux/cpufreq.h | 11 + include/linux/sched.h | 31 ++ include/linux/sched/grid_qos.h | 135 +++++++ init/Kconfig | 13 + kernel/fork.c | 15 + kernel/sched/Makefile | 1 + kernel/sched/core.c | 181 +++++++++ kernel/sched/fair.c | 537 ++++++++++++++++++++++++- kernel/sched/grid/Makefile | 2 + kernel/sched/grid/internal.h | 6 + kernel/sched/grid/power.c | 27 ++ kernel/sched/grid/qos.c | 279 +++++++++++++ kernel/sched/grid/stat.c | 47 +++ kernel/sched/sched.h | 48 ++- mm/mempolicy.c | 11 +- 20 files changed, 1679 insertions(+), 11 deletions(-) create mode 100644 include/linux/sched/grid_qos.h create mode 100644 kernel/sched/grid/Makefile create mode 100644 kernel/sched/grid/internal.h create mode 100644 kernel/sched/grid/power.c create mode 100644 kernel/sched/grid/qos.c create mode 100644 kernel/sched/grid/stat.c -- 2.34.1

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[PATCH OLK-6.6] sched/smt: fix unbalance sched_smt_present dec/inc
by Xia Fukun 09 Jan '24

09 Jan '24

From: Yang Yingliang <yangyingliang(a)huawei.com> hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8UR4U CVE: NA -------------------------------- If cpuset_cpu_inactive() fails in sched_cpu_deactivate(), the cpu offline failed, but sched_smt_present is decreased before calling sched_cpu_deactivate, it leads unbalance dec/inc, so fix it by increasing sched_smt_present in the error path. Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> Signed-off-by: Xia Fukun <xiafukun(a)huawei.com> --- kernel/sched/core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 7a0997e7e136..adecea9c607d 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -9792,6 +9792,10 @@ int sched_cpu_deactivate(unsigned int cpu) ret = cpuset_cpu_inactive(cpu); if (ret) { balance_push_set(cpu, false); +#ifdef CONFIG_SCHED_SMT + if (cpumask_weight(cpu_smt_mask(cpu)) == 2) + static_branch_inc_cpuslocked(&sched_smt_present); +#endif set_cpu_active(cpu, true); sched_update_numa(cpu, true); return ret; -- 2.34.1

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