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[PATCH OLK-5.10 0/5] cpumask: cleanup nr_cpu_ids vs nr_cpumask_bits mess
by Lu Jialin 12 Dec '23

12 Dec '23

From: Zheng Zucheng <zhengzucheng(a)huawei.com> Yury Norov (5): mainline inclusion from mainline-v6.1-rc1 commit 53fc190cc6771c5494d782210334d4ebb50c7103 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8KQBZ CVE: NA mainline inclusion from mainline-v6.1-rc1 commit 38bef8e57f2149acd2c910a98f57dd6291d2e0ec category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8KQBZ CVE: NA mainline inclusion from mainline-v6.1-rc1 commit 7102b3bb070fdf4580a05cbfc5ad3c0691dc4bf9 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8KQBZ CVE: NA mainline inclusion from mainline-v6.1-rc1 commit aa47a7c215e79a2ade6916f163c5a17b561bce4f category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8KQBZ CVE: NA mainline inclusion from mainline-v6.1-rc1 commit 6f9c07be9d020489326098801f0661f754c7c865 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8KQBZ CVE: NA arch/loongarch/kernel/setup.c | 2 +- arch/mips/kernel/setup.c | 2 +- arch/x86/kernel/smpboot.c | 4 ++-- arch/x86/xen/smp_pv.c | 2 +- include/linux/cpumask.h | 22 +++++++++++----------- kernel/smp.c | 6 ++++-- lib/Kconfig | 9 +++++++++ 7 files changed, 29 insertions(+), 18 deletions(-) -- 2.34.1

2 6

[PATCH OLK-6.6 v5 0/6] Ascend features
by Yuan Can 12 Dec '23

12 Dec '23

Navid Emamdoost (1): nbd_genl_status: null check for nla_nest_start Weilong Chen (2): ACPI / APEI: Notify all ras err to driver arm64/ascend: Add new enable_oom_killer interface for oom contrl Xu Qiang (2): irq-gic-v3: Add support to init ts core GICR irq-gic-v3-its: It can't be initialized when the GICR had been cut Yuan Can (1): ascend: export interfaces required by ascend drivers arch/arm64/configs/openeuler_defconfig | 1 + drivers/acpi/apei/Kconfig | 7 + drivers/acpi/apei/ghes.c | 8 +- drivers/block/nbd.c | 6 + drivers/irqchip/Kconfig | 7 + drivers/irqchip/irq-gic-v3-its.c | 254 ++++++++++++++++++++++++- drivers/irqchip/irq-gic-v3.c | 101 +++++++++- include/linux/irqchip/arm-gic-v3.h | 5 + include/linux/oom.h | 24 +++ kernel/power/autosleep.c | 1 + kernel/workqueue.c | 3 + mm/Kconfig | 10 + mm/memcontrol.c | 20 ++ mm/oom_kill.c | 58 ++++++ mm/util.c | 2 + mm/vmalloc.c | 2 + 16 files changed, 500 insertions(+), 9 deletions(-) -- 2.17.1

2 7

[PATCH OLK-6.6 v2 0/4] xfs: fix some misc issue
by Long Li 12 Dec '23

12 Dec '23

his patch set fix some mics xfs issue: Long Li (4): xfs: fix a UAF when inode item push xfs: fix a UAF in xfs_iflush_abort_clean xfs: don't verify agf length when log recovery xfs: xfs_trans_cancel() path must check for log shutdown fs/xfs/libxfs/xfs_alloc.c | 3 ++- fs/xfs/xfs_buf.c | 5 +++++ fs/xfs/xfs_inode_item.c | 8 +++++++- fs/xfs/xfs_trans.c | 2 +- 4 files changed, 15 insertions(+), 3 deletions(-) -- 2.31.1

2 5

[PATCH OLK-5.10] arm64: cpufeature: Add missing .field_width for system registers
by Wang ShaoBo 12 Dec '23

12 Dec '23

hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8NRI6 CVE: NA -------------------------------- This was missed when making specification of a field standard. Fixes: 2ee4c87e5fd2e ("arm64: cpufeature: Always specify and use a field width for capabilities") Signed-off-by: Wang ShaoBo <bobo.shaobowang(a)huawei.com> --- arch/arm64/kernel/cpufeature.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b13deca20432e..6c07804d94667 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2324,6 +2324,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64PFR0_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64PFR0_MPAM_SHIFT, + .field_width = 4, .min_field_value = ID_AA64PFR0_MPAM, }, #endif /* CONFIG_MPAM */ @@ -2605,6 +2606,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64MMFR1_EL1, .field_pos = ID_AA64MMFR1_TWED_SHIFT, + .field_width = 4, .sign = FTR_UNSIGNED, .min_field_value = 1, }, @@ -2616,6 +2618,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR2_WFXT_SHIFT, + .field_width = 4, .matches = has_cpuid_feature, .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED, }, @@ -2626,6 +2629,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, + .field_width = 4, .matches = has_cpuid_feature, .min_field_value = 1, }, @@ -2635,6 +2639,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64MMFR1_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64MMFR1_HPD_SHIFT, + .field_width = 4, .matches = has_cpuid_feature, .min_field_value = 2, }, @@ -2646,6 +2651,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64MMFR1_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64MMFR1_HPD_SHIFT, + .field_width = 4, .matches = plat_can_use_pbha_stage1, .min_field_value = 2, .cpu_enable = cpu_enable_pbha, -- 2.25.1

2 1

[PATCH OLK-5.10] locking/osq_lock: Avoid false sharing in optimistic_spin_node
by Zeng Heng 12 Dec '23

12 Dec '23

hulk inclusion category: performance bugzilla: https://gitee.com/openeuler/kernel/issues/I8MV01 -------------------------------- In the prologue of osq_lock(), it set `cpu` member of percpu struct optimistic_spin_node with the local cpu id, after that the value is never changed any more. Consequently, we can regard the `cpu` member as a constant variable. In the meanwhile, other members like next, prev and locked are frequently modified by osq_lock() and osq_unlock() which come from rwsem, mutex and so on. So here we can place padding and split them into different cache lines, so that avoid cache misses when a cpu is spinning to check previous node's cpu field by vcpu_is_preempted() in the following. Here provide the UnixBench full-core test result as below: Machine Intel(R) Xeon(R) Gold 6248 CPU, 40 cores, 80 threads Run the command of "./Run -c 80 -i 3" 10 times and take the average. System Benchmarks Index Values Without Patch With Patch Diff Dhrystone 2 using register variables 185876.43 185945.41 0.04% Double-Precision Whetstone 79637.27 79659.29 0.03% Execl Throughput 9909.61 10576.06 6.73% File Copy 1024 bufsize 2000 maxblocks 1723.01 2086.08 21.07% File Copy 256 bufsize 500 maxblocks 1150.24 1338.21 16.34% File Copy 4096 bufsize 8000 maxblocks 3719.19 4011.99 7.87% Pipe Throughput 66184.84 66025.25 -0.24% Pipe-based Context Switching 30606.18 31074.21 1.53% Process Creation 9442.48 9450.77 0.09% Shell Scripts (1 concurrent) 44526.52 46548.54 4.54% Shell Scripts (8 concurrent) 42903.96 45718.56 6.56% System Call Overhead 3645.20 3717.42 1.98% ======== System Benchmarks Index Score 15126.87 15931.29 5.32% Signed-off-by: Zeng Heng <zengheng4(a)huawei.com> --- include/linux/osq_lock.h | 2 +- kernel/locking/osq_lock.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/linux/osq_lock.h b/include/linux/osq_lock.h index 5581dbd3bd34..deb90ad5f560 100644 --- a/include/linux/osq_lock.h +++ b/include/linux/osq_lock.h @@ -9,7 +9,7 @@ struct optimistic_spin_node { struct optimistic_spin_node *next, *prev; int locked; /* 1 if lock acquired */ - int cpu; /* encoded CPU # + 1 value */ + int cpu ____cacheline_aligned; /* encoded CPU # + 1 value */ }; struct optimistic_spin_queue { diff --git a/kernel/locking/osq_lock.c b/kernel/locking/osq_lock.c index 1de006ed3aa8..1e1a79580e96 100644 --- a/kernel/locking/osq_lock.c +++ b/kernel/locking/osq_lock.c @@ -96,7 +96,13 @@ bool osq_lock(struct optimistic_spin_queue *lock) node->locked = 0; node->next = NULL; - node->cpu = curr; + /* + * After this cpu member is initialized for the first time, it + * would no longer change in fact. That could avoid cache misses + * when spin and access the cpu member by other CPUs. + */ + if (!node->cpu) + node->cpu = curr; /* * We need both ACQUIRE (pairs with corresponding RELEASE in -- 2.25.1

2 1

[PATCH OLK-6.6 0/6] Add support for hisi HBM devices
by Zhang Zekun 12 Dec '23

12 Dec '23

Add support for HISI HBM device, and HBM ACLS repair. The patch set includes three functionalities. 1. Add support for hbm device hotplug. 2. provide extra information with hbm locality information 3. Add support for HBM acls repair. Zhang Zekun (6): ACPI: OSL: Export the symbol of acpi_hotplug_schedule soc: hisilicon: hisi_hbmdev: Add power domain control methods ACPI: memhotplug: export the state of each hotplug device soc: hisilicon: hisi_hbmdev: Provide extra memory topology information soc: hbmcache: Add support for online and offline the hbm cache soc: hisilicon: hisi_hbmdev: Add hbm acls repair and query methods drivers/acpi/acpi_memhotplug.c | 22 ++ drivers/acpi/internal.h | 1 - drivers/acpi/osl.c | 1 + drivers/base/container.c | 1 + drivers/soc/hisilicon/Kconfig | 36 +++ drivers/soc/hisilicon/Makefile | 3 + drivers/soc/hisilicon/hisi_hbmcache.c | 147 +++++++++ drivers/soc/hisilicon/hisi_hbmdev.c | 435 ++++++++++++++++++++++++++ drivers/soc/hisilicon/hisi_internal.h | 31 ++ include/linux/acpi.h | 2 + include/linux/memory_hotplug.h | 1 + 11 files changed, 679 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/hisilicon/hisi_hbmcache.c create mode 100644 drivers/soc/hisilicon/hisi_hbmdev.c create mode 100644 drivers/soc/hisilicon/hisi_internal.h -- 2.17.1

2 7

[PATCH OLK-5.10] KVM: arm64: Translate logic cluster id to physical cluster id when updating lsudvmbm
by chenxiang 12 Dec '23

12 Dec '23

From: Xiang Chen <chenxiang66(a)hisilicon.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8HY1B ---------------------------------------------------------------- For dvmbm feature, MN requires physical cluster id while it is filled with logic cluster id right now. In some situations which physical cluster id is not equal to logic cluster id such as in PG boards, it will cause issues when enabling dvmbm. To avoid the issue, translate logic cluster id to physical cluster id when updating lsudvmbm. Signed-off-by: Xiang Chen <chenxiang66(a)hisilicon.com> Signed-off-by: Cai Jian <caijian11(a)h-partners.com> --- arch/arm64/kvm/hisilicon/hisi_virt.c | 166 +++++++++++++++++++++++++-- 1 file changed, 157 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index 10233b801896..1f4a8e44228e 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -236,12 +236,113 @@ static int kvm_dvmbm_get_dies_info(struct kvm *kvm, u64 *vm_aff3s, int size) return num; } +#define MAX_CLUSTERS_PER_DIE 8 +#define TB_MN_BASE 0x00C6067f0000 +#define TA_MN_BASE 0x0046067F0000 +#define CHIP_ADDR_OFFSET(_chip) (((((_chip) >> 3) & 0x1) * 0x80000000000) + \ + ((((_chip) >> 2) & 0x1) * (0x100000000000)) + \ + (((_chip) & 0x3) * 0x200000000000)) +#define MAX_PG_CFG_SKITS 4 +#define MAX_PG_CFG_DIES 2 +#define MN_ECO0_OFFSET 0xc00 +#define SOCKET_ID_MASK 0xf8 +#define SOCKET_ID_SHIFT 3 +#define DIE_ID_MASK 0x7 + +static u32 socket_num, die_num; + +static void kvm_get_socket_num(u32 *socket_num) +{ + int socket_id[MAX_PG_CFG_SKITS], cpu; + u32 num = 0; + + for_each_cpu(cpu, cpu_possible_mask) { + bool found = false; + u64 aff3, socket; + int i; + + aff3 = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 3); + /* aff3[7:3]: socket ID */ + socket = (aff3 & SOCKET_ID_MASK) >> SOCKET_ID_SHIFT; + for (i = 0; i < num; i++) { + if (socket_id[i] == socket) { + found = true; + break; + } + } + if (!found) + socket_id[num++] = socket; + } + *socket_num = num; +} + +static void kvm_get_die_num(u32 *die_num) +{ + int die_id[MAX_PG_CFG_DIES], cpu; + u32 num = 0; + + for_each_cpu(cpu, cpu_possible_mask) { + bool found = false; + u64 aff3, die; + int i; + + aff3 = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 3); + /* aff3[2:0]: die ID */ + die = aff3 & DIE_ID_MASK; + for (i = 0; i < num; i++) { + if (die_id[i] == die) { + found = true; + break; + } + } + if (!found) + die_id[num++] = die; + } + *die_num = num; +} + +static u32 g_pg_cfg[MAX_PG_CFG_SKITS * MAX_PG_CFG_DIES]; + +static u64 kvm_switch_aff2_logic_to_phy(unsigned long pg_cfg, u64 logic_aff2) +{ + u32 pg_num = 0, i, j; + u32 cluster_pg[MAX_CLUSTERS_PER_DIE]; + u32 pg_flag[MAX_CLUSTERS_PER_DIE]; + + for (i = 0; i < MAX_CLUSTERS_PER_DIE; i++) { + if (test_bit(i, &pg_cfg)) + pg_num++; + cluster_pg[i] = i; + pg_flag[i] = 0; + } + + for (i = 0; i < MAX_CLUSTERS_PER_DIE - pg_num; i++) { + if (test_bit(i, &pg_cfg)) { + for (j = 0; j < pg_num; j++) { + u32 cluster_bak = MAX_CLUSTERS_PER_DIE - pg_num + j; + + if (!test_bit(cluster_bak, &pg_cfg) && + !pg_flag[cluster_bak]) { + pg_flag[cluster_bak] = 1; + cluster_pg[i] = cluster_bak; + cluster_pg[cluster_bak] = i; + break; + } + } + } + } + + return cluster_pg[logic_aff2]; +} + static void kvm_update_vm_lsudvmbm(struct kvm *kvm) { - u64 mpidr, aff3, aff2, aff1; + u64 mpidr, aff3, aff2, aff1, phy_aff2; u64 vm_aff3s[DVMBM_MAX_DIES]; u64 val; int cpu, nr_dies; + unsigned long pg_cfg; + u32 socket_id; nr_dies = kvm_dvmbm_get_dies_info(kvm, vm_aff3s, DVMBM_MAX_DIES); if (nr_dies > 2) { @@ -258,8 +359,14 @@ static void kvm_update_vm_lsudvmbm(struct kvm *kvm) mpidr = cpu_logical_map(cpu); aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2); aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1); - - val |= 1ULL << (aff2 * 4 + aff1); + socket_id = (aff3 & SOCKET_ID_MASK) >> SOCKET_ID_SHIFT; + + if ((vm_aff3s[0] & DIE_ID_MASK) == 0x3) /* TB totem */ + pg_cfg = g_pg_cfg[0 + socket_id * die_num] & 0xff; + else /* TA totem */ + pg_cfg = g_pg_cfg[1 + socket_id * die_num] & 0xff; + phy_aff2 = kvm_switch_aff2_logic_to_phy(pg_cfg, aff2); + val |= 1ULL << (phy_aff2 * 4 + aff1); } goto out_update; @@ -268,7 +375,7 @@ static void kvm_update_vm_lsudvmbm(struct kvm *kvm) /* nr_dies == 2 */ val = DVMBM_RANGE_TWO_DIES << DVMBM_RANGE_SHIFT | DVMBM_GRAN_CLUSTER << DVMBM_GRAN_SHIFT | - vm_aff3s[0] << DVMBM_DIE1_SHIFT | + vm_aff3s[0] << DVMBM_DIE1_SHIFT | vm_aff3s[1] << DVMBM_DIE2_SHIFT; /* and fulfill bits [43:0] */ @@ -276,11 +383,23 @@ static void kvm_update_vm_lsudvmbm(struct kvm *kvm) mpidr = cpu_logical_map(cpu); aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3); aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2); - - if (aff3 == vm_aff3s[0]) - val |= 1ULL << (aff2 + DVMBM_DIE1_CLUSTER_SHIFT); - else - val |= 1ULL << (aff2 + DVMBM_DIE2_CLUSTER_SHIFT); + socket_id = (aff3 & SOCKET_ID_MASK) >> SOCKET_ID_SHIFT; + + if (aff3 == vm_aff3s[0]) { + if ((vm_aff3s[0] & DIE_ID_MASK) == 0x3) /* TB totem */ + pg_cfg = g_pg_cfg[0 + socket_id * die_num] & 0xff; + else /* TA totem */ + pg_cfg = g_pg_cfg[1 + socket_id * die_num] & 0xff; + phy_aff2 = kvm_switch_aff2_logic_to_phy(pg_cfg, aff2); + val |= 1ULL << (phy_aff2 + DVMBM_DIE1_CLUSTER_SHIFT); + } else { + if ((vm_aff3s[1] & DIE_ID_MASK) == 0x3) /* TB totem */ + pg_cfg = g_pg_cfg[0 + socket_id * die_num] & 0xff; + else /* TA totem */ + pg_cfg = g_pg_cfg[1 + socket_id * die_num] & 0xff; + phy_aff2 = kvm_switch_aff2_logic_to_phy(pg_cfg, aff2); + val |= 1ULL << (phy_aff2 + DVMBM_DIE2_CLUSTER_SHIFT); + } } out_update: @@ -357,6 +476,33 @@ void kvm_hisi_dvmbm_put(struct kvm_vcpu *vcpu) */ } +static void kvm_get_pg_cfg(u32 *pg_cfgs) +{ + void __iomem *mn_base; + u32 i, j; + u64 mn_phy_base; + u32 val; + + kvm_get_socket_num(&socket_num); + kvm_get_die_num(&die_num); + for (i = 0; i < socket_num; i++) { + for (j = 0; j < die_num; j++) { + mn_phy_base = (j == 0) ? TB_MN_BASE : TA_MN_BASE; + mn_phy_base += CHIP_ADDR_OFFSET(i); + mn_phy_base += MN_ECO0_OFFSET; + + mn_base = ioremap(mn_phy_base, 4); + if (!mn_base) { + kvm_info("MN base addr ioremap fail\n"); + return; + } + val = readl_relaxed(mn_base); + pg_cfgs[j + i * die_num] = val & 0xff; + iounmap(mn_base); + } + } +} + int kvm_hisi_init_dvmbm(struct kvm *kvm) { if (!kvm_dvmbm_support) @@ -367,6 +513,8 @@ int kvm_hisi_init_dvmbm(struct kvm *kvm) if (!kvm->arch.dvm_cpumask) return -ENOMEM; + kvm_get_pg_cfg(g_pg_cfg); + return 0; } -- 2.30.0

3 3

[PATCH OLK-6.6 v4 0/7] support userswap feature
by Peng Zhang 12 Dec '23

12 Dec '23

From: ZhangPeng <zhangpeng362(a)huawei.com> This patch series support userswap feature including registration, unregistration, swap-out and swap-in. Userswap feature depends on CONFIG_USERSWAP and can be enabled by cmdline enable_userswap. We tested the concurrent scenario of multi-threaded page fault and multi-threaded swap-in in the uswap demo;and the remapping in the swap-out phase and the copy-free function in the swap-in phase were ok. During the test, related debugging functions including CONFIG_DEBUG_VM, lockdep, slub debug, kasan and kmemleak are enabled. ChangeLog: v3->v4: - define UFFDIO_REGISTER_MODE_USWAP ((__u64)1<<10) rather than ((__u64)1<<3) v2->v3: - update patch 7 commit v1->v2: - enable CONFIG_USERSWAP for openeuler_defconfig ZhangPeng (7): mm/userswap: add VM_USWAP and SWP_USERSWAP_ENTRY mm/userswap: add enable_userswap boot option mm/userswap: introduce MREMAP_USWAP_SET_PTE mm/userswap: support userswap via userfaultfd mm/userswap: introduce UFFDIO_COPY_MODE_DIRECT_MAP mm/userswap: provide cpu info in userfault msg mm/userswap: openeuler_defconfig: enable userswap arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + fs/proc/task_mmu.c | 3 + fs/userfaultfd.c | 43 +- include/linux/mm.h | 8 + include/linux/swap.h | 14 +- include/linux/swapops.h | 16 + include/linux/userfaultfd_k.h | 5 + include/linux/userswap.h | 60 +++ include/trace/events/mmflags.h | 7 + include/uapi/linux/mman.h | 1 + include/uapi/linux/userfaultfd.h | 3 + mm/Kconfig | 10 + mm/Makefile | 1 + mm/memory.c | 8 + mm/mremap.c | 8 +- mm/userfaultfd.c | 12 + mm/userswap.c | 552 +++++++++++++++++++++++++ 18 files changed, 747 insertions(+), 6 deletions(-) create mode 100644 include/linux/userswap.h create mode 100644 mm/userswap.c -- 2.25.1

2 8

[PATCH OLK-6.6] amba-pl011: Fix no irq issue due to no IRQ domain found
by Lin Yujun 12 Dec '23

12 Dec '23

From: Lin Ruizhe <linruizhe(a)huawei.com> hulk inclusion category: bugfix bugzilla: 176552 https://gitee.com/openeuler/kernel/issues/I4DDEL ------------------------------------------------- If pl011 interrupt is connected to MBIGEN interrupt controller, because the mbigen initialization is too late, which will lead to no IRQ due to no IRQ domain found, logs is shown below, "irq: no irq domain found for uart0 !" When dev->irq[0] is zero, try to get IRQ by of_irq_get() again, and return -EPROBE_DEFER if the IRQ domain is not yet created. Using deferred probing mechanism to fix the issue. Signed-off-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> Signed-off-by: Lin ruizhe <linruizhe(a)huawei.com> Signed-off-by: He Ying <heying24(a)huawei.com> Signed-off-by: Chen Jun <chenjun102(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> conflicts: drivers/tty/serial/amba-pl011.c Signed-off-by: Lin Yujun <linyujun809(a)huawei.com> --- drivers/tty/serial/amba-pl011.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 3dc9b0fcab1c..648f99d4774c 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2815,10 +2815,20 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) uap->vendor = vendor; uap->fifosize = vendor->get_fifosize(dev); uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; - uap->port.irq = dev->irq[0]; uap->port.ops = &amba_pl011_pops; uap->port.rs485_config = pl011_rs485_config; uap->port.rs485_supported = pl011_rs485_supported; + + /* if no irq domain found, irq number is 0, try again */ + if (!dev->irq[0] && dev->dev.of_node) { + ret = of_irq_get(dev->dev.of_node, 0); + if (ret < 0) + return ret; + dev->irq[0] = ret; + } + + uap->port.irq = dev->irq[0]; + snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { -- 2.34.1

3 2

[PATCH OLK-6.6] x86/ioapic: add an interface for driver to sync hardware data into memory
by Lin Yujun 12 Dec '23

12 Dec '23

From: Hongbo Yao <yaohongbo(a)huawei.com> hulk inclusion category: bugfix bugzilla: 20890, https://gitee.com/openeuler/kernel/issues/I5ZV1W -------------------------------- The default interrupt trigger mode of Pci driver is Level, however, some pci drivers want to change irq trigger mode to edge by writing hardware register directly. In current kernel, this kind of driver needs to sync entry data which has already been reservd in memory. This patch provides an interface for the driver to sync entry data in memory. Signed-off-by: Hongbo Yao <yaohongbo(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> Signed-off-by: zhangyi (F) <yi.zhang(a)huawei.com> Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> Reviewed-by: Zhang Jianhua <chris.zjh(a)huawei.com> Reviewed-by: Liao Chang <liaochang1(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> Signed-off-by: Lin Yujun <linyujun809(a)huawei.com> --- arch/x86/include/asm/io_apic.h | 1 + arch/x86/kernel/apic/io_apic.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index 51c782600e02..435ae723a238 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -174,6 +174,7 @@ extern void clear_IO_APIC(void); extern void restore_boot_irq_mode(void); extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin); extern void print_IO_APICs(void); +extern void ioapic_sync_hardware_data(int irq); #else /* !CONFIG_X86_IO_APIC */ #define IO_APIC_IRQ(x) 0 diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 00da6cf6b07d..d256e0b57e94 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1202,6 +1202,31 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) } EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); +/* + * The function is only provided for Drivers to keep the data value in + * memory consistent with the value of the register, and these drivers + * must use it carefully. + * + * The correct step should be: + * Change register ---> ioapic_sync_hardware_data ---> request_irq + */ +void ioapic_sync_hardware_data(int irq) +{ + struct IO_APIC_route_entry entry; + struct mp_chip_data *data; + struct irq_pin_list *pin_list; + + data = irq_get_chip_data(irq); + for_each_irq_pin(pin_list, data->irq_2_pin) { + entry = ioapic_read_entry(pin_list->apic, pin_list->pin); + data->entry.trigger = entry.trigger; + data->entry.polarity = entry.polarity; + pr_debug("irq[%d] update trigger[%d] polarity[%d]\n", + irq, entry.trigger, entry.polarity); + } +} +EXPORT_SYMBOL(ioapic_sync_hardware_data); + static struct irq_chip ioapic_chip, ioapic_ir_chip; static void __init setup_IO_APIC_irqs(void) -- 2.34.1

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