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[PATCH openEuler-1.0-LTS 1/3] drivers : remove drivers/soc/hisilicon/lbc
by Yang Yingliang 22 Nov '21

22 Nov '21

From: fengsheng <fengsheng5(a)huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4IYWE?from=project-issue CVE: NA ------------------------------------------------------------ This driver is not in use. Remove it. Signed-off-by: fengsheng <fengsheng5(a)huawei.com> Reviewed-by: lidongming <lidongming5(a)huawei.com> Reviewed-by: ouyang delong <ouyangdelong(a)huawei.com> Acked-by: Xie XiuQi <xiexiuqi(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- MAINTAINERS | 5 - arch/arm64/configs/hulk_defconfig | 1 - arch/arm64/configs/openeuler_defconfig | 1 - arch/arm64/configs/storage_ci_defconfig | 1 - arch/arm64/configs/syzkaller_defconfig | 1 - arch/x86/configs/openeuler_defconfig | 1 - arch/x86/configs/storage_ci_defconfig | 1 - drivers/soc/hisilicon/Kconfig | 1 - drivers/soc/hisilicon/Makefile | 1 - drivers/soc/hisilicon/lbc/Kconfig | 3 - drivers/soc/hisilicon/lbc/Makefile | 2 - drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c | 466 ----------------------- drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h | 120 ------ 13 files changed, 604 deletions(-) delete mode 100644 drivers/soc/hisilicon/lbc/Kconfig delete mode 100644 drivers/soc/hisilicon/lbc/Makefile delete mode 100644 drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c delete mode 100644 drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h diff --git a/MAINTAINERS b/MAINTAINERS index 15609985b6cc6..b84c7cbd4e555 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16332,11 +16332,6 @@ S: Buried alive in reporters F: * F: */ -HISILICON LOCALBUS DRIVER -M: Feng Sheng <fengsheng5(a)huawei.com> -S: Maintained -F: drivers/soc/hisilicon/lbc/ - HISILICON SYSCTRL DRIVER M: Feng Sheng <fengsheng5(a)huawei.com> S: Maintained diff --git a/arch/arm64/configs/hulk_defconfig b/arch/arm64/configs/hulk_defconfig index a2a2216e43f1e..904e9b557122e 100644 --- a/arch/arm64/configs/hulk_defconfig +++ b/arch/arm64/configs/hulk_defconfig @@ -281,7 +281,6 @@ CONFIG_ARCH_XGENE=y # CONFIG_ARCH_ZYNQMP is not set CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y CONFIG_SOC_HISILICON_SYSCTL=m -CONFIG_SOC_HISILICON_LBC=m # # Enable Livepatch diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 089f5be748b10..20ad626791d14 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -5011,7 +5011,6 @@ CONFIG_ARM_SMMU_V3=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y diff --git a/arch/arm64/configs/storage_ci_defconfig b/arch/arm64/configs/storage_ci_defconfig index f468538f22a52..6d671761fd080 100644 --- a/arch/arm64/configs/storage_ci_defconfig +++ b/arch/arm64/configs/storage_ci_defconfig @@ -2219,7 +2219,6 @@ CONFIG_CLKSRC_VERSATILE=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set diff --git a/arch/arm64/configs/syzkaller_defconfig b/arch/arm64/configs/syzkaller_defconfig index eb045bdc5ef16..7c8eca466e25a 100644 --- a/arch/arm64/configs/syzkaller_defconfig +++ b/arch/arm64/configs/syzkaller_defconfig @@ -281,7 +281,6 @@ CONFIG_ARCH_XGENE=y # CONFIG_ARCH_ZYNQMP is not set CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y CONFIG_SOC_HISILICON_SYSCTL=m -CONFIG_SOC_HISILICON_LBC=m # # Enable Livepatch # diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 5a56a81e39e19..0700ef6fc0cf0 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -6168,7 +6168,6 @@ CONFIG_IRQ_REMAP=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set diff --git a/arch/x86/configs/storage_ci_defconfig b/arch/x86/configs/storage_ci_defconfig index 0847b17d293a0..27de222f67966 100644 --- a/arch/x86/configs/storage_ci_defconfig +++ b/arch/x86/configs/storage_ci_defconfig @@ -2389,7 +2389,6 @@ CONFIG_PCC=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig index 520f60cec77b7..6dd657e3eaa98 100644 --- a/drivers/soc/hisilicon/Kconfig +++ b/drivers/soc/hisilicon/Kconfig @@ -1,3 +1,2 @@ -source "drivers/soc/hisilicon/lbc/Kconfig" source "drivers/soc/hisilicon/sysctl/Kconfig" diff --git a/drivers/soc/hisilicon/Makefile b/drivers/soc/hisilicon/Makefile index 33a64532ace35..fe68ce0d54c3e 100644 --- a/drivers/soc/hisilicon/Makefile +++ b/drivers/soc/hisilicon/Makefile @@ -1,2 +1 @@ -obj-y += lbc/ obj-y += sysctl/ diff --git a/drivers/soc/hisilicon/lbc/Kconfig b/drivers/soc/hisilicon/lbc/Kconfig deleted file mode 100644 index 054b6634dae9a..0000000000000 --- a/drivers/soc/hisilicon/lbc/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config SOC_HISILICON_LBC - tristate - default m \ No newline at end of file diff --git a/drivers/soc/hisilicon/lbc/Makefile b/drivers/soc/hisilicon/lbc/Makefile deleted file mode 100644 index d7ec052cb42e2..0000000000000 --- a/drivers/soc/hisilicon/lbc/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -lbc-objs := hs_lbc_pltfm.o -obj-$(CONFIG_SOC_HISILICON_LBC) += lbc.o \ No newline at end of file diff --git a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c b/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c deleted file mode 100644 index c188cd308f862..0000000000000 --- a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/of.h> -#include <linux/of_platform.h> -#include <linux/spinlock.h> -#include <linux/of_address.h> -#include <linux/acpi.h> - -#include "hs_lbc_pltfm.h" - -#define LBC_DRIVER_VERSION "1.9.39.0" - -struct hisi_lbc_dev g_lbc_dev = {0}; - -static void lbc_set_cs_base_addr(unsigned int index, unsigned int cs_base_addr) -{ - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - lbc_reg->cs_base[index] = cs_base_addr; -} - -static void lbc_set_cs_data_width(unsigned int index, unsigned int width) -{ - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - lbc_reg->cs_ctrl[index].data_width = width; -} - -static void lbc_set_cs_data_offset(unsigned int index, unsigned int offset) -{ - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - lbc_reg->cs_ctrl[index].addr_offset = offset; -} - -static void lbc_set_cs_mem_size(unsigned int index, u64 mem_size) -{ - unsigned int size = 0; - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - switch (mem_size) { - case LBC_CS_MEM_SIZE_0: - size = LBC_CS_MEM_SIZE_REG_0; - break; - case LBC_CS_MEM_SIZE_64K: - size = LBC_CS_MEM_SIZE_REG_64K; - break; - case LBC_CS_MEM_SIZE_128K: - size = LBC_CS_MEM_SIZE_REG_128K; - break; - case LBC_CS_MEM_SIZE_256K: - size = LBC_CS_MEM_SIZE_REG_256K; - break; - case LBC_CS_MEM_SIZE_512K: - size = LBC_CS_MEM_SIZE_REG_512K; - break; - case LBC_CS_MEM_SIZE_1M: - size = LBC_CS_MEM_SIZE_REG_1M; - break; - case LBC_CS_MEM_SIZE_2M: - size = LBC_CS_MEM_SIZE_REG_2M; - break; - case LBC_CS_MEM_SIZE_4M: - size = LBC_CS_MEM_SIZE_REG_4M; - break; - case LBC_CS_MEM_SIZE_8M: - size = LBC_CS_MEM_SIZE_REG_8M; - break; - case LBC_CS_MEM_SIZE_16M: - size = LBC_CS_MEM_SIZE_REG_16M; - break; - case LBC_CS_MEM_SIZE_32M: - size = LBC_CS_MEM_SIZE_REG_32M; - break; - case LBC_CS_MEM_SIZE_64M: - size = LBC_CS_MEM_SIZE_REG_64M; - break; - case LBC_CS_MEM_SIZE_128M: - size = LBC_CS_MEM_SIZE_REG_128M; - break; - case LBC_CS_MEM_SIZE_256M: - size = LBC_CS_MEM_SIZE_REG_256M; - break; - default: - size = 0; - } - - lbc_reg->cs_ctrl[index].mem_size = size; -} - -static int hisi_lbc_para_check(unsigned int index, unsigned int offset, unsigned int type) -{ - /* cs index check */ - if (index >= LBC_CS_MAX_NUM) - return -EINVAL; - - /* cs offset check */ - if (offset >= g_lbc_dev.cs[index].size) - return -EINVAL; - - if (type != LBC_RWDATA_WIDTH_8 - && type != LBC_RWDATA_WIDTH_16 - && type != LBC_RWDATA_WIDTH_32) - return -EINVAL; - - /* width check */ - if ((type == LBC_RWDATA_WIDTH_16) - || (type == LBC_RWDATA_WIDTH_32)) { - if (offset % (type * 0x2)) - return -EINVAL; - } - - return 0; -} - -static unsigned int lbc_read(unsigned int index, unsigned int offset, unsigned int type) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - unsigned int value; - unsigned long flags; - - spin_lock_irqsave(&g_lbc_dev.cs[index].lock, flags); - - if (type == LBC_RWDATA_WIDTH_8) - value = readb(base_addr + offset) & 0xff; - else if (type == LBC_RWDATA_WIDTH_16) - value = readw(base_addr + offset) & 0xffff; - else - value = readl(base_addr + offset) & 0xffffffff; - - spin_unlock_irqrestore(&g_lbc_dev.cs[index].lock, flags); - - return value; -} - -static unsigned int lbc_read_unlock(unsigned int index, unsigned int offset, unsigned int type) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - unsigned int value; - - if (type == LBC_RWDATA_WIDTH_8) - value = readb(base_addr + offset) & 0xff; - else if (type == LBC_RWDATA_WIDTH_16) - value = readw(base_addr + offset) & 0xffff; - else - value = readl(base_addr + offset) & 0xffffffff; - - return value; -} - -static int lbc_write(unsigned int index, unsigned int offset, unsigned int type, unsigned int data) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - unsigned long flags; - - spin_lock_irqsave(&g_lbc_dev.cs[index].lock, flags); - - if (type == LBC_RWDATA_WIDTH_8) - writeb(data & 0xff, base_addr + offset); - else if (type == LBC_RWDATA_WIDTH_16) - writew(data & 0xffff, base_addr + offset); - else - writel(data & 0xffffffff, base_addr + offset); - - spin_unlock_irqrestore(&g_lbc_dev.cs[index].lock, flags); - - return 0; -} - -static int lbc_write_unlock(unsigned int index, unsigned int offset, unsigned int type, unsigned int data) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - - if (type == LBC_RWDATA_WIDTH_8) - writeb(data & 0xff, base_addr + offset); - else if (type == LBC_RWDATA_WIDTH_16) - writew(data & 0xffff, base_addr + offset); - else - writel(data & 0xffffffff, base_addr + offset); - - return 0; -} - -int lbc_read8(unsigned int index, unsigned int offset, unsigned char *value) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - if (!value) { - pr_err("value is null\n"); - return -EINVAL; - } - - *value = (unsigned char)lbc_read(index, offset, LBC_RWDATA_WIDTH_8); - - return 0; -} -EXPORT_SYMBOL(lbc_read8); - -int lbc_read8_nolock(unsigned int index, unsigned int offset, unsigned char *value) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - if (!value) { - pr_err("value is null\n"); - return -EINVAL; - } - - *value = (unsigned char)lbc_read_unlock(index, offset, LBC_RWDATA_WIDTH_8); - return 0; -} -EXPORT_SYMBOL(lbc_read8_nolock); - -unsigned short lbc_read16(unsigned int index, unsigned int offset) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_16)) { - pr_err("Lbc para check failed\n"); - return 0; - } - - return (unsigned short)lbc_read(index, offset, LBC_RWDATA_WIDTH_16); -} - -unsigned int lbc_read32(unsigned int index, unsigned int offset) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_32)) { - pr_err("Lbc para check failed\n"); - return 0; - } - - return lbc_read(index, offset, LBC_RWDATA_WIDTH_32); -} - -int lbc_write8(unsigned int index, unsigned int offset, unsigned char data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write(index, offset, LBC_RWDATA_WIDTH_8, (unsigned int)data); -} -EXPORT_SYMBOL(lbc_write8); - -int lbc_write8_nolock(unsigned int index, unsigned int offset, unsigned char data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write_unlock(index, offset, LBC_RWDATA_WIDTH_8, (unsigned int)data); -} -EXPORT_SYMBOL(lbc_write8_nolock); - -int lbc_write16(unsigned int index, unsigned int offset, unsigned short data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_16)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write(index, offset, LBC_RWDATA_WIDTH_16, (unsigned int)data); -} - -int lbc_write32(unsigned int index, unsigned int offset, unsigned int data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_32)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write(index, offset, LBC_RWDATA_WIDTH_32, (unsigned int)data); -} - -static int hisi_lbc_cs_init(struct platform_device *pdev) -{ - unsigned int index; - unsigned int width; - unsigned int shift; - struct resource *cs_base = NULL; - - if (has_acpi_companion(g_lbc_dev.dev)) { - /* get cs index */ - index = 0; - (void)device_property_read_u32(g_lbc_dev.dev, "index", &index); - - if (index >= LBC_CS_MAX_NUM) { - dev_err(g_lbc_dev.dev, "Cs index error\n"); - return -EINVAL; - } - - /* lock init */ - spin_lock_init(&g_lbc_dev.cs[index].lock); - - /* get cs base address */ - cs_base = platform_get_resource(pdev, IORESOURCE_MEM, 1); - - if (!cs_base) { - dev_err(g_lbc_dev.dev, "Can not find this cs base resource\n"); - return -ENOENT; - } - - g_lbc_dev.cs[index].cs_base = devm_ioremap_resource(&pdev->dev, cs_base); - - if (IS_ERR(g_lbc_dev.cs[index].cs_base)) - return (int)PTR_ERR(g_lbc_dev.cs[index].cs_base); - - g_lbc_dev.cs[index].size = (unsigned int)resource_size(cs_base); - - lbc_set_cs_base_addr(index, (unsigned int)cs_base->start); - lbc_set_cs_mem_size(index, resource_size(cs_base)); - - /* get cs width */ - width = 0; - (void)device_property_read_u32(g_lbc_dev.dev, "width", &width); - - if (width > LBC_CS_WIDTH_32) { - dev_err(g_lbc_dev.dev, "Cs width error\n"); - return -EINVAL; - } - - g_lbc_dev.cs[index].width = width; - lbc_set_cs_data_width(index, width); - - /* get cs address offset */ - shift = 0; - (void)device_property_read_u32(g_lbc_dev.dev, "shift", &shift); - - if (shift > LBC_CS_ADDR_SHIFT_2) { - dev_err(g_lbc_dev.dev, "Cs address shift error\n"); - return -EINVAL; - } - - g_lbc_dev.cs[index].shift = shift; - - lbc_set_cs_data_offset(index, shift); - } - - return 0; -} - -static int hisi_lbc_probe(struct platform_device *pdev) -{ - int ret; - struct resource *regs_base = NULL; - - dev_info(&pdev->dev, "hisi lbc probe\n"); - - if ((!pdev->dev.of_node) && (!ACPI_COMPANION(&pdev->dev))) { - dev_err(&pdev->dev, "Device OF-Node and ACPI-Node is NULL\n"); - return -EFAULT; - } - - g_lbc_dev.dev = &pdev->dev; - - /* get resource num */ - regs_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (!g_lbc_dev.is_reg_remaped) { - g_lbc_dev.regs_base = devm_ioremap_resource(&pdev->dev, regs_base); - g_lbc_dev.is_reg_remaped = 1; - } - - if (IS_ERR(g_lbc_dev.regs_base)) { - dev_err(&pdev->dev, "ERROR: regbase\n"); - return (int)PTR_ERR(g_lbc_dev.regs_base); - } - - /* localbus cs init */ - ret = hisi_lbc_cs_init(pdev); - if (ret) { - dev_err(&pdev->dev, "Localbus cs init failed\n"); - return -1; - } - - platform_set_drvdata(pdev, &g_lbc_dev); - dev_info(&pdev->dev, "hisi lbc probe prob ok\n"); - return 0; -} - -static int hisi_lbc_remove(struct platform_device *pdev) -{ - return 0; -} - -static const struct of_device_id g_hisi_lbc_pltfm_match[] = { - { - .compatible = "hisilicon, hi1620_lbc", - }, - {}, -}; - -#ifdef CONFIG_ACPI -static const struct acpi_device_id g_hisi_lbc_acpi_match[] = { - { "HISI0C01", 0 }, - { } -}; -MODULE_DEVICE_TABLE(acpi, g_hisi_lbc_acpi_match); -#endif - -static struct platform_driver g_hisi_lbc_driver = { - .probe = hisi_lbc_probe, - .remove = hisi_lbc_remove, - .driver = { - .name = "hisi-lbc", - .owner = THIS_MODULE, - .of_match_table = g_hisi_lbc_pltfm_match, -#ifdef CONFIG_ACPI - .acpi_match_table = ACPI_PTR(g_hisi_lbc_acpi_match), -#endif - }, - -}; - -static int __init hisi_lbc_init_driver(void) -{ - return platform_driver_register((struct platform_driver *)&g_hisi_lbc_driver); -} - -static void __exit hisi_lbc_exit_driver(void) -{ - platform_driver_unregister((struct platform_driver *)&g_hisi_lbc_driver); -} - -module_init(hisi_lbc_init_driver); -module_exit(hisi_lbc_exit_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Huawei Tech. Co., Ltd."); -MODULE_VERSION(LBC_DRIVER_VERSION); -MODULE_DESCRIPTION("LBC driver for linux"); diff --git a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h b/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h deleted file mode 100644 index 24ca4366ec512..0000000000000 --- a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _HS_LBC_PLTFM_H_ -#define _HS_LBC_PLTFM_H_ -#include <linux/version.h> - -/* RW data width */ -#define LBC_RWDATA_WIDTH_8 (0) -#define LBC_RWDATA_WIDTH_16 (1) -#define LBC_RWDATA_WIDTH_32 (2) - -/* cs width */ -#define LBC_CS_WIDTH_8 (0) -#define LBC_CS_WIDTH_16 (1) -#define LBC_CS_WIDTH_32 (2) - -/* cs address shift */ -#define LBC_CS_ADDR_SHIFT_0 (0) -#define LBC_CS_ADDR_SHIFT_1 (1) -#define LBC_CS_ADDR_SHIFT_2 (2) - -#define LBC_CS_MAX_NUM (4) - -#define LBC_CS_MEM_SIZE_0 (0) -#define LBC_CS_MEM_SIZE_64K (64 * 1024) -#define LBC_CS_MEM_SIZE_128K (LBC_CS_MEM_SIZE_64K << 1) -#define LBC_CS_MEM_SIZE_256K (LBC_CS_MEM_SIZE_128K << 1) -#define LBC_CS_MEM_SIZE_512K (LBC_CS_MEM_SIZE_256K << 1) -#define LBC_CS_MEM_SIZE_1M (LBC_CS_MEM_SIZE_512K << 1) -#define LBC_CS_MEM_SIZE_2M (LBC_CS_MEM_SIZE_1M << 1) -#define LBC_CS_MEM_SIZE_4M (LBC_CS_MEM_SIZE_2M << 1) -#define LBC_CS_MEM_SIZE_8M (LBC_CS_MEM_SIZE_4M << 1) -#define LBC_CS_MEM_SIZE_16M (LBC_CS_MEM_SIZE_8M << 1) -#define LBC_CS_MEM_SIZE_32M (LBC_CS_MEM_SIZE_16M << 1) -#define LBC_CS_MEM_SIZE_64M (LBC_CS_MEM_SIZE_32M << 1) -#define LBC_CS_MEM_SIZE_128M (LBC_CS_MEM_SIZE_64M << 1) -#define LBC_CS_MEM_SIZE_256M (LBC_CS_MEM_SIZE_128M << 1) - -#define LBC_CS_MEM_SIZE_REG_0 (0) -#define LBC_CS_MEM_SIZE_REG_64K (1) -#define LBC_CS_MEM_SIZE_REG_128K (2) -#define LBC_CS_MEM_SIZE_REG_256K (3) -#define LBC_CS_MEM_SIZE_REG_512K (4) -#define LBC_CS_MEM_SIZE_REG_1M (5) -#define LBC_CS_MEM_SIZE_REG_2M (6) -#define LBC_CS_MEM_SIZE_REG_4M (7) -#define LBC_CS_MEM_SIZE_REG_8M (8) -#define LBC_CS_MEM_SIZE_REG_16M (9) -#define LBC_CS_MEM_SIZE_REG_32M (10) -#define LBC_CS_MEM_SIZE_REG_64M (11) -#define LBC_CS_MEM_SIZE_REG_128M (12) -#define LBC_CS_MEM_SIZE_REG_256M (13) -#define LBC_CS_MEM_SIZE_REG_512M (14) -#define LBC_CS_MEM_SIZE_REG_1G (15) -#define LBC_CS_MEM_SIZE_REG_2G (16) -#define LBC_CS_MEM_SIZE_REG_4G (17) - -typedef struct lbc_cs_ctrl { - volatile unsigned int mem_size : 5; - volatile unsigned int data_width : 2; - volatile unsigned int data_order : 1; - volatile unsigned int byte_order : 1; - volatile unsigned int rdy_mode : 1; - volatile unsigned int rdy_pol : 1; - volatile unsigned int addr_offset : 1; - volatile unsigned int lbctl_en : 1; - volatile unsigned int page_en : 1; - volatile unsigned int page_size : 2; - volatile unsigned int rdy_tout_en : 1; - volatile unsigned int rble : 1; - volatile unsigned int reserved : 14; -} LBC_CS_CTRL; - -#define LBC_REG_RSV_MAX_NUM 4 -#define LBC_REG_CRE_MAX_NUM 4 -typedef struct lbc_reg_region { - volatile unsigned int cs_base[LBC_CS_MAX_NUM]; - volatile unsigned int cs_base_reserved[LBC_REG_RSV_MAX_NUM]; - volatile LBC_CS_CTRL cs_ctrl[LBC_CS_MAX_NUM]; - volatile LBC_CS_CTRL cs_ctrl_creserved[LBC_REG_CRE_MAX_NUM]; -} LBC_REG_REGION; - -struct hisi_lbc_cs { - unsigned int index; - spinlock_t lock; - void __iomem *cs_base; - unsigned int size; - unsigned int width; /* width */ - unsigned int shift; /* address shift */ -}; - -struct hisi_lbc_dev { - unsigned char is_reg_remaped; - struct device *dev; - void __iomem *regs_base; /* localbus regs base addr */ - struct hisi_lbc_cs cs[LBC_CS_MAX_NUM]; -}; - -#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 16, 0) -#define __ACCESS_ONCE(x) ({ \ - __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \ - (volatile typeof(x) *)&(x); }) -#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x)) -#endif - -#endif -- 2.25.1

1 2

[PATCH openEuler-1.0-LTS] atlantic: Fix OOB read and write in hw_atl_utils_fw_rpc_wait
by Yang Yingliang 22 Nov '21

22 Nov '21

From: Zekun Shen <bruceshenzk(a)gmail.com> mainline inclusion from mainline-v5.16-rc2 commit b922f622592af76b57cbc566eaeccda0b31a3496 category: bugfix bugzilla: NA CVE: CVE-2021-43975 ------------------------------------------------- This bug report shows up when running our research tools. The reports is SOOB read, but it seems SOOB write is also possible a few lines below. In details, fw.len and sw.len are inputs coming from io. A len over the size of self->rpc triggers SOOB. The patch fixes the bugs by adding sanity checks. The bugs are triggerable with compromised/malfunctioning devices. They are potentially exploitable given they first leak up to 0xffff bytes and able to overwrite the region later. The patch is tested with QEMU emulater. This is NOT tested with a real device. Attached is the log we found by fuzzing. BUG: KASAN: slab-out-of-bounds in hw_atl_utils_fw_upload_dwords+0x393/0x3c0 [atlantic] Read of size 4 at addr ffff888016260b08 by task modprobe/213 CPU: 0 PID: 213 Comm: modprobe Not tainted 5.6.0 #1 Call Trace: dump_stack+0x76/0xa0 print_address_description.constprop.0+0x16/0x200 ? hw_atl_utils_fw_upload_dwords+0x393/0x3c0 [atlantic] ? hw_atl_utils_fw_upload_dwords+0x393/0x3c0 [atlantic] __kasan_report.cold+0x37/0x7c ? aq_hw_read_reg_bit+0x60/0x70 [atlantic] ? hw_atl_utils_fw_upload_dwords+0x393/0x3c0 [atlantic] kasan_report+0xe/0x20 hw_atl_utils_fw_upload_dwords+0x393/0x3c0 [atlantic] hw_atl_utils_fw_rpc_call+0x95/0x130 [atlantic] hw_atl_utils_fw_rpc_wait+0x176/0x210 [atlantic] hw_atl_utils_mpi_create+0x229/0x2e0 [atlantic] ? hw_atl_utils_fw_rpc_wait+0x210/0x210 [atlantic] ? hw_atl_utils_initfw+0x9f/0x1c8 [atlantic] hw_atl_utils_initfw+0x12a/0x1c8 [atlantic] aq_nic_ndev_register+0x88/0x650 [atlantic] ? aq_nic_ndev_init+0x235/0x3c0 [atlantic] aq_pci_probe+0x731/0x9b0 [atlantic] ? aq_pci_func_init+0xc0/0xc0 [atlantic] local_pci_probe+0xd3/0x160 pci_device_probe+0x23f/0x3e0 Reported-by: Brendan Dolan-Gavitt <brendandg(a)nyu.edu> Signed-off-by: Zekun Shen <bruceshenzk(a)gmail.com> Signed-off-by: David S. Miller <davem(a)davemloft.net> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> Reviewed-by: Xiu Jianfeng <xiujianfeng(a)huawei.com> Reviewed-by: Wei Yongjun <weiyongjun1(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- .../ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c index 096ec18e8f15a..49c80bac9ce28 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c @@ -459,6 +459,11 @@ int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, goto err_exit; if (fw.len == 0xFFFFU) { + if (sw.len > sizeof(self->rpc)) { + printk(KERN_INFO "Invalid sw len: %x\n", sw.len); + err = -EINVAL; + goto err_exit; + } err = hw_atl_utils_fw_rpc_call(self, sw.len); if (err < 0) goto err_exit; @@ -469,6 +474,11 @@ int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, if (rpc) { if (fw.len) { + if (fw.len > sizeof(self->rpc)) { + printk(KERN_INFO "Invalid fw len: %x\n", fw.len); + err = -EINVAL; + goto err_exit; + } err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr, -- 2.25.1

1 0

[PATCH OLK-5.10 0/4] Introduce x86 assembler accelerated implementation for SM4 algorithm
by shenzijun 22 Nov '21

22 Nov '21

From: 沈子俊 <shenzijun(a)kylinos.cn> This patchset extracts the public SM4 algorithm as a separate library, At the same time, the acceleration implementation of SM4 in arm64 was adjusted to adapt to this SM4 library. Then introduces an accelerated implementation of the instruction set on x86_64. This optimization supports the four modes of SM4, ECB, CBC, CFB, and CTR. Since CBC and CFB do not support multiple block parallel encryption, the optimization effect is not obvious. And all selftests have passed already. The main algorithm implementation comes from SM4 AES-NI work by libgcrypt and Markku-Juhani O. Saarinen at: https://github.com/mjosaarinen/sm4ni Benchmark on Intel Xeon Cascadelake, the data comes from the mode 218 and mode 518 of tcrypt. The abscissas are blocks of different lengths. The data is tabulated and the unit is Mb/s: sm4-generic | 16 64 128 256 1024 1420 4096 ECB enc | 40.99 46.50 48.05 48.41 49.20 49.25 49.28 ECB dec | 41.07 46.99 48.15 48.67 49.20 49.25 49.29 CBC enc | 37.71 45.28 46.77 47.60 48.32 48.37 48.40 CBC dec | 36.48 44.82 46.43 47.45 48.23 48.30 48.36 CFB enc | 37.94 44.84 46.12 46.94 47.57 47.46 47.68 CFB dec | 37.50 42.84 43.74 44.37 44.85 44.80 44.96 CTR enc | 39.20 45.63 46.75 47.49 48.09 47.85 48.08 CTR dec | 39.64 45.70 46.72 47.47 47.98 47.88 48.06 sm4-aesni-avx ECB enc | 33.75 134.47 221.64 243.43 264.05 251.58 258.13 ECB dec | 34.02 134.92 223.11 245.14 264.12 251.04 258.33 CBC enc | 38.85 46.18 47.67 48.34 49.00 48.96 49.14 CBC dec | 33.54 131.29 223.88 245.27 265.50 252.41 263.78 CFB enc | 38.70 46.10 47.58 48.29 49.01 48.94 49.19 CFB dec | 32.79 128.40 223.23 244.87 265.77 253.31 262.79 CTR enc | 32.58 122.23 220.29 241.16 259.57 248.32 256.69 CTR dec | 32.81 122.47 218.99 241.54 258.42 248.58 256.61 --- v3 changes: * Remove single block algorithm that does not greatly improve performance * Remove accelerated for sm4 key expand, which is not performance-critical * Fix the warning on arm64/sm4-ce v2 changes: * SM4 library functions use "sm4_" prefix instead of "crypto_" prefix * sm4-aesni-avx supports accelerated implementation of four specific modes * tcrypt benchmark supports sm4-aesni-avx * fixes of other reviews 沈子俊 (4): crypto: sm4 - create SM4 library based on sm4 generic code crypto: arm64/sm4-ce - Make dependent on sm4 library instead of sm4-generic crypto: x86/sm4 - add AES-NI/AVX/x86_64 implementation crypto: tcrypt - add the asynchronous speed test for SM4 arch/arm64/crypto/Kconfig | 2 +- arch/arm64/crypto/sm4-ce-glue.c | 20 +- arch/x86/crypto/Makefile | 3 + arch/x86/crypto/sm4-aesni-avx-asm_64.S | 589 +++++++++++++++++++++++++ arch/x86/crypto/sm4_aesni_avx_glue.c | 459 +++++++++++++++++++ crypto/Kconfig | 22 + crypto/sm4_generic.c | 180 +------- crypto/tcrypt.c | 26 +- include/crypto/sm4.h | 25 +- lib/crypto/Kconfig | 3 + lib/crypto/Makefile | 3 + lib/crypto/sm4.c | 176 ++++++++ 12 files changed, 1330 insertions(+), 178 deletions(-) create mode 100644 arch/x86/crypto/sm4-aesni-avx-asm_64.S create mode 100644 arch/x86/crypto/sm4_aesni_avx_glue.c create mode 100644 lib/crypto/sm4.c -- 2.30.0

1 4

[PATCH openEuler-5.10 01/88] topology: Represent clusters of CPUs within a die
by Zheng Zengkai 18 Nov '21

18 Nov '21

From: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> mainline inclusion from tip/sched/core for v5.15-release commit: c5e22feffdd736cb02b98b0f5b375c8ebc858dd4 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4GEZS CVE: NA Reference: https://lore.kernel.org/lkml/20210924085104.44806-1-21cnbao@gmail.com/ ------------------------------------------------------------------------ Both ACPI and DT provide the ability to describe additional layers of topology between that of individual cores and higher level constructs such as the level at which the last level cache is shared. In ACPI this can be represented in PPTT as a Processor Hierarchy Node Structure [1] that is the parent of the CPU cores and in turn has a parent Processor Hierarchy Nodes Structure representing a higher level of topology. For example Kunpeng 920 has 6 or 8 clusters in each NUMA node, and each cluster has 4 cpus. All clusters share L3 cache data, but each cluster has local L3 tag. On the other hand, each clusters will share some internal system bus. +-----------------------------------+ +---------+ | +------+ +------+ +--------------------------+ | | | CPU0 | | cpu1 | | +-----------+ | | | +------+ +------+ | | | | | | +----+ L3 | | | | +------+ +------+ cluster | | tag | | | | | CPU2 | | CPU3 | | | | | | | +------+ +------+ | +-----------+ | | | | | | +-----------------------------------+ | | +-----------------------------------+ | | | +------+ +------+ +--------------------------+ | | | | | | | +-----------+ | | | +------+ +------+ | | | | | | | | L3 | | | | +------+ +------+ +----+ tag | | | | | | | | | | | | | | +------+ +------+ | +-----------+ | | | | | | +-----------------------------------+ | L3 | | data | +-----------------------------------+ | | | +------+ +------+ | +-----------+ | | | | | | | | | | | | | +------+ +------+ +----+ L3 | | | | | | tag | | | | +------+ +------+ | | | | | | | | | | | +-----------+ | | | +------+ +------+ +--------------------------+ | +-----------------------------------| | | +-----------------------------------| | | | +------+ +------+ +--------------------------+ | | | | | | | +-----------+ | | | +------+ +------+ | | | | | | +----+ L3 | | | | +------+ +------+ | | tag | | | | | | | | | | | | | | +------+ +------+ | +-----------+ | | | | | | +-----------------------------------+ | | +-----------------------------------+ | | | +------+ +------+ +--------------------------+ | | | | | | | +-----------+ | | | +------+ +------+ | | | | | | | | L3 | | | | +------+ +------+ +---+ tag | | | | | | | | | | | | | | +------+ +------+ | +-----------+ | | | | | | +-----------------------------------+ | | +-----------------------------------+ | | | +------+ +------+ +--------------------------+ | | | | | | | +-----------+ | | | +------+ +------+ | | | | | | | | L3 | | | | +------+ +------+ +--+ tag | | | | | | | | | | | | | | +------+ +------+ | +-----------+ | | | | +---------+ +-----------------------------------+ That means spreading tasks among clusters will bring more bandwidth while packing tasks within one cluster will lead to smaller cache synchronization latency. So both kernel and userspace will have a chance to leverage this topology to deploy tasks accordingly to achieve either smaller cache latency within one cluster or an even distribution of load among clusters for higher throughput. This patch exposes cluster topology to both kernel and userspace. Libraried like hwloc will know cluster by cluster_cpus and related sysfs attributes. PoC of HWLOC support at [2]. Note this patch only handle the ACPI case. Special consideration is needed for SMT processors, where it is necessary to move 2 levels up the hierarchy from the leaf nodes (thus skipping the processor core level). Note that arm64 / ACPI does not provide any means of identifying a die level in the topology but that may be unrelate to the cluster level. [1] ACPI Specification 6.3 - section 5.2.29.1 processor hierarchy node structure (Type 0) [2] https://github.com/hisilicon/hwloc/tree/linux-cluster Signed-off-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> Signed-off-by: Peter Zijlstra (Intel) <peterz(a)infradead.org> Link: https://lore.kernel.org/r/20210924085104.44806-2-21cnbao@gmail.com Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> Reviewed-by: tao zeng <prime.zeng(a)hisilicon.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- Documentation/admin-guide/cputopology.rst | 26 +++++++-- arch/arm64/kernel/topology.c | 2 + drivers/acpi/pptt.c | 67 +++++++++++++++++++++++ drivers/base/arch_topology.c | 15 +++++ drivers/base/topology.c | 10 ++++ include/linux/acpi.h | 5 ++ include/linux/arch_topology.h | 5 ++ include/linux/topology.h | 6 ++ 8 files changed, 132 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/cputopology.rst b/Documentation/admin-guide/cputopology.rst index b90dafcc8237..57be98ae27b8 100644 --- a/Documentation/admin-guide/cputopology.rst +++ b/Documentation/admin-guide/cputopology.rst @@ -18,6 +18,11 @@ die_id: identifier (rather than the kernel's). The actual value is architecture and platform dependent. +cluster_id: + the cluster ID of cpuX. Typically it is the hardware platform's + identifier (rather than the kernel's). The actual value is + architecture and platform dependent. + core_id: the CPU core ID of cpuX. Typically it is the hardware platform's @@ -64,6 +69,15 @@ die_cpus_list: human-readable list of CPUs within the same die. +cluster_cpus: + + internal kernel map of CPUs within the same cluster + +cluster_cpus_list: + + human-readable list of CPUs within the same cluster. + The format is like 0-3, 8-11, 14,17. + book_siblings: internal kernel map of cpuX's hardware threads within the same @@ -96,11 +110,13 @@ these macros in include/asm-XXX/topology.h:: #define topology_physical_package_id(cpu) #define topology_die_id(cpu) + #define topology_cluster_id(cpu) #define topology_core_id(cpu) #define topology_book_id(cpu) #define topology_drawer_id(cpu) #define topology_sibling_cpumask(cpu) #define topology_core_cpumask(cpu) + #define topology_cluster_cpumask(cpu) #define topology_die_cpumask(cpu) #define topology_book_cpumask(cpu) #define topology_drawer_cpumask(cpu) @@ -116,10 +132,12 @@ not defined by include/asm-XXX/topology.h: 1) topology_physical_package_id: -1 2) topology_die_id: -1 -3) topology_core_id: 0 -4) topology_sibling_cpumask: just the given CPU -5) topology_core_cpumask: just the given CPU -6) topology_die_cpumask: just the given CPU +3) topology_cluster_id: -1 +4) topology_core_id: 0 +5) topology_sibling_cpumask: just the given CPU +6) topology_core_cpumask: just the given CPU +7) topology_cluster_cpumask: just the given CPU +8) topology_die_cpumask: just the given CPU For architectures that don't support books (CONFIG_SCHED_BOOK) there are no default definitions for topology_book_id() and topology_book_cpumask(). diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 19cedf882a6b..a80fcb6dd88a 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -114,6 +114,8 @@ int __init parse_acpi_topology(void) cpu_topology[cpu].thread_id = -1; cpu_topology[cpu].core_id = topology_id; } + topology_id = find_acpi_cpu_topology_cluster(cpu); + cpu_topology[cpu].cluster_id = topology_id; topology_id = find_acpi_cpu_topology_package(cpu); cpu_topology[cpu].package_id = topology_id; diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index 20bd584f2516..3d9403ded527 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -849,6 +849,73 @@ int find_acpi_cpu_topology_package(unsigned int cpu) ACPI_PPTT_PHYSICAL_PACKAGE); } +/** + * find_acpi_cpu_topology_cluster() - Determine a unique CPU cluster value + * @cpu: Kernel logical CPU number + * + * Determine a topology unique cluster ID for the given CPU/thread. + * This ID can then be used to group peers, which will have matching ids. + * + * The cluster, if present is the level of topology above CPUs. In a + * multi-thread CPU, it will be the level above the CPU, not the thread. + * It may not exist in single CPU systems. In simple multi-CPU systems, + * it may be equal to the package topology level. + * + * Return: -ENOENT if the PPTT doesn't exist, the CPU cannot be found + * or there is no toplogy level above the CPU.. + * Otherwise returns a value which represents the package for this CPU. + */ + +int find_acpi_cpu_topology_cluster(unsigned int cpu) +{ + struct acpi_table_header *table; + acpi_status status; + struct acpi_pptt_processor *cpu_node, *cluster_node; + u32 acpi_cpu_id; + int retval; + int is_thread; + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + acpi_pptt_warn_missing(); + return -ENOENT; + } + + acpi_cpu_id = get_acpi_id_for_cpu(cpu); + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); + if (cpu_node == NULL || !cpu_node->parent) { + retval = -ENOENT; + goto put_table; + } + + is_thread = cpu_node->flags & ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD; + cluster_node = fetch_pptt_node(table, cpu_node->parent); + if (cluster_node == NULL) { + retval = -ENOENT; + goto put_table; + } + if (is_thread) { + if (!cluster_node->parent) { + retval = -ENOENT; + goto put_table; + } + cluster_node = fetch_pptt_node(table, cluster_node->parent); + if (cluster_node == NULL) { + retval = -ENOENT; + goto put_table; + } + } + if (cluster_node->flags & ACPI_PPTT_ACPI_PROCESSOR_ID_VALID) + retval = cluster_node->acpi_processor_id; + else + retval = ACPI_PTR_DIFF(cluster_node, table); + +put_table: + acpi_put_table(table); + + return retval; +} + /** * find_acpi_cpu_topology_hetero_id() - Get a core architecture tag * @cpu: Kernel logical CPU number diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index de8587cc119e..21e63b6fab83 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -506,6 +506,11 @@ const struct cpumask *cpu_coregroup_mask(int cpu) return core_mask; } +const struct cpumask *cpu_clustergroup_mask(int cpu) +{ + return &cpu_topology[cpu].cluster_sibling; +} + void update_siblings_masks(unsigned int cpuid) { struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; @@ -523,6 +528,12 @@ void update_siblings_masks(unsigned int cpuid) if (cpuid_topo->package_id != cpu_topo->package_id) continue; + if (cpuid_topo->cluster_id == cpu_topo->cluster_id && + cpuid_topo->cluster_id != -1) { + cpumask_set_cpu(cpu, &cpuid_topo->cluster_sibling); + cpumask_set_cpu(cpuid, &cpu_topo->cluster_sibling); + } + cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); cpumask_set_cpu(cpu, &cpuid_topo->core_sibling); @@ -541,6 +552,9 @@ static void clear_cpu_topology(int cpu) cpumask_clear(&cpu_topo->llc_sibling); cpumask_set_cpu(cpu, &cpu_topo->llc_sibling); + cpumask_clear(&cpu_topo->cluster_sibling); + cpumask_set_cpu(cpu, &cpu_topo->cluster_sibling); + cpumask_clear(&cpu_topo->core_sibling); cpumask_set_cpu(cpu, &cpu_topo->core_sibling); cpumask_clear(&cpu_topo->thread_sibling); @@ -556,6 +570,7 @@ void __init reset_cpu_topology(void) cpu_topo->thread_id = -1; cpu_topo->core_id = -1; + cpu_topo->cluster_id = -1; cpu_topo->package_id = -1; cpu_topo->llc_id = -1; diff --git a/drivers/base/topology.c b/drivers/base/topology.c index 4d254fcc93d1..7157ac08ff57 100644 --- a/drivers/base/topology.c +++ b/drivers/base/topology.c @@ -46,6 +46,9 @@ static DEVICE_ATTR_RO(physical_package_id); define_id_show_func(die_id); static DEVICE_ATTR_RO(die_id); +define_id_show_func(cluster_id); +static DEVICE_ATTR_RO(cluster_id); + define_id_show_func(core_id); static DEVICE_ATTR_RO(core_id); @@ -61,6 +64,10 @@ define_siblings_show_func(core_siblings, core_cpumask); static DEVICE_ATTR_RO(core_siblings); static DEVICE_ATTR_RO(core_siblings_list); +define_siblings_show_func(cluster_cpus, cluster_cpumask); +static DEVICE_ATTR_RO(cluster_cpus); +static DEVICE_ATTR_RO(cluster_cpus_list); + define_siblings_show_func(die_cpus, die_cpumask); static DEVICE_ATTR_RO(die_cpus); static DEVICE_ATTR_RO(die_cpus_list); @@ -88,6 +95,7 @@ static DEVICE_ATTR_RO(drawer_siblings_list); static struct attribute *default_attrs[] = { &dev_attr_physical_package_id.attr, &dev_attr_die_id.attr, + &dev_attr_cluster_id.attr, &dev_attr_core_id.attr, &dev_attr_thread_siblings.attr, &dev_attr_thread_siblings_list.attr, @@ -95,6 +103,8 @@ static struct attribute *default_attrs[] = { &dev_attr_core_cpus_list.attr, &dev_attr_core_siblings.attr, &dev_attr_core_siblings_list.attr, + &dev_attr_cluster_cpus.attr, + &dev_attr_cluster_cpus_list.attr, &dev_attr_die_cpus.attr, &dev_attr_die_cpus_list.attr, &dev_attr_package_cpus.attr, diff --git a/include/linux/acpi.h b/include/linux/acpi.h index a3db177329c2..9045dfb6d19c 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1350,6 +1350,7 @@ static inline int lpit_read_residency_count_address(u64 *address) int acpi_pptt_init(void); int acpi_pptt_cpu_is_thread(unsigned int cpu); int find_acpi_cpu_topology(unsigned int cpu, int level); +int find_acpi_cpu_topology_cluster(unsigned int cpu); int find_acpi_cpu_topology_package(unsigned int cpu); int find_acpi_cpu_topology_hetero_id(unsigned int cpu); int find_acpi_cpu_cache_topology(unsigned int cpu, int level); @@ -1362,6 +1363,10 @@ static inline int find_acpi_cpu_topology(unsigned int cpu, int level) { return -EINVAL; } +static inline int find_acpi_cpu_topology_cluster(unsigned int cpu) +{ + return -EINVAL; +} static inline int find_acpi_cpu_topology_package(unsigned int cpu) { return -EINVAL; diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h index 0f6cd6b73a61..987c7ea75291 100644 --- a/include/linux/arch_topology.h +++ b/include/linux/arch_topology.h @@ -49,10 +49,12 @@ void topology_set_thermal_pressure(const struct cpumask *cpus, struct cpu_topology { int thread_id; int core_id; + int cluster_id; int package_id; int llc_id; cpumask_t thread_sibling; cpumask_t core_sibling; + cpumask_t cluster_sibling; cpumask_t llc_sibling; }; @@ -60,13 +62,16 @@ struct cpu_topology { extern struct cpu_topology cpu_topology[NR_CPUS]; #define topology_physical_package_id(cpu) (cpu_topology[cpu].package_id) +#define topology_cluster_id(cpu) (cpu_topology[cpu].cluster_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) +#define topology_cluster_cpumask(cpu) (&cpu_topology[cpu].cluster_sibling) #define topology_llc_cpumask(cpu) (&cpu_topology[cpu].llc_sibling) void init_cpu_topology(void); void store_cpu_topology(unsigned int cpuid); const struct cpumask *cpu_coregroup_mask(int cpu); +const struct cpumask *cpu_clustergroup_mask(int cpu); void update_siblings_masks(unsigned int cpu); void remove_cpu_topology(unsigned int cpuid); void reset_cpu_topology(void); diff --git a/include/linux/topology.h b/include/linux/topology.h index 7634cd737061..80d27d717631 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -186,6 +186,9 @@ static inline int cpu_to_mem(int cpu) #ifndef topology_die_id #define topology_die_id(cpu) ((void)(cpu), -1) #endif +#ifndef topology_cluster_id +#define topology_cluster_id(cpu) ((void)(cpu), -1) +#endif #ifndef topology_core_id #define topology_core_id(cpu) ((void)(cpu), 0) #endif @@ -195,6 +198,9 @@ static inline int cpu_to_mem(int cpu) #ifndef topology_core_cpumask #define topology_core_cpumask(cpu) cpumask_of(cpu) #endif +#ifndef topology_cluster_cpumask +#define topology_cluster_cpumask(cpu) cpumask_of(cpu) +#endif #ifndef topology_die_cpumask #define topology_die_cpumask(cpu) cpumask_of(cpu) #endif -- 2.20.1

1 87

[PATCH openEuler-1.0-LTS 1/2] crypto: public_key: fix overflow during implicit conversion
by Yang Yingliang 18 Nov '21

18 Nov '21

From: zhenwei pi <pizhenwei(a)bytedance.com> stable inclusion from linux-4.19.207 commit aab312696d37de80502ca633b40184de24f22917 -------------------------------- commit f985911b7bc75d5c98ed24d8aaa8b94c590f7c6a upstream. Hit kernel warning like this, it can be reproduced by verifying 256 bytes datafile by keyctl command, run script: RAWDATA=rawdata SIGDATA=sigdata modprobe pkcs8_key_parser rm -rf *.der *.pem *.pfx rm -rf $RAWDATA dd if=/dev/random of=$RAWDATA bs=256 count=1 openssl req -nodes -x509 -newkey rsa:4096 -keyout key.pem -out cert.pem \ -subj "/C=CN/ST=GD/L=SZ/O=vihoo/OU=dev/CN=xx.com/emailAddress=yy(a)xx.com" KEY_ID=`openssl pkcs8 -in key.pem -topk8 -nocrypt -outform DER | keyctl \ padd asymmetric 123 @s` keyctl pkey_sign $KEY_ID 0 $RAWDATA enc=pkcs1 hash=sha1 > $SIGDATA keyctl pkey_verify $KEY_ID 0 $RAWDATA $SIGDATA enc=pkcs1 hash=sha1 Then the kernel reports: WARNING: CPU: 5 PID: 344556 at crypto/rsa-pkcs1pad.c:540 pkcs1pad_verify+0x160/0x190 ... Call Trace: public_key_verify_signature+0x282/0x380 ? software_key_query+0x12d/0x180 ? keyctl_pkey_params_get+0xd6/0x130 asymmetric_key_verify_signature+0x66/0x80 keyctl_pkey_verify+0xa5/0x100 do_syscall_64+0x35/0xb0 entry_SYSCALL_64_after_hwframe+0x44/0xae The reason of this issue, in function 'asymmetric_key_verify_signature': '.digest_size(u8) = params->in_len(u32)' leads overflow of an u8 value, so use u32 instead of u8 for digest_size field. And reorder struct public_key_signature, it saves 8 bytes on a 64-bit machine. Cc: stable(a)vger.kernel.org Signed-off-by: zhenwei pi <pizhenwei(a)bytedance.com> Reviewed-by: Jarkko Sakkinen <jarkko(a)kernel.org> Signed-off-by: Jarkko Sakkinen <jarkko(a)kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- include/crypto/public_key.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/crypto/public_key.h b/include/crypto/public_key.h index e0b681a717bac..052e26fda2e6c 100644 --- a/include/crypto/public_key.h +++ b/include/crypto/public_key.h @@ -35,9 +35,9 @@ extern void public_key_free(struct public_key *key); struct public_key_signature { struct asymmetric_key_id *auth_ids[2]; u8 *s; /* Signature */ - u32 s_size; /* Number of bytes in signature */ u8 *digest; - u8 digest_size; /* Number of bytes in digest */ + u32 s_size; /* Number of bytes in signature */ + u32 digest_size; /* Number of bytes in digest */ const char *pkey_algo; const char *hash_algo; }; -- 2.25.1

1 1

【Meeting Notice】openEuler kernel 技术分享第十四期 & 双周例会 Time: 2021-11-19 14:00-16:30
by Meeting Book 18 Nov '21

18 Nov '21

1 0

[PATCH openEuler-1.0-LTS] net: bridge: fix stale eth hdr pointer in br_dev_xmit
by Yang Yingliang 18 Nov '21

18 Nov '21

From: Nikolay Aleksandrov <nikolay(a)cumulusnetworks.com> mainline inclusion from mainline-v5.6-rc4 commit 823d81b0fa2cd83a640734e74caee338b5d3c093 category: bugfix bugzilla: 185773 CVE: NA ------------------------------------------------- In br_dev_xmit() we perform vlan filtering in br_allowed_ingress() but if the packet has the vlan header inside (e.g. bridge with disabled tx-vlan-offload) then the vlan filtering code will use skb_vlan_untag() to extract the vid before filtering which in turn calls pskb_may_pull() and we may end up with a stale eth pointer. Moreover the cached eth header pointer will generally be wrong after that operation. Remove the eth header caching and just use eth_hdr() directly, the compiler does the right thing and calculates it only once so we don't lose anything. Fixes: 057658cb33fb ("bridge: suppress arp pkts on BR_NEIGH_SUPPRESS ports") Signed-off-by: Nikolay Aleksandrov <nikolay(a)cumulusnetworks.com> Signed-off-by: David S. Miller <davem(a)davemloft.net> Signed-off-by: Huang Guobin <huangguobin4(a)huawei.com> Reviewed-by: Wei Yongjun <weiyongjun1(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- net/bridge/br_device.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/net/bridge/br_device.c b/net/bridge/br_device.c index a350c05b7ff5e..7b7784bb1cb99 100644 --- a/net/bridge/br_device.c +++ b/net/bridge/br_device.c @@ -39,7 +39,6 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) struct pcpu_sw_netstats *brstats = this_cpu_ptr(br->stats); const struct nf_br_ops *nf_ops; const unsigned char *dest; - struct ethhdr *eth; u16 vid = 0; rcu_read_lock(); @@ -58,15 +57,14 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) BR_INPUT_SKB_CB(skb)->brdev = dev; skb_reset_mac_header(skb); - eth = eth_hdr(skb); skb_pull(skb, ETH_HLEN); if (!br_allowed_ingress(br, br_vlan_group_rcu(br), skb, &vid)) goto out; if (IS_ENABLED(CONFIG_INET) && - (eth->h_proto == htons(ETH_P_ARP) || - eth->h_proto == htons(ETH_P_RARP)) && + (eth_hdr(skb)->h_proto == htons(ETH_P_ARP) || + eth_hdr(skb)->h_proto == htons(ETH_P_RARP)) && br->neigh_suppress_enabled) { br_do_proxy_suppress_arp(skb, br, vid, NULL); } else if (IS_ENABLED(CONFIG_IPV6) && -- 2.25.1

1 0

[PATCH openEuler-1.0-LTS] x86/entry: Make entry_64_compat.S objtool clean
by Yang Yingliang 17 Nov '21

17 Nov '21

From: Peter Zijlstra <peterz(a)infradead.org> mainline inclusion from mainline-v5.8-rc1 commit 1c3e5d3f60e26415d4227aa1193cf9e2db4df834 category: feature bugzilla: 175666 CVE: NA --------------------------- Currently entry_64_compat is exempt from objtool, but with vmlinux mode there is no hiding it. Make the following changes to make it pass: - change entry_SYSENTER_compat to STT_NOTYPE; it's not a function and doesn't have function type stack setup. - mark all STT_NOTYPE symbols with UNWIND_HINT_EMPTY; so we do validate them and don't treat them as unreachable. - don't abuse RSP as a temp register, this confuses objtool mightily as it (rightfully) thinks we're doing unspeakable things to the stack. Signed-off-by: Peter Zijlstra (Intel) <peterz(a)infradead.org> Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de> Reviewed-by: Alexandre Chartre <alexandre.chartre(a)oracle.com> Acked-by: Andy Lutomirski <luto(a)kernel.org> Link: https://lkml.kernel.org/r/20200505134341.272248024@linutronix.de Signed-off-by: Wang ShaoBo <bobo.shaobowang(a)huawei.com> Conflicts: arch/x86/entry/entry_64_compat.S [wangshaobo: change ENDPROC to END, avoid objtool skipping STT_FUNC type check] Reviewed-by: Cheng Jian <cj.chengjian(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- arch/x86/entry/Makefile | 2 -- arch/x86/entry/entry_64_compat.S | 17 +++++++++++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/entry/Makefile b/arch/x86/entry/Makefile index 06fc70cf5433d..e71890149ce0e 100644 --- a/arch/x86/entry/Makefile +++ b/arch/x86/entry/Makefile @@ -3,8 +3,6 @@ # Makefile for the x86 low level entry code # -OBJECT_FILES_NON_STANDARD_entry_64_compat.o := y - CFLAGS_syscall_64.o += $(call cc-option,-Wno-override-init,) CFLAGS_syscall_32.o += $(call cc-option,-Wno-override-init,) obj-y := entry_$(BITS).o thunk_$(BITS).o syscall_$(BITS).o diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index 40d2834a8101e..f326e0c6e8dd8 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -47,11 +47,14 @@ * 0(%ebp) arg6 */ ENTRY(entry_SYSENTER_compat) + UNWIND_HINT_EMPTY /* Interrupts are off on entry. */ SWAPGS /* We are about to clobber %rsp anyway, clobbering here is OK */ - SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp + pushq %rax + SWITCH_TO_KERNEL_CR3 scratch_reg=%rax + popq %rax movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp @@ -104,6 +107,9 @@ ENTRY(entry_SYSENTER_compat) xorl %r14d, %r14d /* nospec r14 */ pushq $0 /* pt_regs->r15 = 0 */ xorl %r15d, %r15d /* nospec r15 */ + + UNWIND_HINT_REGS + cld /* @@ -147,7 +153,7 @@ ENTRY(entry_SYSENTER_compat) popfq jmp .Lsysenter_flags_fixed GLOBAL(__end_entry_SYSENTER_compat) -ENDPROC(entry_SYSENTER_compat) +END(entry_SYSENTER_compat) /* * 32-bit SYSCALL entry. @@ -197,6 +203,7 @@ ENDPROC(entry_SYSENTER_compat) * 0(%esp) arg6 */ ENTRY(entry_SYSCALL_compat) + UNWIND_HINT_EMPTY /* Interrupts are off on entry. */ swapgs @@ -247,6 +254,8 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe) pushq $0 /* pt_regs->r15 = 0 */ xorl %r15d, %r15d /* nospec r15 */ + UNWIND_HINT_REGS + /* * User mode is traced as though IRQs are on, and SYSENTER * turned them off. @@ -335,6 +344,7 @@ END(entry_SYSCALL_compat) * ebp arg6 */ ENTRY(entry_INT80_compat) + UNWIND_HINT_EMPTY /* * Interrupts are off on entry. */ @@ -396,6 +406,9 @@ ENTRY(entry_INT80_compat) xorl %r14d, %r14d /* nospec r14 */ pushq %r15 /* pt_regs->r15 */ xorl %r15d, %r15d /* nospec r15 */ + + UNWIND_HINT_REGS + cld /* -- 2.25.1

1 0

[PATCH openEuler-5.10 0/3] support test GCM/CCM mode for SM4
by shenzijun 17 Nov '21

17 Nov '21

From: 沈子俊 <shenzijun(a)kylinos.cn> The GCM/CCM mode of SM4 is defined in the RFC 8998 specification: https://datatracker.ietf.org/doc/html/rfc8998 沈子俊 (3): crypto: tcrypt - Fix missing return value check crypto: testmgr - Add GCM/CCM mode test of SM4 algorithm crypto: tcrypt - add GCM/CCM mode test for SM4 algorithm crypto/tcrypt.c | 73 ++++++++++++++++++++--- crypto/testmgr.c | 29 ++++++++++ crypto/testmgr.h | 148 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+), 9 deletions(-) -- 2.30.0

3 5

【Meeting Notice】openEuler kernel 技术分享第十四期 & 双周例会 Time: 2021-11-19 14:00-16:30
by Meeting Book 16 Nov '21

16 Nov '21

1 0