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[openeuler:OLK-5.10 2954/2954] arch/arm64/mm/pmem_reserve.c:11:17: sparse: sparse: symbol 'pmem_res' was not declared. Should it be static?
by kernel test robot 10 Jun '25

10 Jun '25

tree: https://gitee.com/openeuler/kernel.git OLK-5.10 head: 90ff3e07cc268a8e40bd578dcc4907a3db419c52 commit: db4cd75bc674e6f473c0a7303b1744155352882c [2954/2954] arm64: register persistent memory via protected memory config: arm64-randconfig-r133-20250610 (https://download.01.org/0day-ci/archive/20250610/202506101929.qhZqxH6c-lkp@…) compiler: aarch64-linux-gcc (GCC) 14.3.0 reproduce: (https://download.01.org/0day-ci/archive/20250610/202506101929.qhZqxH6c-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202506101929.qhZqxH6c-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) vim +/pmem_res +11 arch/arm64/mm/pmem_reserve.c 8 9 #define MAX_REGIONS 8 10 static int pmem_res_cnt; > 11 struct resource pmem_res[MAX_REGIONS]; 12 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

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[PATCH] arm64: Add feature detection for fine grained traps
by frenkjason 10 Jun '25

10 Jun '25

From: Mark Brown <broonie(a)kernel.org> In order to allow us to have shared code for managing fine grained traps for KVM guests add it as a detected feature rather than relying on it being a dependency of other features. Acked-by: Catalin Marinas <catalin.marinas(a)arm.com> Reviewed-by: Eric Auger <eric.auger(a)redhat.com> Signed-off-by: Mark Brown <broonie(a)kernel.org> [maz: converted to ARM64_CPUID_FIELDS()] Link: https://lore.kernel.org/r/20230301-kvm-arm64-fgt-v4-1-1bf8d235ac1f@kernel.o… Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com> Reviewed-by: Miguel Luis <miguel.luis(a)oracle.com> Reviewed-by: Jing Zhang <jingzhangos(a)google.com> Signed-off-by: Marc Zyngier <maz(a)kernel.org> Link: https://lore.kernel.org/r/20230815183903.2735724-10-maz@kernel.org Conflicts: arch/arm64/include/asm/cpucaps.h arch/arm64/kernel/cpufeature.c Signed-off-by: frankyj915 <yangjieyj.yang(a)huawei.com> --- arch/arm64/include/asm/cpucaps.h | 1 + arch/arm64/kernel/cpufeature.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 3107f4a6942d..5999133d9a06 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -65,6 +65,7 @@ #define ARM64_WORKAROUND_HISILICON_ERRATUM_162100125 55 #define ARM64_WORKAROUND_HISILICON_ERRATUM_162100602 56 #define ARM64_HAS_TIDCP1 57 +#define ARM64_HAS_FGT 58 #define ARM64_NCAPS 80 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index ccbce957101a..c82529dffcc7 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1645,6 +1645,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .cpu_enable = cpu_trap_el0_impdef, }, + { + .desc = "Fine Grained Traps", + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .capability = ARM64_HAS_FGT, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64MMFR0_EL1, + .field_pos = ID_AA64MMFR0_FGT_SHIFT, + .sign = FTR_UNSIGNED, + .min_field_value = 1, + }, {}, }; -- 2.25.1

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[PATCH] arm64: add HWCAP for FEAT_HBC (hinted conditional branches)
by frenkjason 10 Jun '25

10 Jun '25

From: Joey Gouly <joey.gouly(a)arm.com> Add a HWCAP for FEAT_HBC, so that userspace can make a decision on using this feature. Signed-off-by: Joey Gouly <joey.gouly(a)arm.com> Cc: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Link: https://lore.kernel.org/r/20230804143746.3900803-2-joey.gouly@arm.com Signed-off-by: Will Deacon <will(a)kernel.org> Conflicts: arch/arm64/include/asm/hwcap.h arch/arm64/include/asm/sysreg.h arch/arm64/include/uapi/asm/hwcap.h arch/arm64/kernel/cpufeature.c arch/arm64/kernel/cpuinfo.c Signed-off-by: frankyj915 <yangjieyj.yang(a)huawei.com> --- arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 1 + arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 98b9359ceff1..6a4446bcae8b 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -88,6 +88,7 @@ #define KERNEL_HWCAP_FRINT __khwcap2_feature(FRINT) #define KERNEL_HWCAP_ECV __khwcap2_feature(ECV) #define KERNEL_HWCAP_DGH __khwcap2_feature(DGH) +#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e579e49a304a..0f97d1c7fe8c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -591,6 +591,7 @@ /* id_aa64isar2 */ #define ID_AA64ISAR2_CLEARBHB_SHIFT 28 +#define ID_AA64ISAR2_BC_SHIFT 20 #define ID_AA64ISAR2_RPRES_SHIFT 4 #define ID_AA64ISAR2_WFXT_SHIFT 0 diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index f36f9eb8dac2..894e5406d641 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -67,5 +67,6 @@ #define HWCAP2_FRINT (1 << 8) #define HWCAP2_ECV (1 << 9) #define HWCAP2_DGH (1 << 10) +#define HWCAP2_HBC (1UL << 44) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index cc50fd0bac99..ccbce957101a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1752,6 +1752,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), #endif HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_BC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_HBC), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index d4c1e6eff56f..d3b1c120e28f 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -88,6 +88,7 @@ static const char *const hwcap_str[] = { "frint", "ecv", "dgh", + "hbc", NULL }; -- 2.25.1

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[PATCH] arm64: trap implementation defined functionality in userspace
by frenkjason 10 Jun '25

10 Jun '25

From: Kristina Martsenko <kristina.martsenko(a)arm.com> The Arm v8.8 extension adds a new control FEAT_TIDCP1 that allows the kernel to disable all implementation-defined system registers and instructions in userspace. This can improve robustness against covert channels between processes, for example in cases where the firmware or hardware didn't disable that functionality by default. The kernel does not currently support any implementation-defined features, as there are no hwcaps for any such features, so disable all imp-def features unconditionally. Any use of imp-def instructions will result in a SIGILL being delivered to the process (same as for undefined instructions). Signed-off-by: Kristina Martsenko <kristina.martsenko(a)arm.com> Link: https://lore.kernel.org/r/20220622115424.683520-1-kristina.martsenko@arm.com Signed-off-by: Will Deacon <will(a)kernel.org> Conflicts: arch/arm64/include/asm/sysreg.h arch/arm64/kernel/cpufeature.c arch/arm64/include/asm/cpucaps.h Signed-off-by: frankyj915 <yangjieyj.yang(a)huawei.com> --- arch/arm64/include/asm/cpucaps.h | 1 + arch/arm64/include/asm/sysreg.h | 5 +++++ arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 163a38107d3d..3107f4a6942d 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -64,6 +64,7 @@ #define ARM64_WORKAROUND_HISILICON_1980005 54 #define ARM64_WORKAROUND_HISILICON_ERRATUM_162100125 55 #define ARM64_WORKAROUND_HISILICON_ERRATUM_162100602 56 +#define ARM64_HAS_TIDCP1 57 #define ARM64_NCAPS 80 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 60c6affb9135..e579e49a304a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -520,6 +520,7 @@ #endif /* SCTLR_EL1 specific flags. */ +#define SCTLR_EL1_TIDCP (BIT(63)) #define SCTLR_EL1_UCI (BIT(26)) #define SCTLR_EL1_E0E (BIT(24)) #define SCTLR_EL1_SPAN (BIT(23)) @@ -678,6 +679,7 @@ /* id_aa64mmfr1 */ #define ID_AA64MMFR1_ECBHB_SHIFT 60 +#define ID_AA64MMFR1_TIDCP1_SHIFT 52 #define ID_AA64MMFR1_PAN_SHIFT 20 #define ID_AA64MMFR1_LOR_SHIFT 16 #define ID_AA64MMFR1_HPD_SHIFT 12 @@ -688,6 +690,9 @@ #define ID_AA64MMFR1_VMIDBITS_8 0 #define ID_AA64MMFR1_VMIDBITS_16 2 +#define ID_AA64MMFR1_TIDCP1_NI 0 +#define ID_AA64MMFR1_TIDCP1_IMP 1 + /* id_aa64mmfr2 */ #define ID_AA64MMFR2_TTL_SHIFT 48 #define ID_AA64MMFR2_FWB_SHIFT 40 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6c0cdac84fb6..cc50fd0bac99 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -228,6 +228,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), @@ -1298,6 +1299,11 @@ static void elf_hwcap_fixup(void) #endif /* ARM64_ERRATUM_1742098 */ } +static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); +} + static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -1628,6 +1634,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .min_field_value = 1, }, #endif + { + .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", + .capability = ARM64_HAS_TIDCP1, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .sys_reg = SYS_ID_AA64MMFR1_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR1_TIDCP1_SHIFT, + .min_field_value = ID_AA64MMFR1_TIDCP1_IMP, + .matches = has_cpuid_feature, + .cpu_enable = cpu_trap_el0_impdef, + }, {}, }; -- 2.25.1

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[PATCH OLK-6.6 0/2] Fix watchdog false positive problem
by Luo Gengkun 10 Jun '25

10 Jun '25

Luo Gengkun (1): [Backport] watchdog: fix watchdog may detect false positive of softlockup Nysal Jan K.A (1): [Backport] watchdog: fix the SOFTLOCKUP_DETECTOR=n case kernel/watchdog.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) -- 2.34.1

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[PATCH 1/3] arm64: trap implementation defined functionality in userspace
by frenkjason 10 Jun '25

10 Jun '25

From: Kristina Martsenko <kristina.martsenko(a)arm.com> The Arm v8.8 extension adds a new control FEAT_TIDCP1 that allows the kernel to disable all implementation-defined system registers and instructions in userspace. This can improve robustness against covert channels between processes, for example in cases where the firmware or hardware didn't disable that functionality by default. The kernel does not currently support any implementation-defined features, as there are no hwcaps for any such features, so disable all imp-def features unconditionally. Any use of imp-def instructions will result in a SIGILL being delivered to the process (same as for undefined instructions). Signed-off-by: Kristina Martsenko <kristina.martsenko(a)arm.com> Link: https://lore.kernel.org/r/20220622115424.683520-1-kristina.martsenko@arm.com Signed-off-by: Will Deacon <will(a)kernel.org> Conflicts: arch/arm64/include/asm/sysreg.h arch/arm64/kernel/cpufeature.c arch/arm64/include/asm/cpucaps.h Signed-off-by: frankyj915 <yangjieyj.yang(a)huawei.com> --- arch/arm64/include/asm/cpucaps.h | 1 + arch/arm64/include/asm/sysreg.h | 5 +++++ arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 163a38107d3d..3107f4a6942d 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -64,6 +64,7 @@ #define ARM64_WORKAROUND_HISILICON_1980005 54 #define ARM64_WORKAROUND_HISILICON_ERRATUM_162100125 55 #define ARM64_WORKAROUND_HISILICON_ERRATUM_162100602 56 +#define ARM64_HAS_TIDCP1 57 #define ARM64_NCAPS 80 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 60c6affb9135..e579e49a304a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -520,6 +520,7 @@ #endif /* SCTLR_EL1 specific flags. */ +#define SCTLR_EL1_TIDCP (BIT(63)) #define SCTLR_EL1_UCI (BIT(26)) #define SCTLR_EL1_E0E (BIT(24)) #define SCTLR_EL1_SPAN (BIT(23)) @@ -678,6 +679,7 @@ /* id_aa64mmfr1 */ #define ID_AA64MMFR1_ECBHB_SHIFT 60 +#define ID_AA64MMFR1_TIDCP1_SHIFT 52 #define ID_AA64MMFR1_PAN_SHIFT 20 #define ID_AA64MMFR1_LOR_SHIFT 16 #define ID_AA64MMFR1_HPD_SHIFT 12 @@ -688,6 +690,9 @@ #define ID_AA64MMFR1_VMIDBITS_8 0 #define ID_AA64MMFR1_VMIDBITS_16 2 +#define ID_AA64MMFR1_TIDCP1_NI 0 +#define ID_AA64MMFR1_TIDCP1_IMP 1 + /* id_aa64mmfr2 */ #define ID_AA64MMFR2_TTL_SHIFT 48 #define ID_AA64MMFR2_FWB_SHIFT 40 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6c0cdac84fb6..cc50fd0bac99 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -228,6 +228,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), @@ -1298,6 +1299,11 @@ static void elf_hwcap_fixup(void) #endif /* ARM64_ERRATUM_1742098 */ } +static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); +} + static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -1628,6 +1634,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .min_field_value = 1, }, #endif + { + .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", + .capability = ARM64_HAS_TIDCP1, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .sys_reg = SYS_ID_AA64MMFR1_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR1_TIDCP1_SHIFT, + .min_field_value = ID_AA64MMFR1_TIDCP1_IMP, + .matches = has_cpuid_feature, + .cpu_enable = cpu_trap_el0_impdef, + }, {}, }; -- 2.25.1

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[PATCH OLK-5.10 0/2] Fix watchdog false positive problem
by Luo Gengkun 10 Jun '25

10 Jun '25

Luo Gengkun (1): watchdog: fix watchdog may detect false positive of softlockup Nysal Jan K.A (1): watchdog: fix the SOFTLOCKUP_DETECTOR=n case include/linux/nmi.h | 1 + kernel/sysctl.c | 2 +- kernel/watchdog.c | 39 ++++++++++++++++++++++++++------------- 3 files changed, 28 insertions(+), 14 deletions(-) -- 2.34.1

2 3

[PATCH OLK-6.6 0/2] Fix watchdog false positive problem
by Luo Gengkun 10 Jun '25

10 Jun '25

Luo Gengkun (1): watchdog: fix watchdog may detect false positive of softlockup Nysal Jan K.A (1): watchdog: fix the SOFTLOCKUP_DETECTOR=n case kernel/watchdog.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) -- 2.34.1

2 3

[PATCH OLK-6.6 0/2] Fix watchdog false positive problem
by Luo Gengkun 10 Jun '25

10 Jun '25

Luo Gengkun (1): [Backport] watchdog: fix watchdog may detect false positive of softlockup Nysal Jan K.A (1): [Backport] watchdog: fix the SOFTLOCKUP_DETECTOR=n case kernel/watchdog.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) -- 2.34.1

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[openeuler:OLK-5.10 2954/2954] net/ipv4/sysctl_net_ipv4.c:477:50: sparse: sparse: incorrect type in argument 3 (different address spaces)
by kernel test robot 10 Jun '25

10 Jun '25

tree: https://gitee.com/openeuler/kernel.git OLK-5.10 head: 90ff3e07cc268a8e40bd578dcc4907a3db419c52 commit: dae7bed961c55d9837eada7f98f34f1adb0e9d21 [2954/2954] tcp_comp: add sysctl for enable/disable compression config: arm64-randconfig-r133-20250610 (https://download.01.org/0day-ci/archive/20250610/202506101624.VyZdjKoM-lkp@…) compiler: aarch64-linux-gcc (GCC) 14.3.0 reproduce: (https://download.01.org/0day-ci/archive/20250610/202506101624.VyZdjKoM-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202506101624.VyZdjKoM-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> net/ipv4/sysctl_net_ipv4.c:477:50: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void * @@ got void [noderef] __user *buffer @@ net/ipv4/sysctl_net_ipv4.c:477:50: sparse: expected void * net/ipv4/sysctl_net_ipv4.c:477:50: sparse: got void [noderef] __user *buffer >> net/ipv4/sysctl_net_ipv4.c:621:35: sparse: sparse: incorrect type in initializer (incompatible argument 3 (different address spaces)) @@ expected int ( [usertype] *proc_handler )( ... ) @@ got int ( * )( ... ) @@ net/ipv4/sysctl_net_ipv4.c:621:35: sparse: expected int ( [usertype] *proc_handler )( ... ) net/ipv4/sysctl_net_ipv4.c:621:35: sparse: got int ( * )( ... ) vim +477 net/ipv4/sysctl_net_ipv4.c 467 468 #if IS_ENABLED(CONFIG_TCP_COMP) 469 static int proc_tcp_compression_ports(struct ctl_table *table, int write, 470 void __user *buffer, size_t *lenp, 471 loff_t *ppos) 472 { 473 unsigned long *bitmap = *(unsigned long **)table->data; 474 unsigned long bitmap_len = table->maxlen; 475 int ret; 476 > 477 ret = proc_do_large_bitmap(table, write, buffer, lenp, ppos); 478 if (write && ret == 0) { 479 if (bitmap_empty(bitmap, bitmap_len)) { 480 if (static_key_enabled(&tcp_have_comp)) 481 static_branch_disable(&tcp_have_comp); 482 } else { 483 if (!static_key_enabled(&tcp_have_comp)) 484 static_branch_enable(&tcp_have_comp); 485 } 486 } 487 488 return ret; 489 } 490 #endif 491 492 static struct ctl_table ipv4_table[] = { 493 { 494 .procname = "tcp_max_orphans", 495 .data = &sysctl_tcp_max_orphans, 496 .maxlen = sizeof(int), 497 .mode = 0644, 498 .proc_handler = proc_dointvec 499 }, 500 { 501 .procname = "inet_peer_threshold", 502 .data = &inet_peer_threshold, 503 .maxlen = sizeof(int), 504 .mode = 0644, 505 .proc_handler = proc_dointvec 506 }, 507 { 508 .procname = "inet_peer_minttl", 509 .data = &inet_peer_minttl, 510 .maxlen = sizeof(int), 511 .mode = 0644, 512 .proc_handler = proc_dointvec_jiffies, 513 }, 514 { 515 .procname = "inet_peer_maxttl", 516 .data = &inet_peer_maxttl, 517 .maxlen = sizeof(int), 518 .mode = 0644, 519 .proc_handler = proc_dointvec_jiffies, 520 }, 521 { 522 .procname = "tcp_mem", 523 .maxlen = sizeof(sysctl_tcp_mem), 524 .data = &sysctl_tcp_mem, 525 .mode = 0644, 526 .proc_handler = proc_doulongvec_minmax, 527 }, 528 { 529 .procname = "tcp_low_latency", 530 .data = &sysctl_tcp_low_latency, 531 .maxlen = sizeof(int), 532 .mode = 0644, 533 .proc_handler = proc_dointvec 534 }, 535 #ifdef CONFIG_NETLABEL 536 { 537 .procname = "cipso_cache_enable", 538 .data = &cipso_v4_cache_enabled, 539 .maxlen = sizeof(int), 540 .mode = 0644, 541 .proc_handler = proc_dointvec, 542 }, 543 { 544 .procname = "cipso_cache_bucket_size", 545 .data = &cipso_v4_cache_bucketsize, 546 .maxlen = sizeof(int), 547 .mode = 0644, 548 .proc_handler = proc_dointvec, 549 }, 550 { 551 .procname = "cipso_rbm_optfmt", 552 .data = &cipso_v4_rbm_optfmt, 553 .maxlen = sizeof(int), 554 .mode = 0644, 555 .proc_handler = proc_dointvec, 556 }, 557 { 558 .procname = "cipso_rbm_strictvalid", 559 .data = &cipso_v4_rbm_strictvalid, 560 .maxlen = sizeof(int), 561 .mode = 0644, 562 .proc_handler = proc_dointvec, 563 }, 564 #endif /* CONFIG_NETLABEL */ 565 { 566 .procname = "tcp_available_ulp", 567 .maxlen = TCP_ULP_BUF_MAX, 568 .mode = 0444, 569 .proc_handler = proc_tcp_available_ulp, 570 }, 571 { 572 .procname = "icmp_msgs_per_sec", 573 .data = &sysctl_icmp_msgs_per_sec, 574 .maxlen = sizeof(int), 575 .mode = 0644, 576 .proc_handler = proc_dointvec_minmax, 577 .extra1 = SYSCTL_ZERO, 578 }, 579 { 580 .procname = "icmp_msgs_burst", 581 .data = &sysctl_icmp_msgs_burst, 582 .maxlen = sizeof(int), 583 .mode = 0644, 584 .proc_handler = proc_dointvec_minmax, 585 .extra1 = SYSCTL_ZERO, 586 }, 587 { 588 .procname = "udp_mem", 589 .data = &sysctl_udp_mem, 590 .maxlen = sizeof(sysctl_udp_mem), 591 .mode = 0644, 592 .proc_handler = proc_doulongvec_minmax, 593 }, 594 { 595 .procname = "fib_sync_mem", 596 .data = &sysctl_fib_sync_mem, 597 .maxlen = sizeof(sysctl_fib_sync_mem), 598 .mode = 0644, 599 .proc_handler = proc_douintvec_minmax, 600 .extra1 = &sysctl_fib_sync_mem_min, 601 .extra2 = &sysctl_fib_sync_mem_max, 602 }, 603 { 604 .procname = "tcp_rx_skb_cache", 605 .data = &tcp_rx_skb_cache_key.key, 606 .mode = 0644, 607 .proc_handler = proc_do_static_key, 608 }, 609 { 610 .procname = "tcp_tx_skb_cache", 611 .data = &tcp_tx_skb_cache_key.key, 612 .mode = 0644, 613 .proc_handler = proc_do_static_key, 614 }, 615 #if IS_ENABLED(CONFIG_TCP_COMP) 616 { 617 .procname = "tcp_compression_ports", 618 .data = &sysctl_tcp_compression_ports, 619 .maxlen = 65536, 620 .mode = 0644, > 621 .proc_handler = proc_tcp_compression_ports, 622 }, 623 #endif 624 { } 625 }; 626 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

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