driver inclusion category: bugfix bugzilla: https://atomgit.com/openeuler/kernel/issues/9066 ---------------------------------------------------------------------- ARMv7 has changed the cycle counter from counter 0 to counter 31, event counters will be indexed starting from 0 instead of 1. With that change, Linux mainline support of Arm core PMU has changed the starting counter id of chained events from 2 to 0, which will conflict to the counter configuration logic of hw-metric feature since hw-metric will subtract that id by 1 to calculate the correct chicken bit for the very first event counter. If the minimum id comes to 0, subtract from it will generate an invalid index which will then triger a warning. Adapt that change of mainline by remove the subtraction, as well as the comment. Fixes: 608277cf9fc2e ("arm64: perf: Add support for HIP12 hw metric") Signed-off-by: Yushan Wang <wangyushan12@huawei.com> Signed-off-by: Ying Jiang <jiangying44@h-partners.com> --- drivers/perf/arm_pmuv3.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index ee56bde77ef5..bbf464942ffa 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -646,9 +646,6 @@ static void armv8pmu_write_evcntr(int idx, u64 value) static inline void armv8pmu_write_reload_counter(struct perf_event *event, u64 value) { - /* Need to be event->hw.idx - 1 since counter 0 is PMCCNTR_EL0 */ - int idx = event->hw.idx - 1; - #define HW_METRIC_RELOAD_CNTR(n) sys_reg(3, 3, 15, 3, (2 + n)) #define write_hw_metric_reload_cntr(_value, _n) \ do { \ @@ -671,7 +668,7 @@ static inline void armv8pmu_write_reload_counter(struct perf_event *event, event->hw.config_base, event->hw.idx); \ } \ } while (0) - write_hw_metric_reload_cntr(value, idx); + write_hw_metric_reload_cntr(value, event->hw.idx); #undef write_hw_metric_reload_cntr #undef HW_METRIC_RELOAD_CNTR } -- 2.33.0