From: Zeng Heng <zengheng4@huawei.com> hulk inclusion category: feature bugzilla: https://gitcode.com/openeuler/kernel/issues/10066 ---------------------------------------- Add detection for the ARM64 Domain-based TLB Invalidation (TLBID) feature as defined in ARMv9.3-A architecture. TLBID allows TLB invalidation operations to be scoped to a specific domain, avoiding the need for global TLB invalidation broadcasts across the system. This reduces cache coherency traffic and improves performance in virtualization scenarios. Signed-off-by: Zeng Heng <zengheng4@huawei.com> --- arch/arm64/Kconfig | 20 ++++++++++++++++++++ arch/arm64/include/asm/cpufeature.h | 7 +++++++ arch/arm64/kernel/cpufeature.c | 10 ++++++++++ arch/arm64/tools/cpucaps | 2 +- arch/arm64/tools/sysreg | 5 ++++- 5 files changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 736908afc98a..fe3fa113e5cd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2303,6 +2303,26 @@ config ARM64_TLB_RANGE The feature introduces new assembly instructions, and they were support when binutils >= 2.30. +config ARM64_TLBID + bool "Enable support for TLBID (TLBI Domains)" + default y + help + TLBI broadcasting all PEs introduces performance noise. By + combining hardware and software, TLBID (TLBI Domain) limit TLBI + to an appropriate scope, avoiding the performance overhead caused + by broadcasting. + + Arm Architecture defines the FEAT_TLBID extension since Armv9.3, + when present, allows the OSPM to target TLB invalidations to + a specific domain. A TLBI domain can be contained in multiple + parent domains. + + The TLBI table lists all the PE and SMMU components and the TLBI + Domains that each component belongs to. + + The feature is detected at runtime, and will remain disabled + if the system does not implement the feature. + config ARM64_MPAM bool "Enable support for MPAM" select ACPI_MPAM if ACPI diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 714f3db48f9f..9e617d40c50b 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -927,6 +927,13 @@ static inline bool system_supports_sysinstr128(void) return cpus_have_const_cap(ARM64_HAS_SYSINSTR128); } +static inline bool system_supports_tlbid(void) +{ + return IS_ENABLED(CONFIG_ARM64_TLBID) && + system_supports_sysinstr128() && + cpus_have_const_cap(ARM64_HAS_TLBID); +} + static inline bool cpus_support_mpam(void) { return IS_ENABLED(CONFIG_ARM64_MPAM) && diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 13df5120dfe1..82468372fdd4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -470,6 +470,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_TLBID_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -3342,6 +3343,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, SYSINSTR_128, IMP) }, +#ifdef CONFIG_ARM64_TLBID + { + .desc = "TLBI Domains", + .capability = ARM64_HAS_TLBID, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, TLBID, IMP) + }, +#endif {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 7e1c20c32243..c0409ba0dcca 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -120,7 +120,7 @@ HAS_LSUI HAS_FPMR HAS_BBML3 HAS_SYSINSTR128 -KABI_RESERVE_13 +HAS_TLBID KABI_RESERVE_14 KABI_RESERVE_15 KABI_RESERVE_16 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b77ebdc4e776..1e8dee638509 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2295,7 +2295,10 @@ UnsignedEnum 47:44 SRMASK 0b0000 NI 0b0001 IMP EndEnum -Res0 43:40 +UnsignedEnum 43:40 TLBID + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 39:36 E3DSE 0b0000 NI 0b0001 IMP -- 2.33.0