virt inclusion category: feature bugzilla: https://atomgit.com/openeuler/kernel/issues/8756 CVE: NA ----------------------------------------------------------- For compatibility reasons, add MIDR definitions MIDR_HISI_HIP10, MIDR_HISI_HIP10C, MIDR_HISI_HIP13 and use MIDR instead of cpu type to determine whether NCSNP, IPIv and DVMBM are supported. Signed-off-by: liqiqi <liqiqi23@huawei.com> --- arch/arm64/include/asm/cputype.h | 6 ++++++ arch/arm64/kvm/hisilicon/hisi_virt.c | 23 +++++++++++++++-------- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 490c2ac36ac0..42ee48192443 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -142,7 +142,10 @@ #define HISI_CPU_PART_TSV110 0xD01 #define HISI_CPU_PART_LINXICORE9100 0xD02 +#define HISI_CPU_PART_HIP10 0xD03 +#define HISI_CPU_PART_HIP10C 0xD45 #define HISI_CPU_PART_HIP12 0xD06 +#define HISI_CPU_PART_HIP13 0xD08 #define APPLE_CPU_PART_M1_ICESTORM 0x022 #define APPLE_CPU_PART_M1_FIRESTORM 0x023 @@ -230,7 +233,10 @@ #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) #define MIDR_HISI_LINXICORE9100 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_LINXICORE9100) +#define MIDR_HISI_HIP10 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP10) +#define MIDR_HISI_HIP10C MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP10C) #define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12) +#define MIDR_HISI_HIP13 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP13) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index d82c7691836e..b67e219dff65 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -121,7 +121,7 @@ bool hisi_ncsnp_supported(void) unsigned int high; bool supported = false; - if (cpu_type != HI_1620) + if (read_cpuid_id() != MIDR_HISI_TSV110) return supported; base = ioremap(NCSNP_MMIO_BASE, 4); @@ -171,7 +171,9 @@ early_param("kvm-arm.ipiv_enabled", early_ipiv_enable); bool hisi_ipiv_supported(void) { - if (cpu_type != HI_IP12) + u32 midr = read_cpuid_id(); + + if (midr != MIDR_HISI_HIP12 && midr != MIDR_HISI_HIP13) return false; /* Determine whether IPIV is supported by the hardware */ @@ -232,8 +234,10 @@ void ipiv_gicd_init(void) bool hisi_dvmbm_supported(void) { - if (cpu_type != HI_IP10 && cpu_type != HI_IP10C && - cpu_type != HI_IP12) + u32 midr = read_cpuid_id(); + + if (midr != MIDR_HISI_HIP10 && midr != MIDR_HISI_HIP10C && + midr != MIDR_HISI_HIP12 && midr != MIDR_HISI_HIP13) return false; if (!is_kernel_in_hyp_mode()) { @@ -542,6 +546,7 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) struct kvm_vcpu *tmp; cpumask_t mask; unsigned long i; + u32 midr; /* Don't bother on old hardware */ if (!kvm_dvmbm_support) @@ -581,10 +586,11 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) * Re-calculate LSUDVMBM_EL2 for this VM and kick all vcpus * out to reload the LSUDVMBM configuration. */ - if (cpu_type == HI_IP12) - kvm_update_vm_lsudvmbm_hip12(kvm); - else + midr = read_cpuid_id(); + if (midr == MIDR_HISI_HIP10 || midr == MIDR_HISI_HIP10C) kvm_update_vm_lsudvmbm(kvm); + else + kvm_update_vm_lsudvmbm_hip12(kvm); kvm_make_all_cpus_request(kvm, KVM_REQ_RELOAD_TLBI_DVMBM); out_unlock: @@ -608,8 +614,9 @@ void kvm_get_pg_cfg(void) u32 pg_cfgs[MAX_PG_CFG_SOCKETS * MAX_DIES_PER_SOCKET]; u64 mn_phy_base; u32 val; + u32 midr = read_cpuid_id(); - if (cpu_type == HI_IP12) + if (midr != MIDR_HISI_HIP10 && midr != MIDR_HISI_HIP10C) return; socket_num = kvm_get_socket_num(); -- 2.43.0