From: Yifan Wu <wuyifan50@huawei.com> mainline inclusion from mainline-v7.1-rc1 commit 74cd4e0e5399480e3fab2cd6a6cbdb17f673c335 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/8904 CVE: NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i... ---------------------------------------------------------------------- The function executes a CBEQ instruction which is valid if the CPU supports the CMPBR extension. The CBEQ branches to skip the following UDF instruction, and no SIGILL is generated. Otherwise, it will generate a SIGILL. Signed-off-by: Yifan Wu <wuyifan50@huawei.com> Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Conflicts: tools/testing/selftests/arm64/abi/hwcap.c [context conflict] Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Hongye Lin <linhongye@h-partners.com> --- tools/testing/selftests/arm64/abi/hwcap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index ff1821c0058c..8d929174e0d3 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -48,7 +48,8 @@ static void atomics_sigill(void) static void cmpbr_sigill(void) { - /* Not implemented, too complicated and unreliable anyway */ + asm volatile(".inst 0x74C00040\n" /* CBEQ w0, w0, +8 */ + "udf #0" : : : "cc"); /* UDF #0 */ } -- 2.33.0