November 2023 - Kernel-build - mailweb.openeuler.org

[PATCH openEuler-20.03-LTS-SP4 v2] support CPU turbo feature
by Yu Liao 20 Nov '23

20 Nov '23

Backport the following patches: cpufreq: change '.set_boost' to act on one policy cpufreq: CPPC: add SW BOOST support --- v2: modified return vaule of cpufreq_boost_set_sw() to -EINVAL --- kernel.spec | 5 +- ...ange-.set_boost-to-act-on-one-policy.patch | 186 ++++++++++++++++++ ...48-cpufreq-CPPC-add-SW-BOOST-support.patch | 142 +++++++++++++ series.conf | 2 + 4 files changed, 334 insertions(+), 1 deletion(-) create mode 100644 patches/0647-cpufreq-change-.set_boost-to-act-on-one-policy.patch create mode 100644 patches/0648-cpufreq-CPPC-add-SW-BOOST-support.patch diff --git a/kernel.spec b/kernel.spec index 21a246f26f45..c6ac5b3f416b 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0246 +Release: %{hulkrelease}.0247 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -850,6 +850,9 @@ fi %changelog +* Mon Nov 20 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2311.3.0.0247 +- Backport cpu turbo patches + * Fri Nov 17 2023 Zhou Kaiqi <zhoukaiqi(a)huawei.com> - 4.19.90-2311.3.0.0246 - genirq: Increase the number of IRQ descriptors - irqchip: gic-v3: Collection table support muti pages diff --git a/patches/0647-cpufreq-change-.set_boost-to-act-on-one-policy.patch b/patches/0647-cpufreq-change-.set_boost-to-act-on-one-policy.patch new file mode 100644 index 000000000000..7ca215fc4481 --- /dev/null +++ b/patches/0647-cpufreq-change-.set_boost-to-act-on-one-policy.patch @@ -0,0 +1,186 @@ +From a93e5e087b753c9fe954e4a82ae1224ba56732d0 Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:30 +0800 +Subject: [PATCH openEuler-1.0-LTS 1/2] cpufreq: change '.set_boost' to act on + one policy + +mainline inclusion +from mainline-v5.8-rc1 +commit cf6fada71543ceea0f6228ffdc0b85778f3f5a6e +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +Macro 'for_each_active_policy()' is defined internally. To avoid some +cpufreq driver needing this macro to iterate over all the policies in +'.set_boost' callback, we redefine '.set_boost' to act on only one +policy and pass the policy as an argument. + +'cpufreq_boost_trigger_state()' iterates over all the policies to set +boost for the system. + +This is preparation for adding SW BOOST support for CPPC. + +To protect Boost enable/disable by sysfs from CPU online/offline, +add 'cpu_hotplug_lock' before calling '.set_boost' for each CPU. + +Also move the lock from 'set_boost()' to 'store_cpb()' in +acpi_cpufreq. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject & changelog ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> + +Conflicts: + drivers/cpufreq/cpufreq.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/acpi-cpufreq.c | 14 ++++---- + drivers/cpufreq/cpufreq.c | 58 +++++++++++++++++++--------------- + include/linux/cpufreq.h | 2 +- + 3 files changed, 42 insertions(+), 32 deletions(-) + +diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c +index ce0a51849f66..189c7c9e2641 100644 +--- a/drivers/cpufreq/acpi-cpufreq.c ++++ b/drivers/cpufreq/acpi-cpufreq.c +@@ -147,12 +147,12 @@ static void boost_set_msr_each(void *p_en) + boost_set_msr(enable); + } + +-static int set_boost(int val) ++static int set_boost(struct cpufreq_policy *policy, int val) + { +- get_online_cpus(); +- on_each_cpu(boost_set_msr_each, (void *)(long)val, 1); +- put_online_cpus(); +- pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); ++ on_each_cpu_mask(policy->cpus, boost_set_msr_each, ++ (void *)(long)val, 1); ++ pr_debug("CPU %*pbl: Core Boosting %sabled.\n", ++ cpumask_pr_args(policy->cpus), val ? "en" : "dis"); + + return 0; + } +@@ -183,7 +183,9 @@ static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, + if (ret || val > 1) + return -EINVAL; + +- set_boost(val); ++ get_online_cpus(); ++ set_boost(policy, val); ++ put_online_cpus(); + + return count; + } +diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c +index 99ca9c50a88f..49ed22b45fb7 100644 +--- a/drivers/cpufreq/cpufreq.c ++++ b/drivers/cpufreq/cpufreq.c +@@ -2347,34 +2347,32 @@ EXPORT_SYMBOL(cpufreq_update_policy); + /********************************************************************* + * BOOST * + *********************************************************************/ +-static int cpufreq_boost_set_sw(int state) ++static int cpufreq_boost_set_sw(struct cpufreq_policy *policy, int state) + { +- struct cpufreq_policy *policy; + int ret = -EINVAL; + +- for_each_active_policy(policy) { +- if (!policy->freq_table) +- continue; +- +- ret = cpufreq_frequency_table_cpuinfo(policy, +- policy->freq_table); +- if (ret) { +- pr_err("%s: Policy frequency update failed\n", +- __func__); +- break; +- } ++ if (!policy->freq_table) ++ return -EINVAL; + +- down_write(&policy->rwsem); +- policy->user_policy.max = policy->max; +- cpufreq_governor_limits(policy); +- up_write(&policy->rwsem); ++ ret = cpufreq_frequency_table_cpuinfo(policy, ++ policy->freq_table); ++ if (ret) { ++ pr_err("%s: Policy frequency update failed\n", ++ __func__); ++ return ret; + } + ++ down_write(&policy->rwsem); ++ policy->user_policy.max = policy->max; ++ cpufreq_governor_limits(policy); ++ up_write(&policy->rwsem); ++ + return ret; + } + + int cpufreq_boost_trigger_state(int state) + { ++ struct cpufreq_policy *policy; + unsigned long flags; + int ret = 0; + +@@ -2385,15 +2383,25 @@ int cpufreq_boost_trigger_state(int state) + cpufreq_driver->boost_enabled = state; + write_unlock_irqrestore(&cpufreq_driver_lock, flags); + +- ret = cpufreq_driver->set_boost(state); +- if (ret) { +- write_lock_irqsave(&cpufreq_driver_lock, flags); +- cpufreq_driver->boost_enabled = !state; +- write_unlock_irqrestore(&cpufreq_driver_lock, flags); +- +- pr_err("%s: Cannot %s BOOST\n", +- __func__, state ? "enable" : "disable"); ++ get_online_cpus(); ++ for_each_active_policy(policy) { ++ ret = cpufreq_driver->set_boost(policy, state); ++ if (ret) ++ goto err_reset_state; + } ++ put_online_cpus(); ++ ++ return 0; ++ ++err_reset_state: ++ put_online_cpus(); ++ ++ write_lock_irqsave(&cpufreq_driver_lock, flags); ++ cpufreq_driver->boost_enabled = !state; ++ write_unlock_irqrestore(&cpufreq_driver_lock, flags); ++ ++ pr_err("%s: Cannot %s BOOST\n", ++ __func__, state ? "enable" : "disable"); + + return ret; + } +diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h +index 3361663144a1..ff6b10552c86 100644 +--- a/include/linux/cpufreq.h ++++ b/include/linux/cpufreq.h +@@ -334,7 +334,7 @@ struct cpufreq_driver { + + /* platform specific boost support code */ + bool boost_enabled; +- int (*set_boost)(int state); ++ int (*set_boost)(struct cpufreq_policy *policy, int state); + }; + + /* flags */ +-- +2.25.1 + diff --git a/patches/0648-cpufreq-CPPC-add-SW-BOOST-support.patch b/patches/0648-cpufreq-CPPC-add-SW-BOOST-support.patch new file mode 100644 index 000000000000..a8dfe4af2621 --- /dev/null +++ b/patches/0648-cpufreq-CPPC-add-SW-BOOST-support.patch @@ -0,0 +1,142 @@ +From 5cca93b9a9e4690a8491f6fde455ff0268f1e92a Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:31 +0800 +Subject: [PATCH openEuler-1.0-LTS 2/2] cpufreq: CPPC: add SW BOOST support + +mainline inclusion +from mainline-v5.8-rc1 +commit 54e74df5d76dea824c7c0c9d1b97150bf9b33793 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +To add SW BOOST support for CPPC, we need to get the max frequency of +boost mode and non-boost mode. ACPI spec 6.2 section 8.4.7.1 describes +the following two CPC registers. + +"Highest performance is the absolute maximum performance an individual +processor may reach, assuming ideal conditions. This performance level +may not be sustainable for long durations, and may only be achievable if +other platform components are in a specific state; for example, it may +require other processors be in an idle state. + +Nominal Performance is the maximum sustained performance level of the +processor, assuming ideal operating conditions. In absence of an +external constraint (power, thermal, etc.) this is the performance level +the platform is expected to be able to maintain continuously. All +processors are expected to be able to sustain their nominal performance +state simultaneously." + +To add SW BOOST support for CPPC, we can use Highest Performance as the +max performance in boost mode and Nominal Performance as the max +performance in non-boost mode. If the Highest Performance is greater +than the Nominal Performance, we assume SW BOOST is supported. + +The current CPPC driver does not support SW BOOST and use 'Highest +Performance' as the max performance the CPU can achieve. 'Nominal +Performance' is used to convert 'performance' to 'frequency'. That +means, if firmware enable boost and provide a value for Highest +Performance which is greater than Nominal Performance, boost feature is +enabled by default. + +Because SW BOOST is disabled by default, so, after this patch, boost +feature is disabled by default even if boost is enabled by firmware. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/cppc_cpufreq.c | 35 ++++++++++++++++++++++++++++++++-- + 1 file changed, 33 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c +index 0a245f1caa95..15cffca10f1a 100644 +--- a/drivers/cpufreq/cppc_cpufreq.c ++++ b/drivers/cpufreq/cppc_cpufreq.c +@@ -41,6 +41,7 @@ + * requested etc. + */ + static struct cppc_cpudata **all_cpu_data; ++static bool boost_supported; + + struct cppc_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +@@ -314,7 +315,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * Section 8.4.7.1.1.5 of ACPI 6.1 spec) + */ + policy->min = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_nonlinear_perf); +- policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + /* + * Set cpuinfo.min_freq to Lowest to make the full range of performance +@@ -322,7 +323,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * nonlinear perf + */ + policy->cpuinfo.min_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_perf); +- policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num); + policy->shared_type = cpu->shared_type; +@@ -347,6 +348,13 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + + cpu->cur_policy = policy; + ++ /* ++ * If 'highest_perf' is greater than 'nominal_perf', we assume CPU Boost ++ * is supported. ++ */ ++ if (cpu->perf_caps.highest_perf > cpu->perf_caps.nominal_perf) ++ boost_supported = true; ++ + /* Set policy->cur to max now. The governors will adjust later. */ + policy->cur = cppc_cpufreq_perf_to_khz(cpu, + cpu->perf_caps.highest_perf); +@@ -414,6 +422,28 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpunum) + return cppc_get_rate_from_fbctrs(cpu, fb_ctrs_t0, fb_ctrs_t1); + } + ++static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state) ++{ ++ struct cppc_cpudata *cpudata; ++ int ret; ++ ++ if (!boost_supported) { ++ pr_err("BOOST not supported by CPU or firmware\n"); ++ return -EINVAL; ++ } ++ ++ cpudata = all_cpu_data[policy->cpu]; ++ if (state) ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.highest_perf); ++ else ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.nominal_perf); ++ policy->cpuinfo.max_freq = policy->max; ++ ++ return 0; ++} ++ + static struct cpufreq_driver cppc_cpufreq_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = cppc_verify_policy, +@@ -421,6 +451,7 @@ static struct cpufreq_driver cppc_cpufreq_driver = { + .get = cppc_cpufreq_get_rate, + .init = cppc_cpufreq_cpu_init, + .stop_cpu = cppc_cpufreq_stop_cpu, ++ .set_boost = cppc_cpufreq_set_boost, + .name = "cppc_cpufreq", + }; + +-- +2.25.1 + diff --git a/series.conf b/series.conf index 06e45f51800c..9da341a8f57f 100644 --- a/series.conf +++ b/series.conf @@ -647,3 +647,5 @@ patches/0643-net-hns3-Fix-ethtool_-Ops-gen_-Improper-modification.patch patches/0644-net-hns3-Fix-unreasonable-modifications-caused-by-ro.patch patches/0645-irqchip-gic-v3-Collection-table-support-muti-pages.patch patches/0646-genirq-Increase-the-number-of-IRQ-descriptors.patch +patches/0647-cpufreq-change-.set_boost-to-act-on-one-policy.patch +patches/0648-cpufreq-CPPC-add-SW-BOOST-support.patch -- 2.25.1

2 1

[PATCH openEuler-20.03-LTS-SP4 v2] support CPU turbo feature
by Yu Liao 16 Nov '23

16 Nov '23

v1 -> v2: fix typo in series.conf Backport the following patches: cpufreq: change '.set_boost' to act on one policy cpufreq: CPPC: add SW BOOST support --- kernel.spec | 5 +- ...ange-.set_boost-to-act-on-one-policy.patch | 186 ++++++++++++++++++ ...63-cpufreq-CPPC-add-SW-BOOST-support.patch | 142 +++++++++++++ series.conf | 2 + 4 files changed, 334 insertions(+), 1 deletion(-) create mode 100644 patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch create mode 100644 patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch diff --git a/kernel.spec b/kernel.spec index 39fc740d35f6..afb398809fbb 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0244 +Release: %{hulkrelease}.0245 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -850,6 +850,9 @@ fi %changelog +* Thu Nov 16 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2311.3.0.0245 +- Backport cpu turbo patches + * Wed Nov 15 2023 Luo Shengwei <luoshengwei(a)huawei.com> - 4.19.90-2311.3.0.0244 - !2803 drivers/gmjstcm: fix a dev_err() call in spi tcm device probe - !2841 drm/qxl: fix UAF on handle creation diff --git a/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch b/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch new file mode 100644 index 000000000000..83a5195807bb --- /dev/null +++ b/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch @@ -0,0 +1,186 @@ +From a93e5e087b753c9fe954e4a82ae1224ba56732d0 Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:30 +0800 +Subject: [PATCH openEuler-1.0-LTS 1/2] cpufreq: change '.set_boost' to act on + one policy + +mainline inclusion +from mainline-v5.8-rc1 +commit cf6fada71543ceea0f6228ffdc0b85778f3f5a6e +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +Macro 'for_each_active_policy()' is defined internally. To avoid some +cpufreq driver needing this macro to iterate over all the policies in +'.set_boost' callback, we redefine '.set_boost' to act on only one +policy and pass the policy as an argument. + +'cpufreq_boost_trigger_state()' iterates over all the policies to set +boost for the system. + +This is preparation for adding SW BOOST support for CPPC. + +To protect Boost enable/disable by sysfs from CPU online/offline, +add 'cpu_hotplug_lock' before calling '.set_boost' for each CPU. + +Also move the lock from 'set_boost()' to 'store_cpb()' in +acpi_cpufreq. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject & changelog ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> + +Conflicts: + drivers/cpufreq/cpufreq.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/acpi-cpufreq.c | 14 ++++---- + drivers/cpufreq/cpufreq.c | 58 +++++++++++++++++++--------------- + include/linux/cpufreq.h | 2 +- + 3 files changed, 42 insertions(+), 32 deletions(-) + +diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c +index ce0a51849f66..189c7c9e2641 100644 +--- a/drivers/cpufreq/acpi-cpufreq.c ++++ b/drivers/cpufreq/acpi-cpufreq.c +@@ -147,12 +147,12 @@ static void boost_set_msr_each(void *p_en) + boost_set_msr(enable); + } + +-static int set_boost(int val) ++static int set_boost(struct cpufreq_policy *policy, int val) + { +- get_online_cpus(); +- on_each_cpu(boost_set_msr_each, (void *)(long)val, 1); +- put_online_cpus(); +- pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); ++ on_each_cpu_mask(policy->cpus, boost_set_msr_each, ++ (void *)(long)val, 1); ++ pr_debug("CPU %*pbl: Core Boosting %sabled.\n", ++ cpumask_pr_args(policy->cpus), val ? "en" : "dis"); + + return 0; + } +@@ -183,7 +183,9 @@ static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, + if (ret || val > 1) + return -EINVAL; + +- set_boost(val); ++ get_online_cpus(); ++ set_boost(policy, val); ++ put_online_cpus(); + + return count; + } +diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c +index 99ca9c50a88f..49ed22b45fb7 100644 +--- a/drivers/cpufreq/cpufreq.c ++++ b/drivers/cpufreq/cpufreq.c +@@ -2347,34 +2347,32 @@ EXPORT_SYMBOL(cpufreq_update_policy); + /********************************************************************* + * BOOST * + *********************************************************************/ +-static int cpufreq_boost_set_sw(int state) ++static int cpufreq_boost_set_sw(struct cpufreq_policy *policy, int state) + { +- struct cpufreq_policy *policy; + int ret = -EINVAL; + +- for_each_active_policy(policy) { +- if (!policy->freq_table) +- continue; +- +- ret = cpufreq_frequency_table_cpuinfo(policy, +- policy->freq_table); +- if (ret) { +- pr_err("%s: Policy frequency update failed\n", +- __func__); +- break; +- } ++ if (!policy->freq_table) ++ return -ENXIO; + +- down_write(&policy->rwsem); +- policy->user_policy.max = policy->max; +- cpufreq_governor_limits(policy); +- up_write(&policy->rwsem); ++ ret = cpufreq_frequency_table_cpuinfo(policy, ++ policy->freq_table); ++ if (ret) { ++ pr_err("%s: Policy frequency update failed\n", ++ __func__); ++ return ret; + } + ++ down_write(&policy->rwsem); ++ policy->user_policy.max = policy->max; ++ cpufreq_governor_limits(policy); ++ up_write(&policy->rwsem); ++ + return ret; + } + + int cpufreq_boost_trigger_state(int state) + { ++ struct cpufreq_policy *policy; + unsigned long flags; + int ret = 0; + +@@ -2385,15 +2383,25 @@ int cpufreq_boost_trigger_state(int state) + cpufreq_driver->boost_enabled = state; + write_unlock_irqrestore(&cpufreq_driver_lock, flags); + +- ret = cpufreq_driver->set_boost(state); +- if (ret) { +- write_lock_irqsave(&cpufreq_driver_lock, flags); +- cpufreq_driver->boost_enabled = !state; +- write_unlock_irqrestore(&cpufreq_driver_lock, flags); +- +- pr_err("%s: Cannot %s BOOST\n", +- __func__, state ? "enable" : "disable"); ++ get_online_cpus(); ++ for_each_active_policy(policy) { ++ ret = cpufreq_driver->set_boost(policy, state); ++ if (ret) ++ goto err_reset_state; + } ++ put_online_cpus(); ++ ++ return 0; ++ ++err_reset_state: ++ put_online_cpus(); ++ ++ write_lock_irqsave(&cpufreq_driver_lock, flags); ++ cpufreq_driver->boost_enabled = !state; ++ write_unlock_irqrestore(&cpufreq_driver_lock, flags); ++ ++ pr_err("%s: Cannot %s BOOST\n", ++ __func__, state ? "enable" : "disable"); + + return ret; + } +diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h +index 3361663144a1..ff6b10552c86 100644 +--- a/include/linux/cpufreq.h ++++ b/include/linux/cpufreq.h +@@ -334,7 +334,7 @@ struct cpufreq_driver { + + /* platform specific boost support code */ + bool boost_enabled; +- int (*set_boost)(int state); ++ int (*set_boost)(struct cpufreq_policy *policy, int state); + }; + + /* flags */ +-- +2.25.1 + diff --git a/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch b/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch new file mode 100644 index 000000000000..a8dfe4af2621 --- /dev/null +++ b/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch @@ -0,0 +1,142 @@ +From 5cca93b9a9e4690a8491f6fde455ff0268f1e92a Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:31 +0800 +Subject: [PATCH openEuler-1.0-LTS 2/2] cpufreq: CPPC: add SW BOOST support + +mainline inclusion +from mainline-v5.8-rc1 +commit 54e74df5d76dea824c7c0c9d1b97150bf9b33793 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +To add SW BOOST support for CPPC, we need to get the max frequency of +boost mode and non-boost mode. ACPI spec 6.2 section 8.4.7.1 describes +the following two CPC registers. + +"Highest performance is the absolute maximum performance an individual +processor may reach, assuming ideal conditions. This performance level +may not be sustainable for long durations, and may only be achievable if +other platform components are in a specific state; for example, it may +require other processors be in an idle state. + +Nominal Performance is the maximum sustained performance level of the +processor, assuming ideal operating conditions. In absence of an +external constraint (power, thermal, etc.) this is the performance level +the platform is expected to be able to maintain continuously. All +processors are expected to be able to sustain their nominal performance +state simultaneously." + +To add SW BOOST support for CPPC, we can use Highest Performance as the +max performance in boost mode and Nominal Performance as the max +performance in non-boost mode. If the Highest Performance is greater +than the Nominal Performance, we assume SW BOOST is supported. + +The current CPPC driver does not support SW BOOST and use 'Highest +Performance' as the max performance the CPU can achieve. 'Nominal +Performance' is used to convert 'performance' to 'frequency'. That +means, if firmware enable boost and provide a value for Highest +Performance which is greater than Nominal Performance, boost feature is +enabled by default. + +Because SW BOOST is disabled by default, so, after this patch, boost +feature is disabled by default even if boost is enabled by firmware. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/cppc_cpufreq.c | 35 ++++++++++++++++++++++++++++++++-- + 1 file changed, 33 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c +index 0a245f1caa95..15cffca10f1a 100644 +--- a/drivers/cpufreq/cppc_cpufreq.c ++++ b/drivers/cpufreq/cppc_cpufreq.c +@@ -41,6 +41,7 @@ + * requested etc. + */ + static struct cppc_cpudata **all_cpu_data; ++static bool boost_supported; + + struct cppc_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +@@ -314,7 +315,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * Section 8.4.7.1.1.5 of ACPI 6.1 spec) + */ + policy->min = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_nonlinear_perf); +- policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + /* + * Set cpuinfo.min_freq to Lowest to make the full range of performance +@@ -322,7 +323,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * nonlinear perf + */ + policy->cpuinfo.min_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_perf); +- policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num); + policy->shared_type = cpu->shared_type; +@@ -347,6 +348,13 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + + cpu->cur_policy = policy; + ++ /* ++ * If 'highest_perf' is greater than 'nominal_perf', we assume CPU Boost ++ * is supported. ++ */ ++ if (cpu->perf_caps.highest_perf > cpu->perf_caps.nominal_perf) ++ boost_supported = true; ++ + /* Set policy->cur to max now. The governors will adjust later. */ + policy->cur = cppc_cpufreq_perf_to_khz(cpu, + cpu->perf_caps.highest_perf); +@@ -414,6 +422,28 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpunum) + return cppc_get_rate_from_fbctrs(cpu, fb_ctrs_t0, fb_ctrs_t1); + } + ++static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state) ++{ ++ struct cppc_cpudata *cpudata; ++ int ret; ++ ++ if (!boost_supported) { ++ pr_err("BOOST not supported by CPU or firmware\n"); ++ return -EINVAL; ++ } ++ ++ cpudata = all_cpu_data[policy->cpu]; ++ if (state) ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.highest_perf); ++ else ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.nominal_perf); ++ policy->cpuinfo.max_freq = policy->max; ++ ++ return 0; ++} ++ + static struct cpufreq_driver cppc_cpufreq_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = cppc_verify_policy, +@@ -421,6 +451,7 @@ static struct cpufreq_driver cppc_cpufreq_driver = { + .get = cppc_cpufreq_get_rate, + .init = cppc_cpufreq_cpu_init, + .stop_cpu = cppc_cpufreq_stop_cpu, ++ .set_boost = cppc_cpufreq_set_boost, + .name = "cppc_cpufreq", + }; + +-- +2.25.1 + diff --git a/series.conf b/series.conf index d78c29dea2e9..89ccb80a37d8 100644 --- a/series.conf +++ b/series.conf @@ -362,3 +362,5 @@ patches/0358-spi-hisi-sfc-v3xx-add-address-mode-check.patch patches/0359-spi-hisi-sfc-v3xx-fix-potential-irq-race-condition.patch patches/0360-spi-hisi-sfc-v3xx-drop-unnecessary-ACPI_PTR-and-rela.patch patches/0361-config-arm64-Build-HiSilicon-SPI-SFC-driver-as-modul.patch +patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch +patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch -- 2.25.1

2 1

[PATCH openEuler-20.03-LTS-SP4] support CPU turbo feature
by Yu Liao 16 Nov '23

16 Nov '23

Backport the following patches: cpufreq: change '.set_boost' to act on one policy cpufreq: CPPC: add SW BOOST support --- kernel.spec | 5 +- ...ange-.set_boost-to-act-on-one-policy.patch | 186 ++++++++++++++++++ ...63-cpufreq-CPPC-add-SW-BOOST-support.patch | 142 +++++++++++++ series.conf | 2 + 4 files changed, 334 insertions(+), 1 deletion(-) create mode 100644 patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch create mode 100644 patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch diff --git a/kernel.spec b/kernel.spec index 39fc740d35f6..afb398809fbb 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0244 +Release: %{hulkrelease}.0245 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -850,6 +850,9 @@ fi %changelog +* Thu Nov 16 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2311.3.0.0245 +- Backport cpu turbo patches + * Wed Nov 15 2023 Luo Shengwei <luoshengwei(a)huawei.com> - 4.19.90-2311.3.0.0244 - !2803 drivers/gmjstcm: fix a dev_err() call in spi tcm device probe - !2841 drm/qxl: fix UAF on handle creation diff --git a/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch b/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch new file mode 100644 index 000000000000..83a5195807bb --- /dev/null +++ b/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch @@ -0,0 +1,186 @@ +From a93e5e087b753c9fe954e4a82ae1224ba56732d0 Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:30 +0800 +Subject: [PATCH openEuler-1.0-LTS 1/2] cpufreq: change '.set_boost' to act on + one policy + +mainline inclusion +from mainline-v5.8-rc1 +commit cf6fada71543ceea0f6228ffdc0b85778f3f5a6e +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +Macro 'for_each_active_policy()' is defined internally. To avoid some +cpufreq driver needing this macro to iterate over all the policies in +'.set_boost' callback, we redefine '.set_boost' to act on only one +policy and pass the policy as an argument. + +'cpufreq_boost_trigger_state()' iterates over all the policies to set +boost for the system. + +This is preparation for adding SW BOOST support for CPPC. + +To protect Boost enable/disable by sysfs from CPU online/offline, +add 'cpu_hotplug_lock' before calling '.set_boost' for each CPU. + +Also move the lock from 'set_boost()' to 'store_cpb()' in +acpi_cpufreq. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject & changelog ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> + +Conflicts: + drivers/cpufreq/cpufreq.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/acpi-cpufreq.c | 14 ++++---- + drivers/cpufreq/cpufreq.c | 58 +++++++++++++++++++--------------- + include/linux/cpufreq.h | 2 +- + 3 files changed, 42 insertions(+), 32 deletions(-) + +diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c +index ce0a51849f66..189c7c9e2641 100644 +--- a/drivers/cpufreq/acpi-cpufreq.c ++++ b/drivers/cpufreq/acpi-cpufreq.c +@@ -147,12 +147,12 @@ static void boost_set_msr_each(void *p_en) + boost_set_msr(enable); + } + +-static int set_boost(int val) ++static int set_boost(struct cpufreq_policy *policy, int val) + { +- get_online_cpus(); +- on_each_cpu(boost_set_msr_each, (void *)(long)val, 1); +- put_online_cpus(); +- pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); ++ on_each_cpu_mask(policy->cpus, boost_set_msr_each, ++ (void *)(long)val, 1); ++ pr_debug("CPU %*pbl: Core Boosting %sabled.\n", ++ cpumask_pr_args(policy->cpus), val ? "en" : "dis"); + + return 0; + } +@@ -183,7 +183,9 @@ static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, + if (ret || val > 1) + return -EINVAL; + +- set_boost(val); ++ get_online_cpus(); ++ set_boost(policy, val); ++ put_online_cpus(); + + return count; + } +diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c +index 99ca9c50a88f..49ed22b45fb7 100644 +--- a/drivers/cpufreq/cpufreq.c ++++ b/drivers/cpufreq/cpufreq.c +@@ -2347,34 +2347,32 @@ EXPORT_SYMBOL(cpufreq_update_policy); + /********************************************************************* + * BOOST * + *********************************************************************/ +-static int cpufreq_boost_set_sw(int state) ++static int cpufreq_boost_set_sw(struct cpufreq_policy *policy, int state) + { +- struct cpufreq_policy *policy; + int ret = -EINVAL; + +- for_each_active_policy(policy) { +- if (!policy->freq_table) +- continue; +- +- ret = cpufreq_frequency_table_cpuinfo(policy, +- policy->freq_table); +- if (ret) { +- pr_err("%s: Policy frequency update failed\n", +- __func__); +- break; +- } ++ if (!policy->freq_table) ++ return -ENXIO; + +- down_write(&policy->rwsem); +- policy->user_policy.max = policy->max; +- cpufreq_governor_limits(policy); +- up_write(&policy->rwsem); ++ ret = cpufreq_frequency_table_cpuinfo(policy, ++ policy->freq_table); ++ if (ret) { ++ pr_err("%s: Policy frequency update failed\n", ++ __func__); ++ return ret; + } + ++ down_write(&policy->rwsem); ++ policy->user_policy.max = policy->max; ++ cpufreq_governor_limits(policy); ++ up_write(&policy->rwsem); ++ + return ret; + } + + int cpufreq_boost_trigger_state(int state) + { ++ struct cpufreq_policy *policy; + unsigned long flags; + int ret = 0; + +@@ -2385,15 +2383,25 @@ int cpufreq_boost_trigger_state(int state) + cpufreq_driver->boost_enabled = state; + write_unlock_irqrestore(&cpufreq_driver_lock, flags); + +- ret = cpufreq_driver->set_boost(state); +- if (ret) { +- write_lock_irqsave(&cpufreq_driver_lock, flags); +- cpufreq_driver->boost_enabled = !state; +- write_unlock_irqrestore(&cpufreq_driver_lock, flags); +- +- pr_err("%s: Cannot %s BOOST\n", +- __func__, state ? "enable" : "disable"); ++ get_online_cpus(); ++ for_each_active_policy(policy) { ++ ret = cpufreq_driver->set_boost(policy, state); ++ if (ret) ++ goto err_reset_state; + } ++ put_online_cpus(); ++ ++ return 0; ++ ++err_reset_state: ++ put_online_cpus(); ++ ++ write_lock_irqsave(&cpufreq_driver_lock, flags); ++ cpufreq_driver->boost_enabled = !state; ++ write_unlock_irqrestore(&cpufreq_driver_lock, flags); ++ ++ pr_err("%s: Cannot %s BOOST\n", ++ __func__, state ? "enable" : "disable"); + + return ret; + } +diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h +index 3361663144a1..ff6b10552c86 100644 +--- a/include/linux/cpufreq.h ++++ b/include/linux/cpufreq.h +@@ -334,7 +334,7 @@ struct cpufreq_driver { + + /* platform specific boost support code */ + bool boost_enabled; +- int (*set_boost)(int state); ++ int (*set_boost)(struct cpufreq_policy *policy, int state); + }; + + /* flags */ +-- +2.25.1 + diff --git a/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch b/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch new file mode 100644 index 000000000000..a8dfe4af2621 --- /dev/null +++ b/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch @@ -0,0 +1,142 @@ +From 5cca93b9a9e4690a8491f6fde455ff0268f1e92a Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:31 +0800 +Subject: [PATCH openEuler-1.0-LTS 2/2] cpufreq: CPPC: add SW BOOST support + +mainline inclusion +from mainline-v5.8-rc1 +commit 54e74df5d76dea824c7c0c9d1b97150bf9b33793 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +To add SW BOOST support for CPPC, we need to get the max frequency of +boost mode and non-boost mode. ACPI spec 6.2 section 8.4.7.1 describes +the following two CPC registers. + +"Highest performance is the absolute maximum performance an individual +processor may reach, assuming ideal conditions. This performance level +may not be sustainable for long durations, and may only be achievable if +other platform components are in a specific state; for example, it may +require other processors be in an idle state. + +Nominal Performance is the maximum sustained performance level of the +processor, assuming ideal operating conditions. In absence of an +external constraint (power, thermal, etc.) this is the performance level +the platform is expected to be able to maintain continuously. All +processors are expected to be able to sustain their nominal performance +state simultaneously." + +To add SW BOOST support for CPPC, we can use Highest Performance as the +max performance in boost mode and Nominal Performance as the max +performance in non-boost mode. If the Highest Performance is greater +than the Nominal Performance, we assume SW BOOST is supported. + +The current CPPC driver does not support SW BOOST and use 'Highest +Performance' as the max performance the CPU can achieve. 'Nominal +Performance' is used to convert 'performance' to 'frequency'. That +means, if firmware enable boost and provide a value for Highest +Performance which is greater than Nominal Performance, boost feature is +enabled by default. + +Because SW BOOST is disabled by default, so, after this patch, boost +feature is disabled by default even if boost is enabled by firmware. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/cppc_cpufreq.c | 35 ++++++++++++++++++++++++++++++++-- + 1 file changed, 33 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c +index 0a245f1caa95..15cffca10f1a 100644 +--- a/drivers/cpufreq/cppc_cpufreq.c ++++ b/drivers/cpufreq/cppc_cpufreq.c +@@ -41,6 +41,7 @@ + * requested etc. + */ + static struct cppc_cpudata **all_cpu_data; ++static bool boost_supported; + + struct cppc_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +@@ -314,7 +315,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * Section 8.4.7.1.1.5 of ACPI 6.1 spec) + */ + policy->min = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_nonlinear_perf); +- policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + /* + * Set cpuinfo.min_freq to Lowest to make the full range of performance +@@ -322,7 +323,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * nonlinear perf + */ + policy->cpuinfo.min_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_perf); +- policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num); + policy->shared_type = cpu->shared_type; +@@ -347,6 +348,13 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + + cpu->cur_policy = policy; + ++ /* ++ * If 'highest_perf' is greater than 'nominal_perf', we assume CPU Boost ++ * is supported. ++ */ ++ if (cpu->perf_caps.highest_perf > cpu->perf_caps.nominal_perf) ++ boost_supported = true; ++ + /* Set policy->cur to max now. The governors will adjust later. */ + policy->cur = cppc_cpufreq_perf_to_khz(cpu, + cpu->perf_caps.highest_perf); +@@ -414,6 +422,28 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpunum) + return cppc_get_rate_from_fbctrs(cpu, fb_ctrs_t0, fb_ctrs_t1); + } + ++static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state) ++{ ++ struct cppc_cpudata *cpudata; ++ int ret; ++ ++ if (!boost_supported) { ++ pr_err("BOOST not supported by CPU or firmware\n"); ++ return -EINVAL; ++ } ++ ++ cpudata = all_cpu_data[policy->cpu]; ++ if (state) ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.highest_perf); ++ else ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.nominal_perf); ++ policy->cpuinfo.max_freq = policy->max; ++ ++ return 0; ++} ++ + static struct cpufreq_driver cppc_cpufreq_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = cppc_verify_policy, +@@ -421,6 +451,7 @@ static struct cpufreq_driver cppc_cpufreq_driver = { + .get = cppc_cpufreq_get_rate, + .init = cppc_cpufreq_cpu_init, + .stop_cpu = cppc_cpufreq_stop_cpu, ++ .set_boost = cppc_cpufreq_set_boost, + .name = "cppc_cpufreq", + }; + +-- +2.25.1 + diff --git a/series.conf b/series.conf index d78c29dea2e9..35aef9d23d6c 100644 --- a/series.conf +++ b/series.conf @@ -362,3 +362,5 @@ patches/0358-spi-hisi-sfc-v3xx-add-address-mode-check.patch patches/0359-spi-hisi-sfc-v3xx-fix-potential-irq-race-condition.patch patches/0360-spi-hisi-sfc-v3xx-drop-unnecessary-ACPI_PTR-and-rela.patch patches/0361-config-arm64-Build-HiSilicon-SPI-SFC-driver-as-modul.patch +patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch +patches/0363--cpufreq-CPPC-add-SW-BOOST-support.patch -- 2.25.1

2 1

[PATCH openEuler-20.03-LTS-SP4] support CPU turbo feature
by Yu Liao 16 Nov '23

16 Nov '23

Backport the following patches: cpufreq: change '.set_boost' to act on one policy cpufreq: CPPC: add SW BOOST support --- kernel.spec | 5 +- ...ange-.set_boost-to-act-on-one-policy.patch | 186 ++++++++++++++++++ ...63-cpufreq-CPPC-add-SW-BOOST-support.patch | 142 +++++++++++++ series.conf | 2 + 4 files changed, 334 insertions(+), 1 deletion(-) create mode 100644 patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch create mode 100644 patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch diff --git a/kernel.spec b/kernel.spec index 39fc740d35f6..afb398809fbb 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0244 +Release: %{hulkrelease}.0245 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -850,6 +850,9 @@ fi %changelog +* Thu Nov 16 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2311.3.0.0245 +- Backport cpu turbo patches + * Wed Nov 15 2023 Luo Shengwei <luoshengwei(a)huawei.com> - 4.19.90-2311.3.0.0244 - !2803 drivers/gmjstcm: fix a dev_err() call in spi tcm device probe - !2841 drm/qxl: fix UAF on handle creation diff --git a/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch b/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch new file mode 100644 index 000000000000..83a5195807bb --- /dev/null +++ b/patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch @@ -0,0 +1,186 @@ +From a93e5e087b753c9fe954e4a82ae1224ba56732d0 Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:30 +0800 +Subject: [PATCH openEuler-1.0-LTS 1/2] cpufreq: change '.set_boost' to act on + one policy + +mainline inclusion +from mainline-v5.8-rc1 +commit cf6fada71543ceea0f6228ffdc0b85778f3f5a6e +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +Macro 'for_each_active_policy()' is defined internally. To avoid some +cpufreq driver needing this macro to iterate over all the policies in +'.set_boost' callback, we redefine '.set_boost' to act on only one +policy and pass the policy as an argument. + +'cpufreq_boost_trigger_state()' iterates over all the policies to set +boost for the system. + +This is preparation for adding SW BOOST support for CPPC. + +To protect Boost enable/disable by sysfs from CPU online/offline, +add 'cpu_hotplug_lock' before calling '.set_boost' for each CPU. + +Also move the lock from 'set_boost()' to 'store_cpb()' in +acpi_cpufreq. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject & changelog ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> + +Conflicts: + drivers/cpufreq/cpufreq.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/acpi-cpufreq.c | 14 ++++---- + drivers/cpufreq/cpufreq.c | 58 +++++++++++++++++++--------------- + include/linux/cpufreq.h | 2 +- + 3 files changed, 42 insertions(+), 32 deletions(-) + +diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c +index ce0a51849f66..189c7c9e2641 100644 +--- a/drivers/cpufreq/acpi-cpufreq.c ++++ b/drivers/cpufreq/acpi-cpufreq.c +@@ -147,12 +147,12 @@ static void boost_set_msr_each(void *p_en) + boost_set_msr(enable); + } + +-static int set_boost(int val) ++static int set_boost(struct cpufreq_policy *policy, int val) + { +- get_online_cpus(); +- on_each_cpu(boost_set_msr_each, (void *)(long)val, 1); +- put_online_cpus(); +- pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); ++ on_each_cpu_mask(policy->cpus, boost_set_msr_each, ++ (void *)(long)val, 1); ++ pr_debug("CPU %*pbl: Core Boosting %sabled.\n", ++ cpumask_pr_args(policy->cpus), val ? "en" : "dis"); + + return 0; + } +@@ -183,7 +183,9 @@ static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, + if (ret || val > 1) + return -EINVAL; + +- set_boost(val); ++ get_online_cpus(); ++ set_boost(policy, val); ++ put_online_cpus(); + + return count; + } +diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c +index 99ca9c50a88f..49ed22b45fb7 100644 +--- a/drivers/cpufreq/cpufreq.c ++++ b/drivers/cpufreq/cpufreq.c +@@ -2347,34 +2347,32 @@ EXPORT_SYMBOL(cpufreq_update_policy); + /********************************************************************* + * BOOST * + *********************************************************************/ +-static int cpufreq_boost_set_sw(int state) ++static int cpufreq_boost_set_sw(struct cpufreq_policy *policy, int state) + { +- struct cpufreq_policy *policy; + int ret = -EINVAL; + +- for_each_active_policy(policy) { +- if (!policy->freq_table) +- continue; +- +- ret = cpufreq_frequency_table_cpuinfo(policy, +- policy->freq_table); +- if (ret) { +- pr_err("%s: Policy frequency update failed\n", +- __func__); +- break; +- } ++ if (!policy->freq_table) ++ return -ENXIO; + +- down_write(&policy->rwsem); +- policy->user_policy.max = policy->max; +- cpufreq_governor_limits(policy); +- up_write(&policy->rwsem); ++ ret = cpufreq_frequency_table_cpuinfo(policy, ++ policy->freq_table); ++ if (ret) { ++ pr_err("%s: Policy frequency update failed\n", ++ __func__); ++ return ret; + } + ++ down_write(&policy->rwsem); ++ policy->user_policy.max = policy->max; ++ cpufreq_governor_limits(policy); ++ up_write(&policy->rwsem); ++ + return ret; + } + + int cpufreq_boost_trigger_state(int state) + { ++ struct cpufreq_policy *policy; + unsigned long flags; + int ret = 0; + +@@ -2385,15 +2383,25 @@ int cpufreq_boost_trigger_state(int state) + cpufreq_driver->boost_enabled = state; + write_unlock_irqrestore(&cpufreq_driver_lock, flags); + +- ret = cpufreq_driver->set_boost(state); +- if (ret) { +- write_lock_irqsave(&cpufreq_driver_lock, flags); +- cpufreq_driver->boost_enabled = !state; +- write_unlock_irqrestore(&cpufreq_driver_lock, flags); +- +- pr_err("%s: Cannot %s BOOST\n", +- __func__, state ? "enable" : "disable"); ++ get_online_cpus(); ++ for_each_active_policy(policy) { ++ ret = cpufreq_driver->set_boost(policy, state); ++ if (ret) ++ goto err_reset_state; + } ++ put_online_cpus(); ++ ++ return 0; ++ ++err_reset_state: ++ put_online_cpus(); ++ ++ write_lock_irqsave(&cpufreq_driver_lock, flags); ++ cpufreq_driver->boost_enabled = !state; ++ write_unlock_irqrestore(&cpufreq_driver_lock, flags); ++ ++ pr_err("%s: Cannot %s BOOST\n", ++ __func__, state ? "enable" : "disable"); + + return ret; + } +diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h +index 3361663144a1..ff6b10552c86 100644 +--- a/include/linux/cpufreq.h ++++ b/include/linux/cpufreq.h +@@ -334,7 +334,7 @@ struct cpufreq_driver { + + /* platform specific boost support code */ + bool boost_enabled; +- int (*set_boost)(int state); ++ int (*set_boost)(struct cpufreq_policy *policy, int state); + }; + + /* flags */ +-- +2.25.1 + diff --git a/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch b/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch new file mode 100644 index 000000000000..a8dfe4af2621 --- /dev/null +++ b/patches/0363-cpufreq-CPPC-add-SW-BOOST-support.patch @@ -0,0 +1,142 @@ +From 5cca93b9a9e4690a8491f6fde455ff0268f1e92a Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Date: Sat, 30 May 2020 10:08:31 +0800 +Subject: [PATCH openEuler-1.0-LTS 2/2] cpufreq: CPPC: add SW BOOST support + +mainline inclusion +from mainline-v5.8-rc1 +commit 54e74df5d76dea824c7c0c9d1b97150bf9b33793 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I88RXU +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +To add SW BOOST support for CPPC, we need to get the max frequency of +boost mode and non-boost mode. ACPI spec 6.2 section 8.4.7.1 describes +the following two CPC registers. + +"Highest performance is the absolute maximum performance an individual +processor may reach, assuming ideal conditions. This performance level +may not be sustainable for long durations, and may only be achievable if +other platform components are in a specific state; for example, it may +require other processors be in an idle state. + +Nominal Performance is the maximum sustained performance level of the +processor, assuming ideal operating conditions. In absence of an +external constraint (power, thermal, etc.) this is the performance level +the platform is expected to be able to maintain continuously. All +processors are expected to be able to sustain their nominal performance +state simultaneously." + +To add SW BOOST support for CPPC, we can use Highest Performance as the +max performance in boost mode and Nominal Performance as the max +performance in non-boost mode. If the Highest Performance is greater +than the Nominal Performance, we assume SW BOOST is supported. + +The current CPPC driver does not support SW BOOST and use 'Highest +Performance' as the max performance the CPU can achieve. 'Nominal +Performance' is used to convert 'performance' to 'frequency'. That +means, if firmware enable boost and provide a value for Highest +Performance which is greater than Nominal Performance, boost feature is +enabled by default. + +Because SW BOOST is disabled by default, so, after this patch, boost +feature is disabled by default even if boost is enabled by firmware. + +Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> +Suggested-by: Viresh Kumar <viresh.kumar(a)linaro.org> +Acked-by: Viresh Kumar <viresh.kumar(a)linaro.org> +[ rjw: Subject ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/cpufreq/cppc_cpufreq.c | 35 ++++++++++++++++++++++++++++++++-- + 1 file changed, 33 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c +index 0a245f1caa95..15cffca10f1a 100644 +--- a/drivers/cpufreq/cppc_cpufreq.c ++++ b/drivers/cpufreq/cppc_cpufreq.c +@@ -41,6 +41,7 @@ + * requested etc. + */ + static struct cppc_cpudata **all_cpu_data; ++static bool boost_supported; + + struct cppc_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +@@ -314,7 +315,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * Section 8.4.7.1.1.5 of ACPI 6.1 spec) + */ + policy->min = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_nonlinear_perf); +- policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + /* + * Set cpuinfo.min_freq to Lowest to make the full range of performance +@@ -322,7 +323,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + * nonlinear perf + */ + policy->cpuinfo.min_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_perf); +- policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.highest_perf); ++ policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf); + + policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num); + policy->shared_type = cpu->shared_type; +@@ -347,6 +348,13 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) + + cpu->cur_policy = policy; + ++ /* ++ * If 'highest_perf' is greater than 'nominal_perf', we assume CPU Boost ++ * is supported. ++ */ ++ if (cpu->perf_caps.highest_perf > cpu->perf_caps.nominal_perf) ++ boost_supported = true; ++ + /* Set policy->cur to max now. The governors will adjust later. */ + policy->cur = cppc_cpufreq_perf_to_khz(cpu, + cpu->perf_caps.highest_perf); +@@ -414,6 +422,28 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpunum) + return cppc_get_rate_from_fbctrs(cpu, fb_ctrs_t0, fb_ctrs_t1); + } + ++static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state) ++{ ++ struct cppc_cpudata *cpudata; ++ int ret; ++ ++ if (!boost_supported) { ++ pr_err("BOOST not supported by CPU or firmware\n"); ++ return -EINVAL; ++ } ++ ++ cpudata = all_cpu_data[policy->cpu]; ++ if (state) ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.highest_perf); ++ else ++ policy->max = cppc_cpufreq_perf_to_khz(cpudata, ++ cpudata->perf_caps.nominal_perf); ++ policy->cpuinfo.max_freq = policy->max; ++ ++ return 0; ++} ++ + static struct cpufreq_driver cppc_cpufreq_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = cppc_verify_policy, +@@ -421,6 +451,7 @@ static struct cpufreq_driver cppc_cpufreq_driver = { + .get = cppc_cpufreq_get_rate, + .init = cppc_cpufreq_cpu_init, + .stop_cpu = cppc_cpufreq_stop_cpu, ++ .set_boost = cppc_cpufreq_set_boost, + .name = "cppc_cpufreq", + }; + +-- +2.25.1 + diff --git a/series.conf b/series.conf index d78c29dea2e9..35aef9d23d6c 100644 --- a/series.conf +++ b/series.conf @@ -362,3 +362,5 @@ patches/0358-spi-hisi-sfc-v3xx-add-address-mode-check.patch patches/0359-spi-hisi-sfc-v3xx-fix-potential-irq-race-condition.patch patches/0360-spi-hisi-sfc-v3xx-drop-unnecessary-ACPI_PTR-and-rela.patch patches/0361-config-arm64-Build-HiSilicon-SPI-SFC-driver-as-modul.patch +patches/0362-cpufreq-change-.set_boost-to-act-on-one-policy.patch +patches/0363--cpufreq-CPPC-add-SW-BOOST-support.patch -- 2.25.1

1 0

[PATCH openEuler-20.03-LTS-SP4] MPAM: support ACPI for MPAM 2.0
by Yu Liao 10 Nov '23

10 Nov '23

Containing the following patches: ACPI/MPAM: Adapt to Arm's MPAM ACPI table version 2 ACPI / PPTT: Find PPTT processor node by cache id ACPICA: ACPI 6.4: PPTT: add new version of subtable type 1 ACPICA: Add support for Arm's MPAM ACPI table version 2 --- kernel.spec | 6 +- ...rt-for-Arm-s-MPAM-ACPI-table-version.patch | 166 ++++++++++ ...PPTT-add-new-version-of-subtable-typ.patch | 65 ++++ ...Find-PPTT-processor-node-by-cache-id.patch | 114 +++++++ ...t-to-Arm-s-MPAM-ACPI-table-version-2.patch | 302 ++++++++++++++++++ series.conf | 4 + 6 files changed, 656 insertions(+), 1 deletion(-) create mode 100644 patches/0118-ACPICA-Add-support-for-Arm-s-MPAM-ACPI-table-version.patch create mode 100644 patches/0119-ACPICA-ACPI-6.4-PPTT-add-new-version-of-subtable-typ.patch create mode 100644 patches/0120-ACPI-PPTT-Find-PPTT-processor-node-by-cache-id.patch create mode 100644 patches/0121-ACPI-MPAM-Adapt-to-Arm-s-MPAM-ACPI-table-version-2.patch diff --git a/kernel.spec b/kernel.spec index c359e305adcb..31c70083ef82 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0238 +Release: %{hulkrelease}.0239 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -836,6 +836,10 @@ fi %endif %changelog + +* Fri Nov 10 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2311.1.0.0239 +- mpam: support ACPI for MPAM 2.0 + * Thu Nov 9 2023 Kunkun Jiang <jiangkunkun(a)huawei.com> - 4.19.90-2311.1.0.0238 - scsi: virtio_scsi: limit number of hw queues by nr_cpu_ids diff --git a/patches/0118-ACPICA-Add-support-for-Arm-s-MPAM-ACPI-table-version.patch b/patches/0118-ACPICA-Add-support-for-Arm-s-MPAM-ACPI-table-version.patch new file mode 100644 index 000000000000..9986d73ca082 --- /dev/null +++ b/patches/0118-ACPICA-Add-support-for-Arm-s-MPAM-ACPI-table-version.patch @@ -0,0 +1,166 @@ +From fbd9895d29825eeea4d958e41a9974534baa8a6c Mon Sep 17 00:00:00 2001 +From: Hesham Almatary <hesham.almatary(a)huawei.com> +Date: Fri, 9 Jun 2023 13:06:49 +0800 +Subject: [PATCH openEuler-20.03-LTS-SP4 1/4] ACPICA: Add support for Arm's MPAM ACPI + table version 2 + +mainline inclusion +from mainline-v6.4-rc1 +commit 47920aae34e295f4ffbeac0b10698ceda52eec99 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I77UDW +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +ACPICA commit 005e24bcaa6e4c7db327b4f81fb63b2715aac7e6 + +Complies with ACPI for Memory System Resource Partitioning and +Monitoring 2.0 [1]. Document number: DEN0065, as of December 2022. + +Support for all types of MPAM resources. No support yet for: +1) MPAM PCC Interface Type +2) The optional Resource-specific data per MSC node, introduced in v2 of the +MPAM ACPI spec. + +[1] https://developer.arm.com/documentation/den0065/latest + +Link: https://github.com/acpica/acpica/commit/005e24bc +Signed-off-by: Hesham Almatary <hesham.almatary(a)huawei.com> +Signed-off-by: Bob Moore <robert.moore(a)intel.com> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> + +Conflicts: + include/acpi/actbl2.h +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + include/acpi/actbl2.h | 111 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 111 insertions(+) + +diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h +index 476d0f6188c6..38325bd24231 100644 +--- a/include/acpi/actbl2.h ++++ b/include/acpi/actbl2.h +@@ -964,6 +964,117 @@ struct acpi_mpam_node_memory { + u8 reserved1[3]; + }; + ++/******************************************************************************* ++ * ++ * MPAM - Memory System Resource Partitioning and Monitoring ++ * ++ * Conforms to "ACPI for Memory System Resource Partitioning and Monitoring 2.0" ++ * Document number: ARM DEN 0065, December, 2022. ++ * ++ ******************************************************************************/ ++ ++/* MPAM RIS locator types. Table 11, Location types */ ++enum acpi_mpam_locator_type { ++ ACPI_MPAM_LOCATION_TYPE_PROCESSOR_CACHE = 0, ++ ACPI_MPAM_LOCATION_TYPE_MEMORY = 1, ++ ACPI_MPAM_LOCATION_TYPE_SMMU = 2, ++ ACPI_MPAM_LOCATION_TYPE_MEMORY_CACHE = 3, ++ ACPI_MPAM_LOCATION_TYPE_ACPI_DEVICE = 4, ++ ACPI_MPAM_LOCATION_TYPE_INTERCONNECT = 5, ++ ACPI_MPAM_LOCATION_TYPE_UNKNOWN = 0xFF ++}; ++ ++/* MPAM Functional dependency descriptor. Table 10 */ ++struct acpi_mpam_func_deps { ++ u32 producer; ++ u32 reserved; ++}; ++ ++/* MPAM Processor cache locator descriptor. Table 13 */ ++struct acpi_mpam_resource_cache_locator { ++ u64 cache_reference; ++ u32 reserved; ++}; ++ ++/* MPAM Memory locator descriptor. Table 14 */ ++struct acpi_mpam_resource_memory_locator { ++ u64 proximity_domain; ++ u32 reserved; ++}; ++ ++/* MPAM SMMU locator descriptor. Table 15 */ ++struct acpi_mpam_resource_smmu_locator { ++ u64 smmu_interface; ++ u32 reserved; ++}; ++ ++/* MPAM Memory-side cache locator descriptor. Table 16 */ ++struct acpi_mpam_resource_memcache_locator { ++ u8 reserved[7]; ++ u8 level; ++ u32 reference; ++}; ++ ++/* MPAM ACPI device locator descriptor. Table 17 */ ++struct acpi_mpam_resource_acpi_locator { ++ u64 acpi_hw_id; ++ u32 acpi_unique_id; ++}; ++ ++/* MPAM Interconnect locator descriptor. Table 18 */ ++struct acpi_mpam_resource_interconnect_locator { ++ u64 inter_connect_desc_tbl_off; ++ u32 reserved; ++}; ++ ++/* MPAM Locator structure. Table 12 */ ++struct acpi_mpam_resource_generic_locator { ++ u64 descriptor1; ++ u32 descriptor2; ++}; ++ ++union acpi_mpam_resource_locator { ++ struct acpi_mpam_resource_cache_locator cache_locator; ++ struct acpi_mpam_resource_memory_locator memory_locator; ++ struct acpi_mpam_resource_smmu_locator smmu_locator; ++ struct acpi_mpam_resource_memcache_locator mem_cache_locator; ++ struct acpi_mpam_resource_acpi_locator acpi_locator; ++ struct acpi_mpam_resource_interconnect_locator interconnect_ifc_locator; ++ struct acpi_mpam_resource_generic_locator generic_locator; ++}; ++ ++/* Memory System Component Resource Node Structure Table 9 */ ++struct acpi_mpam_resource_node { ++ u32 identifier; ++ u8 ris_index; ++ u16 reserved1; ++ u8 locator_type; ++ union acpi_mpam_resource_locator locator; ++ u32 num_functional_deps; ++}; ++ ++/* Memory System Component (MSC) Node Structure. Table 4 */ ++struct acpi_mpam_msc_node { ++ u16 length; ++ u8 interface_type; ++ u8 reserved; ++ u32 identifier; ++ u64 base_address; ++ u32 mmio_size; ++ u32 overflow_interrupt; ++ u32 overflow_interrupt_flags; ++ u32 reserved1; ++ u32 overflow_interrupt_affinity; ++ u32 error_interrupt; ++ u32 error_interrupt_flags; ++ u32 reserved2; ++ u32 error_interrupt_affinity; ++ u32 max_nrdy_usec; ++ u64 hardware_id_linked_device; ++ u32 instance_id_linked_device; ++ u32 num_resouce_nodes; ++}; ++ + /******************************************************************************* + * + * MSDM - Microsoft Data Management table +-- +2.25.1 + diff --git a/patches/0119-ACPICA-ACPI-6.4-PPTT-add-new-version-of-subtable-typ.patch b/patches/0119-ACPICA-ACPI-6.4-PPTT-add-new-version-of-subtable-typ.patch new file mode 100644 index 000000000000..e5b6f51c5892 --- /dev/null +++ b/patches/0119-ACPICA-ACPI-6.4-PPTT-add-new-version-of-subtable-typ.patch @@ -0,0 +1,65 @@ +From 3cab8977d9a1456204cc629bbae1572c583a91fb Mon Sep 17 00:00:00 2001 +From: Erik Kaneda <erik.kaneda(a)intel.com> +Date: Fri, 9 Jun 2023 13:06:50 +0800 +Subject: [PATCH openEuler-20.03-LTS-SP4 2/4] ACPICA: ACPI 6.4: PPTT: add new version + of subtable type 1 + +mainline inclusion +from mainline-v5.13-rc1 +commit 5e2e86c0b9970e6f70869e76a1c6417036fd3a7e +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I77UDW +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +This commit squashes the following: + +ACPICA commit 475c5e89f8f701ccdfee6ca567e33c854ecd6c9e +ACPICA commit 82cf78ac175a4b7d8842c5b786be24031c817cfd + +This new subtable is only valid for PPTT version 3. + +Elyes fixed a misspelled identifier in this commit. + +Link: https://github.com/acpica/acpica/commit/475c5e89 +Link: https://github.com/acpica/acpica/commit/82cf78ac +Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> +Signed-off-by: Erik Kaneda <erik.kaneda(a)intel.com> +Signed-off-by: Bob Moore <robert.moore(a)intel.com> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki(a)intel.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + include/acpi/actbl2.h | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h +index 38325bd24231..d95852c1708f 100644 +--- a/include/acpi/actbl2.h ++++ b/include/acpi/actbl2.h +@@ -1664,6 +1664,12 @@ struct acpi_pptt_cache { + u16 line_size; + }; + ++/* 1: Cache Type Structure for PPTT version 3 */ ++ ++struct acpi_pptt_cache_v1 { ++ u32 cache_id; ++}; ++ + /* Flags */ + + #define ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */ +@@ -1673,6 +1679,7 @@ struct acpi_pptt_cache { + #define ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */ + #define ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */ + #define ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */ ++#define ACPI_PPTT_CACHE_ID_VALID (1<<7) /* Cache ID valid */ + + /* Masks for Attributes */ + +-- +2.25.1 + diff --git a/patches/0120-ACPI-PPTT-Find-PPTT-processor-node-by-cache-id.patch b/patches/0120-ACPI-PPTT-Find-PPTT-processor-node-by-cache-id.patch new file mode 100644 index 000000000000..7c8b81358dd8 --- /dev/null +++ b/patches/0120-ACPI-PPTT-Find-PPTT-processor-node-by-cache-id.patch @@ -0,0 +1,114 @@ +From c76f178feff20fcbda0dba4a72418f310d65f61b Mon Sep 17 00:00:00 2001 +From: Yu Liao <liaoyu15(a)huawei.com> +Date: Fri, 9 Jun 2023 13:06:51 +0800 +Subject: [PATCH openEuler-20.03-LTS-SP4 3/4] ACPI / PPTT: Find PPTT processor node + by cache id + +openeuler inclusion +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I77UDW +CVE: NA + +-------------------------------- + +The MPAM table identifies caches by id, but the driver also wants to know +the processor node. + +Add a helper that walks every possible cache, until it finds the one +identified by id, then return processor node. + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + drivers/acpi/pptt.c | 55 ++++++++++++++++++++++++++++++++++++++++++++ + include/linux/acpi.h | 5 ++++ + 2 files changed, 60 insertions(+) + +diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c +index 879b9155b7b4..74ce9fcee830 100644 +--- a/drivers/acpi/pptt.c ++++ b/drivers/acpi/pptt.c +@@ -896,3 +896,58 @@ int find_acpi_cpu_topology_hetero_id(unsigned int cpu) + return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE, + ACPI_PPTT_ACPI_IDENTICAL); + } ++ ++struct acpi_pptt_processor *find_acpi_processor_node_from_cache_id(u32 cache_id) ++{ ++ u32 acpi_cpu_id; ++ acpi_status status; ++ int level, cpu, num_levels; ++ struct acpi_pptt_cache *cache; ++ struct acpi_table_header *table; ++ struct acpi_pptt_cache_v1 *cache_v1; ++ struct acpi_pptt_processor *cpu_node; ++ ++ status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); ++ if (ACPI_FAILURE(status)) { ++ pr_warn_once("No PPTT table found, cache topology may be inaccurate\n"); ++ return NULL; ++ } ++ ++ if (table->revision < 3) { ++ acpi_put_table(table); ++ return NULL; ++ } ++ ++ /* ++ * If we found the cache first, we'd still need to walk from each CPU ++ * to find the level... ++ */ ++ for_each_possible_cpu(cpu) { ++ acpi_cpu_id = get_acpi_id_for_cpu(cpu); ++ cpu_node = acpi_find_processor_node(table, acpi_cpu_id); ++ if (!cpu_node) ++ break; ++ num_levels = acpi_count_levels(table, cpu_node); ++ ++ for (level = 0; level <= num_levels; level++) { ++ cache = acpi_find_cache_node(table, acpi_cpu_id, ++ ACPI_PPTT_CACHE_TYPE_UNIFIED, ++ level, &cpu_node); ++ if (!cache) ++ continue; ++ ++ cache_v1 = ACPI_ADD_PTR(struct acpi_pptt_cache_v1, ++ cache, ++ sizeof(struct acpi_pptt_cache)); ++ ++ if (cache->flags & ACPI_PPTT_CACHE_ID_VALID && ++ cache_v1->cache_id == cache_id) { ++ acpi_put_table(table); ++ return cpu_node; ++ } ++ } ++ } ++ ++ acpi_put_table(table); ++ return NULL; ++} +diff --git a/include/linux/acpi.h b/include/linux/acpi.h +index 4a0142276cb8..3669c2ff26ed 100644 +--- a/include/linux/acpi.h ++++ b/include/linux/acpi.h +@@ -1331,6 +1331,7 @@ int find_acpi_cpu_topology(unsigned int cpu, int level); + int find_acpi_cpu_topology_package(unsigned int cpu); + int find_acpi_cpu_topology_hetero_id(unsigned int cpu); + int find_acpi_cpu_cache_topology(unsigned int cpu, int level); ++struct acpi_pptt_processor *find_acpi_processor_node_from_cache_id(u32 cache_id); + #else + static inline int acpi_pptt_cpu_is_thread(unsigned int cpu) + { +@@ -1352,6 +1353,10 @@ static inline int find_acpi_cpu_cache_topology(unsigned int cpu, int level) + { + return -EINVAL; + } ++static inline struct acpi_pptt_processor *find_acpi_processor_node_from_cache_id(u32 cache_id) ++{ ++ return NULL; ++} + #endif + + struct acpi_pptt_processor * +-- +2.25.1 + diff --git a/patches/0121-ACPI-MPAM-Adapt-to-Arm-s-MPAM-ACPI-table-version-2.patch b/patches/0121-ACPI-MPAM-Adapt-to-Arm-s-MPAM-ACPI-table-version-2.patch new file mode 100644 index 000000000000..ff649474e1f0 --- /dev/null +++ b/patches/0121-ACPI-MPAM-Adapt-to-Arm-s-MPAM-ACPI-table-version-2.patch @@ -0,0 +1,302 @@ +From c366e5ecb88cf89495a82a26274e682fb45631ab Mon Sep 17 00:00:00 2001 +From: Yu Liao <liaoyu15(a)huawei.com> +Date: Fri, 9 Jun 2023 13:06:52 +0800 +Subject: [PATCH openEuler-20.03-LTS-SP4 4/4] ACPI/MPAM: Adapt to Arm's MPAM ACPI + table version 2 + +openeuler inclusion +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I77UDW +CVE: NA + +-------------------------------- + +Support ACPI for MPAM 2.0 [1]. Compatible with MPAM ACPI 1.0 by reading +ACPI revision. + +[1] https://developer.arm.com/documentation/den0065/latest + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + arch/arm64/kernel/mpam/mpam_device.c | 2 +- + drivers/acpi/arm64/Makefile | 2 +- + drivers/acpi/arm64/mpam.c | 21 +++- + drivers/acpi/arm64/mpam_v2.c | 175 +++++++++++++++++++++++++++ + include/linux/arm_mpam.h | 2 +- + 5 files changed, 195 insertions(+), 7 deletions(-) + create mode 100644 drivers/acpi/arm64/mpam_v2.c + +diff --git a/arch/arm64/kernel/mpam/mpam_device.c b/arch/arm64/kernel/mpam/mpam_device.c +index b77cea2673c0..1003716efc09 100644 +--- a/arch/arm64/kernel/mpam/mpam_device.c ++++ b/arch/arm64/kernel/mpam/mpam_device.c +@@ -1873,7 +1873,7 @@ static int __init arm_mpam_driver_init(void) + if (acpi_disabled) + return platform_driver_register(&arm_mpam_driver); + else +- return acpi_mpam_parse(); ++ return acpi_mpam_parse_version(); + } + + /* +diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile +index 81408ce40506..4ba0486dac6b 100644 +--- a/drivers/acpi/arm64/Makefile ++++ b/drivers/acpi/arm64/Makefile +@@ -1,3 +1,3 @@ + obj-$(CONFIG_ACPI_IORT) += iort.o + obj-$(CONFIG_ACPI_GTDT) += gtdt.o +-obj-$(CONFIG_ACPI_MPAM) += mpam.o ++obj-$(CONFIG_ACPI_MPAM) += mpam.o mpam_v2.o +diff --git a/drivers/acpi/arm64/mpam.c b/drivers/acpi/arm64/mpam.c +index 6f4572193eb2..7b92cab79cf1 100644 +--- a/drivers/acpi/arm64/mpam.c ++++ b/drivers/acpi/arm64/mpam.c +@@ -32,6 +32,8 @@ + #include <linux/nodemask.h> + #include <linux/arm_mpam.h> + ++extern int __init acpi_mpam_parse_table_v2(struct acpi_table_header *table, ++ struct acpi_table_header *pptt); + /** + * acpi_mpam_label_cache_component_id() - Recursivly find @min_physid + * for all leaf CPUs below @cpu_node, use numa node id of @min_cpu_node +@@ -40,7 +42,7 @@ + * @cpu_node: The point in the toplogy to start the walk + * @component_id: The id labels the structure mpam_node cache + */ +-static int ++int + acpi_mpam_label_cache_component_id(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node, + u32 *component_id) +@@ -213,11 +215,11 @@ static int __init acpi_mpam_parse_table(struct acpi_table_header *table, + return ret; + } + +-int __init acpi_mpam_parse(void) ++int __init acpi_mpam_parse_version(void) + { + struct acpi_table_header *mpam, *pptt; + acpi_status status; +- int ret; ++ int ret = -EINVAL; + + if (!cpus_have_const_cap(ARM64_HAS_MPAM)) + return 0; +@@ -234,7 +236,18 @@ int __init acpi_mpam_parse(void) + if (ACPI_FAILURE(status)) + pptt = NULL; + +- ret = acpi_mpam_parse_table(mpam, pptt); ++ /* ++ * The BIOS of Kunpeng 920 supports MPAM ACPI 1.0, but the ACPI ++ * revision is wrongly written as 1, so distinguished by ++ * oem_table_id here. ++ */ ++ if (mpam->revision == 0 || strncmp(mpam->oem_table_id, "HIP08", 5) == 0) ++ ret = acpi_mpam_parse_table(mpam, pptt); ++ else if (mpam->revision == 1) ++ ret = acpi_mpam_parse_table_v2(mpam, pptt); ++ else ++ pr_err("unsupported MPAM ACPI version: %u\n", mpam->revision); ++ + acpi_put_table(pptt); + acpi_put_table(mpam); + +diff --git a/drivers/acpi/arm64/mpam_v2.c b/drivers/acpi/arm64/mpam_v2.c +new file mode 100644 +index 000000000000..a3888a5da695 +--- /dev/null ++++ b/drivers/acpi/arm64/mpam_v2.c +@@ -0,0 +1,175 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Common code for ARM v8 MPAM ACPI 2.0 ++ * ++ * Copyright (C) 2019-2022 Huawei Technologies Co., Ltd ++ * ++ * Author: Yu Liao <liaoyu15(a)huawei.com> ++ * ++ * Code was partially borrowed from http://www.linux-arm.org/git?p= ++ * linux-jm.git;a=commit;h=10fe7d6363ae96b25f584d4a91f9d0f2fd5faf3b. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ */ ++ ++/* Parse the MPAM ACPI table feeding the discovered nodes into the driver */ ++#define pr_fmt(fmt) "ACPI MPAM: " fmt ++ ++#include <linux/acpi.h> ++#include <acpi/processor.h> ++#include <linux/cpu.h> ++#include <linux/cpumask.h> ++#include <linux/cacheinfo.h> ++#include <linux/string.h> ++#include <linux/nodemask.h> ++#include <linux/arm_mpam.h> ++ ++extern int ++acpi_mpam_label_cache_component_id(struct acpi_table_header *table_hdr, ++ struct acpi_pptt_processor *cpu_node, ++ u32 *component_id); ++ ++static int __init acpi_mpam_parse_cache_v2(struct acpi_mpam_msc_node *msc, ++ struct acpi_table_header *pptt) ++{ ++ int ret = 0; ++ int level; ++ u32 component_id; ++ struct mpam_device *dev; ++ struct cacheinfo *ci; ++ struct acpi_pptt_processor *pptt_cpu_node; ++ struct acpi_mpam_resource_node *resources; ++ ++ resources = (struct acpi_mpam_resource_node *)(msc + 1); ++ ++ pptt_cpu_node = find_acpi_processor_node_from_cache_id(resources->locator.cache_locator.cache_reference); ++ if (!pptt_cpu_node) { ++ pr_err("Failed to find processor cpu node\n"); ++ return -EINVAL; ++ } ++ ++ ret = acpi_mpam_label_cache_component_id(pptt, pptt_cpu_node, ++ &component_id); ++ if (ret) { ++ pr_err("Failed to label cache component id\n"); ++ return -EINVAL; ++ } ++ ++ cpus_read_lock(); ++ ci = cacheinfo_shared_cpu_map_search(pptt_cpu_node); ++ if (!ci) { ++ pr_err_once("No CPU has cache with PPTT reference %#llx", ++ resources->locator.cache_locator.cache_reference); ++ pr_err_once("All CPUs must be online to probe mpam.\n"); ++ cpus_read_unlock(); ++ return -ENODEV; ++ } ++ ++ level = ci->level; ++ ci = NULL; ++ cpus_read_unlock(); ++ ++ /* ++ * Possible we can get cpu-affinity in next MPAM ACPI version, ++ * now we have to set it to NULL and use default possible_aff- ++ * inity. ++ */ ++ dev = mpam_device_create_cache(level, component_id, NULL, ++ msc->base_address); ++ if (IS_ERR(dev)) { ++ pr_err("Failed to create cache node\n"); ++ return -EINVAL; ++ } ++ ++ return mpam_register_device_irq(dev, ++ msc->overflow_interrupt, msc->overflow_interrupt_flags, ++ msc->error_interrupt, msc->error_interrupt_flags); ++} ++ ++static int __init acpi_mpam_parse_memory_v2(struct acpi_mpam_msc_node *msc) ++{ ++ u32 component_id; ++ struct mpam_device *dev; ++ struct acpi_mpam_resource_node *resources; ++ ++ resources = (struct acpi_mpam_resource_node *)(msc + 1); ++ ++ component_id = acpi_map_pxm_to_node(resources->locator.memory_locator.proximity_domain); ++ if (component_id == NUMA_NO_NODE) ++ component_id = 0; ++ ++ dev = mpam_device_create_memory(component_id, msc->base_address); ++ if (IS_ERR(dev)) { ++ pr_err("Failed to create memory node\n"); ++ return -EINVAL; ++ } ++ ++ return mpam_register_device_irq(dev, ++ msc->overflow_interrupt, msc->overflow_interrupt_flags, ++ msc->error_interrupt, msc->error_interrupt_flags); ++} ++ ++int __init acpi_mpam_parse_table_v2(struct acpi_table_header *table, ++ struct acpi_table_header *pptt) ++{ ++ char *table_offset = (char *)(table + 1); ++ char *table_end = (char *)table + table->length; ++ struct acpi_mpam_msc_node *node_hdr; ++ struct acpi_mpam_resource_node *resources; ++ int ret = 0; ++ ++ ret = mpam_discovery_start(); ++ ++ if (ret) ++ return ret; ++ ++ node_hdr = (struct acpi_mpam_msc_node *)table_offset; ++ resources = (struct acpi_mpam_resource_node *)(node_hdr + 1); ++ ++ while (table_offset < table_end) { ++ switch (resources->locator_type) { ++ ++ case ACPI_MPAM_LOCATION_TYPE_PROCESSOR_CACHE: ++ ret = acpi_mpam_parse_cache_v2(node_hdr, pptt); ++ break; ++ case ACPI_MPAM_LOCATION_TYPE_MEMORY: ++ ret = acpi_mpam_parse_memory_v2(node_hdr); ++ break; ++ default: ++ pr_warn_once("Unknown node type %u offset %ld.", ++ (resources->locator_type), ++ (table_offset-(char *)table)); ++ /* fall through */ ++ case ACPI_MPAM_LOCATION_TYPE_SMMU: ++ /* not yet supported */ ++ /* fall through */ ++ case ACPI_MPAM_TYPE_UNKNOWN: ++ break; ++ } ++ if (ret) ++ break; ++ ++ table_offset += node_hdr->length; ++ node_hdr = (struct acpi_mpam_msc_node *)table_offset; ++ resources = (struct acpi_mpam_resource_node *)(node_hdr + 1); ++ } ++ ++ if (ret) { ++ pr_err("discovery failed: %d\n", ret); ++ mpam_discovery_failed(); ++ } else { ++ ret = mpam_discovery_complete(); ++ if (!ret) ++ pr_info("Successfully init mpam by ACPI.\n"); ++ } ++ ++ return ret; ++} +diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h +index eed95ba06a5d..9bdca6cd3cc9 100644 +--- a/include/linux/arm_mpam.h ++++ b/include/linux/arm_mpam.h +@@ -116,6 +116,6 @@ static inline int mpam_register_device_irq(struct mpam_device *dev, + return ret; + } + +-int __init acpi_mpam_parse(void); ++int __init acpi_mpam_parse_version(void); + + #endif +-- +2.25.1 + diff --git a/series.conf b/series.conf index 44b2f1866829..244389e3d2da 100644 --- a/series.conf +++ b/series.conf @@ -118,3 +118,7 @@ patches/0114-perf-auxtrace-arm64-Add-support-for-HiSilicon-PCIe-T.patch patches/0115-perf-auxtrace-arm64-Add-support-for-parsing-HiSilico.patch patches/0116-Fix-the-header-file-location-error-and-adjust-the-fu.patch patches/0117-scsi-virtio_scsi-limit-number-of-hw-queues-by-nr_cpu.patch +patches/0118-ACPICA-Add-support-for-Arm-s-MPAM-ACPI-table-version.patch +patches/0119-ACPICA-ACPI-6.4-PPTT-add-new-version-of-subtable-typ.patch +patches/0120-ACPI-PPTT-Find-PPTT-processor-node-by-cache-id.patch +patches/0121-ACPI-MPAM-Adapt-to-Arm-s-MPAM-ACPI-table-version-2.patch -- 2.25.1

2 1

[PATCH openEuler-20.03-LTS-SP4] kernel.spec skip check patches that from linux master or stable
by Yu Liao 08 Nov '23

08 Nov '23

--- kernel.spec | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/kernel.spec b/kernel.spec index 21c0951a3151..5f736aaa7464 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0235 +Release: %{hulkrelease}.0236 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -247,6 +247,10 @@ Checkpatches() { set +e while read patch; do + if head -n 10 $PATCH_DIR/$patch | grep -q "mainline inclusion\|stable inclusion"; then + continue + fi + output=$(scripts/checkpatch.pl --ignore $ignores_for_main $PATCH_DIR/$patch) if echo "$output" | grep -q "ERROR:"; then echo "checkpatch $patch failed" @@ -831,6 +835,10 @@ fi %endif %changelog + +* Wed Nov 8 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2311.1.0.0236 +- kernel.spec: skip check patches that from linux master or stable + * Mon Nov 6 2023 YunYi Yang <yangyunyi2(a)huawei.com> - 4.19.90-2311.1.0.0235 - Fix the header file location error and adjust the function and structure version. - perf auxtrace arm64: Add support for parsing HiSilicon PCIe Trace packet -- 2.33.0

2 1

[PATCH openEuler-22.03-LTS-Next] openeuler: add net-acc to kernel-tools
by Liu Jian 07 Nov '23

07 Nov '23

From: "liujian (CE)" <liujian56(a)huawei.com> add net-acc to kernel-tools Signed-off-by: Liu Jian <liujian56(a)huawei.com> --- kernel.spec | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/kernel.spec b/kernel.spec index 658564d..85a0dcf 100644 --- a/kernel.spec +++ b/kernel.spec @@ -12,7 +12,7 @@ %global upstream_sublevel 0 %global devel_release 166 %global maintenance_release .0.0 -%global pkg_release .79 +%global pkg_release .80 %define with_debuginfo 1 # Do not recompute the build-id of vmlinux in find-debuginfo.sh @@ -429,6 +429,9 @@ popd pushd tools/kvm/kvm_stat/ make %{?_smp_mflags} man popd +pushd tools/netacc +make BPFTOOL=../../tools/bpf/bpftool/bpftool +popd %install %if 0%{?with_source} @@ -705,6 +708,9 @@ popd pushd tools/kvm/kvm_stat make INSTALL_ROOT=%{buildroot} install-tools popd +pushd tools/netacc +make INSTALL_ROOT=%{buildroot} install +popd %define __spec_install_post\ %{?__debug_package:%{__debug_install_post}}\ @@ -853,6 +859,8 @@ fi %{_bindir}/gpio-watch %{_mandir}/man1/kvm_stat* %{_bindir}/kvm_stat +%{_sbindir}/net-acc +%{_sbindir}/tuned_acc/netacc %{_libdir}/libcpupower.so.0 %{_libdir}/libcpupower.so.0.0.1 %license linux-%{KernelVer}/COPYING @@ -889,6 +897,9 @@ fi %endif %changelog +* Tue Nov 07 2023 Liu Jian <liujian56(a)huawei.com> - 5.10.0-166.0.0.80 +- And net-acc tool to kernel-tools. + * Thu Nov 02 2023 Jialin Zhang <zhangjialin11(a)huawei.com> - 5.10.0-166.0.0.79 - !2675 RDMA/hns: Support STARS over RDMA - !2688 nvmet-tcp: Fix a possible UAF in queue intialization setup -- 2.34.1

2 1

[PATCH openEuler-20.03-LTS-SP4 v2] Expose SVE2 features for userspace
by Yu Liao 03 Nov '23

03 Nov '23

v1 -> v2: modified patch name --- kernel.spec | 7 +- ...rm64-HWCAP-add-support-for-AT_HWCAP2.patch | 463 ++++++++++++++++++ ...4-Expose-SVE2-features-for-userspace.patch | 275 +++++++++++ ...-Fix-missing-ZFR0-in-__read_sysreg_b.patch | 55 +++ ...-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch | 67 +++ series.conf | 4 + 6 files changed, 870 insertions(+), 1 deletion(-) create mode 100644 patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch create mode 100644 patches/0098-arm64-Expose-SVE2-features-for-userspace.patch create mode 100644 patches/0099-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch create mode 100644 patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch diff --git a/kernel.spec b/kernel.spec index db1c158ac117..3047a91b59bb 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0232 +Release: %{hulkrelease}.0233 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -832,6 +832,11 @@ fi %changelog +* Fri Nov 3 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2310.4.0.0233 +- arm64: HWCAP: add support for AT_HWCAP2 +- arm64: Expose SVE2 features for userspace +- arm64: cpufeature: Fix missing ZFR0 in __read_sysreg_by_encoding() + * Thu Nov 2 2023 hongrongxuan <hongrongxuan(a)huawei.com> - 4.19.90-2311.1.0.0232 - remove linux-kernel-test.patch diff --git a/patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch b/patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch new file mode 100644 index 000000000000..46effba895fb --- /dev/null +++ b/patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch @@ -0,0 +1,463 @@ +From a97497b283894653e53f7eb83b5825f5564d1614 Mon Sep 17 00:00:00 2001 +From: Andrew Murray <andrew.murray(a)arm.com> +Date: Tue, 9 Apr 2019 10:52:40 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 1/4] arm64: HWCAP: add support for + AT_HWCAP2 + +mainline inclusion +from mainline-v5.2-rc1 +commit 06a916feca2b262ab0c1a2aeb68882f4b1108a07 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +As we will exhaust the first 32 bits of AT_HWCAP let's start +exposing AT_HWCAP2 to userspace to give us up to 64 caps. + +Whilst it's possible to use the remaining 32 bits of AT_HWCAP, we +prefer to expand into AT_HWCAP2 in order to provide a consistent +view to userspace between ILP32 and LP64. However internal to the +kernel we prefer to continue to use the full space of elf_hwcap. + +To reduce complexity and allow for future expansion, we now +represent hwcaps in the kernel as ordinals and use a +KERNEL_HWCAP_ prefix. This allows us to support automatic feature +based module loading for all our hwcaps. + +We introduce cpu_set_feature to set hwcaps which complements the +existing cpu_have_feature helper. These helpers allow us to clean +up existing direct uses of elf_hwcap and reduce any future effort +required to move beyond 64 caps. + +For convenience we also introduce cpu_{have,set}_named_feature which +makes use of the cpu_feature macro to allow providing a hwcap name +without a {KERNEL_}HWCAP_ prefix. + +Signed-off-by: Andrew Murray <andrew.murray(a)arm.com> +[will: use const_ilog2() and tweak documentation] +Signed-off-by: Will Deacon <will.deacon(a)arm.com> + +Conflicts: + Documentation/arm64/elf_hwcaps.txt + arch/arm64/crypto/chacha-neon-glue.c + arch/arm64/crypto/crct10dif-ce-glue.c + arch/arm64/crypto/ghash-ce-glue.c + arch/arm64/crypto/nhpoly1305-neon-glue.c + arch/arm64/kernel/cpufeature.c + drivers/clocksource/arm_arch_timer.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + Documentation/arm64/elf_hwcaps.txt | 13 ++++-- + arch/arm64/crypto/aes-ce-ccm-glue.c | 2 +- + arch/arm64/crypto/aes-neonbs-glue.c | 2 +- + arch/arm64/crypto/chacha20-neon-glue.c | 2 +- + arch/arm64/crypto/ghash-ce-glue.c | 6 +-- + arch/arm64/crypto/sha256-glue.c | 4 +- + arch/arm64/include/asm/cpufeature.h | 22 +++++----- + arch/arm64/include/asm/hwcap.h | 49 ++++++++++++++++++++- + arch/arm64/include/uapi/asm/hwcap.h | 2 +- + arch/arm64/kernel/cpufeature.c | 60 +++++++++++++------------- + arch/arm64/kernel/cpuinfo.c | 2 +- + arch/arm64/kernel/fpsimd.c | 4 +- + drivers/clocksource/arm_arch_timer.c | 8 ++++ + 13 files changed, 120 insertions(+), 56 deletions(-) + +diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt +index 6feaffe90e22..186feb16e2f2 100644 +--- a/Documentation/arm64/elf_hwcaps.txt ++++ b/Documentation/arm64/elf_hwcaps.txt +@@ -13,9 +13,9 @@ architected discovery mechanism available to userspace code at EL0. The + kernel exposes the presence of these features to userspace through a set + of flags called hwcaps, exposed in the auxilliary vector. + +-Userspace software can test for features by acquiring the AT_HWCAP entry +-of the auxilliary vector, and testing whether the relevant flags are +-set, e.g. ++Userspace software can test for features by acquiring the AT_HWCAP or ++AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant ++flags are set, e.g. + + bool floating_point_is_present(void) + { +@@ -182,3 +182,10 @@ HWCAP_FLAGM + HWCAP_SSBS + + Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010. ++ ++ ++4. Unused AT_HWCAP bits ++----------------------- ++ ++For interoperation with userspace, the kernel guarantees that bits 62 ++and 63 of AT_HWCAP will always be returned as 0. +diff --git a/arch/arm64/crypto/aes-ce-ccm-glue.c b/arch/arm64/crypto/aes-ce-ccm-glue.c +index 5fc6f51908fd..036ea77f83bc 100644 +--- a/arch/arm64/crypto/aes-ce-ccm-glue.c ++++ b/arch/arm64/crypto/aes-ce-ccm-glue.c +@@ -372,7 +372,7 @@ static struct aead_alg ccm_aes_alg = { + + static int __init aes_mod_init(void) + { +- if (!(elf_hwcap & HWCAP_AES)) ++ if (!cpu_have_named_feature(AES)) + return -ENODEV; + return crypto_register_aead(&ccm_aes_alg); + } +diff --git a/arch/arm64/crypto/aes-neonbs-glue.c b/arch/arm64/crypto/aes-neonbs-glue.c +index 5cc248967387..742359801559 100644 +--- a/arch/arm64/crypto/aes-neonbs-glue.c ++++ b/arch/arm64/crypto/aes-neonbs-glue.c +@@ -442,7 +442,7 @@ static int __init aes_init(void) + int err; + int i; + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + + err = crypto_register_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); +diff --git a/arch/arm64/crypto/chacha20-neon-glue.c b/arch/arm64/crypto/chacha20-neon-glue.c +index 727579c93ded..bb3314905bee 100644 +--- a/arch/arm64/crypto/chacha20-neon-glue.c ++++ b/arch/arm64/crypto/chacha20-neon-glue.c +@@ -114,7 +114,7 @@ static struct skcipher_alg alg = { + + static int __init chacha20_simd_mod_init(void) + { +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + + return crypto_register_skcipher(&alg); +diff --git a/arch/arm64/crypto/ghash-ce-glue.c b/arch/arm64/crypto/ghash-ce-glue.c +index 1ed227bf6106..cd9d743cb40f 100644 +--- a/arch/arm64/crypto/ghash-ce-glue.c ++++ b/arch/arm64/crypto/ghash-ce-glue.c +@@ -648,10 +648,10 @@ static int __init ghash_ce_mod_init(void) + { + int ret; + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + +- if (elf_hwcap & HWCAP_PMULL) ++ if (cpu_have_named_feature(PMULL)) + pmull_ghash_update = pmull_ghash_update_p64; + + else +@@ -661,7 +661,7 @@ static int __init ghash_ce_mod_init(void) + if (ret) + return ret; + +- if (elf_hwcap & HWCAP_PMULL) { ++ if (cpu_have_named_feature(PMULL)) { + ret = crypto_register_aead(&gcm_aes_alg); + if (ret) + crypto_unregister_shash(&ghash_alg); +diff --git a/arch/arm64/crypto/sha256-glue.c b/arch/arm64/crypto/sha256-glue.c +index 4aedeaefd61f..0cccdb9cc2c0 100644 +--- a/arch/arm64/crypto/sha256-glue.c ++++ b/arch/arm64/crypto/sha256-glue.c +@@ -173,7 +173,7 @@ static int __init sha256_mod_init(void) + if (ret) + return ret; + +- if (elf_hwcap & HWCAP_ASIMD) { ++ if (cpu_have_named_feature(ASIMD)) { + ret = crypto_register_shashes(neon_algs, ARRAY_SIZE(neon_algs)); + if (ret) + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); +@@ -183,7 +183,7 @@ static int __init sha256_mod_init(void) + + static void __exit sha256_mod_fini(void) + { +- if (elf_hwcap & HWCAP_ASIMD) ++ if (cpu_have_named_feature(ASIMD)) + crypto_unregister_shashes(neon_algs, ARRAY_SIZE(neon_algs)); + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); + } +diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h +index ffb0a1ec0088..eef5a9c9b823 100644 +--- a/arch/arm64/include/asm/cpufeature.h ++++ b/arch/arm64/include/asm/cpufeature.h +@@ -14,15 +14,8 @@ + #include <asm/hwcap.h> + #include <asm/sysreg.h> + +-/* +- * In the arm64 world (as in the ARM world), elf_hwcap is used both internally +- * in the kernel and for user space to keep track of which optional features +- * are supported by the current system. So let's map feature 'x' to HWCAP_x. +- * Note that HWCAP_x constants are bit fields so we need to take the log. +- */ +- +-#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap)) +-#define cpu_feature(x) ilog2(HWCAP_ ## x) ++#define MAX_CPU_FEATURES 64 ++#define cpu_feature(x) KERNEL_HWCAP_ ## x + + #ifndef __ASSEMBLY__ + +@@ -372,10 +365,19 @@ extern bool set_cap_spectre_bhb; + + bool this_cpu_has_cap(unsigned int cap); + ++static inline void cpu_set_feature(unsigned int num) ++{ ++ WARN_ON(num >= MAX_CPU_FEATURES); ++ elf_hwcap |= BIT(num); ++} ++#define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name)) ++ + static inline bool cpu_have_feature(unsigned int num) + { +- return elf_hwcap & (1UL << num); ++ WARN_ON(num >= MAX_CPU_FEATURES); ++ return elf_hwcap & BIT(num); + } ++#define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name)) + + /* System capability check for constant caps */ + static __always_inline bool __cpus_have_const_cap(int num) +diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h +index 428b745b5386..458ff2d7ece3 100644 +--- a/arch/arm64/include/asm/hwcap.h ++++ b/arch/arm64/include/asm/hwcap.h +@@ -40,11 +40,58 @@ + #define COMPAT_HWCAP2_CRC32 (1 << 4) + + #ifndef __ASSEMBLY__ ++#include <linux/kernel.h> ++#include <linux/log2.h> ++ ++/* ++ * For userspace we represent hwcaps as a collection of HWCAP{,2}_x bitfields ++ * as described in uapi/asm/hwcap.h. For the kernel we represent hwcaps as ++ * natural numbers (in a single range of size MAX_CPU_FEATURES) defined here ++ * with prefix KERNEL_HWCAP_ mapped to their HWCAP{,2}_x counterpart. ++ * ++ * Hwcaps should be set and tested within the kernel via the ++ * cpu_{set,have}_named_feature(feature) where feature is the unique suffix ++ * of KERNEL_HWCAP_{feature}. ++ */ ++#define __khwcap_feature(x) const_ilog2(HWCAP_ ## x) ++#define KERNEL_HWCAP_FP __khwcap_feature(FP) ++#define KERNEL_HWCAP_ASIMD __khwcap_feature(ASIMD) ++#define KERNEL_HWCAP_EVTSTRM __khwcap_feature(EVTSTRM) ++#define KERNEL_HWCAP_AES __khwcap_feature(AES) ++#define KERNEL_HWCAP_PMULL __khwcap_feature(PMULL) ++#define KERNEL_HWCAP_SHA1 __khwcap_feature(SHA1) ++#define KERNEL_HWCAP_SHA2 __khwcap_feature(SHA2) ++#define KERNEL_HWCAP_CRC32 __khwcap_feature(CRC32) ++#define KERNEL_HWCAP_ATOMICS __khwcap_feature(ATOMICS) ++#define KERNEL_HWCAP_FPHP __khwcap_feature(FPHP) ++#define KERNEL_HWCAP_ASIMDHP __khwcap_feature(ASIMDHP) ++#define KERNEL_HWCAP_CPUID __khwcap_feature(CPUID) ++#define KERNEL_HWCAP_ASIMDRDM __khwcap_feature(ASIMDRDM) ++#define KERNEL_HWCAP_JSCVT __khwcap_feature(JSCVT) ++#define KERNEL_HWCAP_FCMA __khwcap_feature(FCMA) ++#define KERNEL_HWCAP_LRCPC __khwcap_feature(LRCPC) ++#define KERNEL_HWCAP_DCPOP __khwcap_feature(DCPOP) ++#define KERNEL_HWCAP_SHA3 __khwcap_feature(SHA3) ++#define KERNEL_HWCAP_SM3 __khwcap_feature(SM3) ++#define KERNEL_HWCAP_SM4 __khwcap_feature(SM4) ++#define KERNEL_HWCAP_ASIMDDP __khwcap_feature(ASIMDDP) ++#define KERNEL_HWCAP_SHA512 __khwcap_feature(SHA512) ++#define KERNEL_HWCAP_SVE __khwcap_feature(SVE) ++#define KERNEL_HWCAP_ASIMDFHM __khwcap_feature(ASIMDFHM) ++#define KERNEL_HWCAP_DIT __khwcap_feature(DIT) ++#define KERNEL_HWCAP_USCAT __khwcap_feature(USCAT) ++#define KERNEL_HWCAP_ILRCPC __khwcap_feature(ILRCPC) ++#define KERNEL_HWCAP_FLAGM __khwcap_feature(FLAGM) ++#define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS) ++ ++#define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 32) ++ + /* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +-#define ELF_HWCAP (elf_hwcap) ++#define ELF_HWCAP lower_32_bits(elf_hwcap) ++#define ELF_HWCAP2 upper_32_bits(elf_hwcap) + + #ifdef CONFIG_AARCH32_EL0 + extern unsigned int a32_elf_hwcap, a32_elf_hwcap2; +diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h +index 2bcd6e4f3474..602158a55554 100644 +--- a/arch/arm64/include/uapi/asm/hwcap.h ++++ b/arch/arm64/include/uapi/asm/hwcap.h +@@ -18,7 +18,7 @@ + #define _UAPI__ASM_HWCAP_H + + /* +- * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP ++ * HWCAP flags - for AT_HWCAP + */ + #define HWCAP_FP (1 << 0) + #define HWCAP_ASIMD (1 << 1) +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 1c93cc3f7692..3a0e7e10f2d7 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1553,35 +1553,35 @@ static const struct arm64_cpu_capabilities arm64_features[] = { + } + + static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC), +- HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), ++ HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), + #ifdef CONFIG_ARM64_SVE +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), + #endif +- HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS), ++ HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), + {}, + }; + +@@ -1627,7 +1627,7 @@ static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) + { + switch (cap->hwcap_type) { + case CAP_HWCAP: +- elf_hwcap |= cap->hwcap; ++ cpu_set_feature(cap->hwcap); + break; + #ifdef CONFIG_AARCH32_EL0 + case CAP_COMPAT_HWCAP: +@@ -1650,7 +1650,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) + + switch (cap->hwcap_type) { + case CAP_HWCAP: +- rc = (elf_hwcap & cap->hwcap) != 0; ++ rc = cpu_have_feature(cap->hwcap); + break; + #ifdef CONFIG_AARCH32_EL0 + case CAP_COMPAT_HWCAP: +@@ -1671,7 +1671,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) + static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) + { + /* We support emulation of accesses to CPU ID feature registers */ +- elf_hwcap |= HWCAP_CPUID; ++ cpu_set_named_feature(CPUID); + for (; hwcaps->matches; hwcaps++) + if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) + cap_set_elf_hwcap(hwcaps); +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index 005d88db1082..bfe3bb8f05fe 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -164,7 +164,7 @@ static int c_show(struct seq_file *m, void *v) + #endif /* CONFIG_AARCH32_EL0 */ + } else { + for (j = 0; hwcap_str[j]; j++) +- if (elf_hwcap & (1 << j)) ++ if (cpu_have_feature(j)) + seq_printf(m, " %s", hwcap_str[j]); + } + seq_puts(m, "\n"); +diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c +index bb048144c3bd..6972de5681ec 100644 +--- a/arch/arm64/kernel/fpsimd.c ++++ b/arch/arm64/kernel/fpsimd.c +@@ -1302,14 +1302,14 @@ static inline void fpsimd_hotplug_init(void) { } + */ + static int __init fpsimd_init(void) + { +- if (elf_hwcap & HWCAP_FP) { ++ if (cpu_have_named_feature(FP)) { + fpsimd_pm_init(); + fpsimd_hotplug_init(); + } else { + pr_notice("Floating-point is not implemented\n"); + } + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + pr_notice("Advanced SIMD is not implemented\n"); + + return sve_sysctl_init(); +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index 58863fd9c91b..fbfc81932dea 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -825,7 +825,11 @@ static void arch_timer_evtstrm_enable(int divider) + cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) + | ARCH_TIMER_VIRT_EVT_EN; + arch_timer_set_cntkctl(cntkctl); ++#ifdef CONFIG_ARM64 ++ cpu_set_named_feature(EVTSTRM); ++#else + elf_hwcap |= HWCAP_EVTSTRM; ++#endif + #ifdef CONFIG_AARCH32_EL0 + a32_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; + #endif +@@ -1059,7 +1063,11 @@ static int arch_timer_cpu_pm_notify(struct notifier_block *self, + } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) { + arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl)); + ++#ifdef CONFIG_ARM64 ++ if (cpu_have_named_feature(EVTSTRM)) ++#else + if (elf_hwcap & HWCAP_EVTSTRM) ++#endif + cpumask_set_cpu(smp_processor_id(), &evtstrm_available); + } + return NOTIFY_OK; +-- +2.25.1 + diff --git a/patches/0098-arm64-Expose-SVE2-features-for-userspace.patch b/patches/0098-arm64-Expose-SVE2-features-for-userspace.patch new file mode 100644 index 000000000000..45f709f3fab0 --- /dev/null +++ b/patches/0098-arm64-Expose-SVE2-features-for-userspace.patch @@ -0,0 +1,275 @@ +From 2ba00283ddd367afa75f72e3b4de15f80b4a97a7 Mon Sep 17 00:00:00 2001 +From: Dave Martin <Dave.Martin(a)arm.com> +Date: Thu, 18 Apr 2019 18:41:38 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 2/4] arm64: Expose SVE2 features for + userspace + +mainline inclusion +from mainline-v5.2-rc1 +commit 06a916feca2b262ab0c1a2aeb68882f4b1108a07 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +This patch provides support for reporting the presence of SVE2 and +its optional features to userspace. + +This will also enable visibility of SVE2 for guests, when KVM +support for SVE-enabled guests is available. + +Signed-off-by: Dave Martin <Dave.Martin(a)arm.com> +Signed-off-by: Will Deacon <will.deacon(a)arm.com> + +Conflicts: + arch/arm64/include/asm/hwcap.h + arch/arm64/include/uapi/asm/hwcap.h + arch/arm64/kernel/cpuinfo.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + Documentation/arm64/cpu-feature-registers.txt | 16 +++++++++++++ + Documentation/arm64/elf_hwcaps.txt | 24 +++++++++++++++++++ + Documentation/arm64/sve.txt | 17 +++++++++++++ + arch/arm64/Kconfig | 3 +++ + arch/arm64/include/asm/hwcap.h | 6 +++++ + arch/arm64/include/asm/sysreg.h | 14 +++++++++++ + arch/arm64/include/uapi/asm/hwcap.h | 10 ++++++++ + arch/arm64/kernel/cpufeature.c | 17 ++++++++++++- + arch/arm64/kernel/cpuinfo.c | 10 ++++++++ + 9 files changed, 116 insertions(+), 1 deletion(-) + +diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt +index 7964f03846b1..fcd2e1deb886 100644 +--- a/Documentation/arm64/cpu-feature-registers.txt ++++ b/Documentation/arm64/cpu-feature-registers.txt +@@ -201,6 +201,22 @@ infrastructure: + | AT | [35-32] | y | + x--------------------------------------------------x + ++ 6) ID_AA64ZFR0_EL1 - SVE feature ID register 0 ++ ++ x--------------------------------------------------x ++ | Name | bits | visible | ++ |--------------------------------------------------| ++ | SM4 | [43-40] | y | ++ |--------------------------------------------------| ++ | SHA3 | [35-32] | y | ++ |--------------------------------------------------| ++ | BitPerm | [19-16] | y | ++ |--------------------------------------------------| ++ | AES | [7-4] | y | ++ |--------------------------------------------------| ++ | SVEVer | [3-0] | y | ++ x--------------------------------------------------x ++ + Appendix I: Example + --------------------------- + +diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt +index 186feb16e2f2..e2ce14dfccf2 100644 +--- a/Documentation/arm64/elf_hwcaps.txt ++++ b/Documentation/arm64/elf_hwcaps.txt +@@ -159,6 +159,30 @@ HWCAP_SVE + + Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001. + ++HWCAP2_SVE2 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. ++ ++HWCAP2_SVEAES ++ ++ Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. ++ ++HWCAP2_SVEPMULL ++ ++ Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. ++ ++HWCAP2_SVEBITPERM ++ ++ Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. ++ ++HWCAP2_SVESHA3 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. ++ ++HWCAP2_SVESM4 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. ++ + HWCAP_ASIMDFHM + + Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001. +diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt +index 2001d84384ca..5689fc9a976a 100644 +--- a/Documentation/arm64/sve.txt ++++ b/Documentation/arm64/sve.txt +@@ -34,6 +34,23 @@ model features for SVE is included in Appendix A. + following sections: software that needs to verify that those interfaces are + present must check for HWCAP_SVE instead. + ++* On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also ++ be reported in the AT_HWCAP2 aux vector entry. In addition to this, ++ optional extensions to SVE2 may be reported by the presence of: ++ ++ HWCAP2_SVE2 ++ HWCAP2_SVEAES ++ HWCAP2_SVEPMULL ++ HWCAP2_SVEBITPERM ++ HWCAP2_SVESHA3 ++ HWCAP2_SVESM4 ++ ++ This list may be extended over time as the SVE architecture evolves. ++ ++ These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1, ++ which userspace can read using an MRS instruction. See elf_hwcaps.txt and ++ cpu-feature-registers.txt for details. ++ + * Debuggers should restrict themselves to interacting with the target via the + NT_ARM_SVE regset. The recommended way of detecting support for this regset + is to connect to a target process first and then attempt a +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 88b8031a93b2..f7398a1904a2 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1316,6 +1316,9 @@ config ARM64_SVE + + To enable use of this extension on CPUs that implement it, say Y. + ++ On CPUs that support the SVE2 extensions, this option will enable ++ those too. ++ + Note that for architectural reasons, firmware _must_ implement SVE + support when running on SVE capable hardware. The required support + is present in: +diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h +index 458ff2d7ece3..08315a3bf387 100644 +--- a/arch/arm64/include/asm/hwcap.h ++++ b/arch/arm64/include/asm/hwcap.h +@@ -85,6 +85,12 @@ + #define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS) + + #define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 32) ++#define KERNEL_HWCAP_SVE2 __khwcap2_feature(SVE2) ++#define KERNEL_HWCAP_SVEAES __khwcap2_feature(SVEAES) ++#define KERNEL_HWCAP_SVEPMULL __khwcap2_feature(SVEPMULL) ++#define KERNEL_HWCAP_SVEBITPERM __khwcap2_feature(SVEBITPERM) ++#define KERNEL_HWCAP_SVESHA3 __khwcap2_feature(SVESHA3) ++#define KERNEL_HWCAP_SVESM4 __khwcap2_feature(SVESM4) + + /* + * This yields a mask that user programs can use to figure out what +diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h +index 0fd51d253648..69618e602ed8 100644 +--- a/arch/arm64/include/asm/sysreg.h ++++ b/arch/arm64/include/asm/sysreg.h +@@ -564,6 +564,20 @@ + #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 + #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 + ++/* id_aa64zfr0 */ ++#define ID_AA64ZFR0_SM4_SHIFT 40 ++#define ID_AA64ZFR0_SHA3_SHIFT 32 ++#define ID_AA64ZFR0_BITPERM_SHIFT 16 ++#define ID_AA64ZFR0_AES_SHIFT 4 ++#define ID_AA64ZFR0_SVEVER_SHIFT 0 ++ ++#define ID_AA64ZFR0_SM4 0x1 ++#define ID_AA64ZFR0_SHA3 0x1 ++#define ID_AA64ZFR0_BITPERM 0x1 ++#define ID_AA64ZFR0_AES 0x1 ++#define ID_AA64ZFR0_AES_PMULL 0x2 ++#define ID_AA64ZFR0_SVEVER_SVE2 0x1 ++ + /* id_aa64mmfr0 */ + #define ID_AA64MMFR0_TGRAN4_SHIFT 28 + #define ID_AA64MMFR0_TGRAN64_SHIFT 24 +diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h +index 602158a55554..fea93415b493 100644 +--- a/arch/arm64/include/uapi/asm/hwcap.h ++++ b/arch/arm64/include/uapi/asm/hwcap.h +@@ -50,4 +50,14 @@ + #define HWCAP_FLAGM (1 << 27) + #define HWCAP_SSBS (1 << 28) + ++/* ++ * HWCAP2 flags - for AT_HWCAP2 ++ */ ++#define HWCAP2_SVE2 (1 << 1) ++#define HWCAP2_SVEAES (1 << 2) ++#define HWCAP2_SVEPMULL (1 << 3) ++#define HWCAP2_SVEBITPERM (1 << 4) ++#define HWCAP2_SVESHA3 (1 << 5) ++#define HWCAP2_SVESM4 (1 << 6) ++ + #endif /* _UAPI__ASM_HWCAP_H */ +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 3a0e7e10f2d7..4f384bbd86c7 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -183,6 +183,15 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + ARM64_FTR_END, + }; + ++static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), ++ ARM64_FTR_END, ++}; ++ + static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { + /* + * We already refuse to boot CPUs that don't support our configured +@@ -399,7 +408,7 @@ static const struct __ftr_reg_entry { + /* Op1 = 0, CRn = 0, CRm = 4 */ + ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), + ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), +- ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), ++ ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), + + /* Op1 = 0, CRn = 0, CRm = 5 */ + ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), +@@ -1580,6 +1589,12 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { + HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), + #ifdef CONFIG_ARM64_SVE + HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), + #endif + HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), + {}, +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index bfe3bb8f05fe..c8e4ddd23f0c 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -82,6 +82,16 @@ static const char *const hwcap_str[] = { + "ilrcpc", + "flagm", + "ssbs", ++ "sb", ++ "paca", ++ "pacg", ++ "dcpodp", ++ "sve2", ++ "sveaes", ++ "svepmull", ++ "svebitperm", ++ "svesha3", ++ "svesm4", + NULL + }; + +-- +2.25.1 + diff --git a/patches/0099-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch b/patches/0099-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch new file mode 100644 index 000000000000..4ce008cecf19 --- /dev/null +++ b/patches/0099-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch @@ -0,0 +1,55 @@ +From 9f8dff634365e7bfa0c764ccd31b54a4f0992bc8 Mon Sep 17 00:00:00 2001 +From: Dave Martin <Dave.Martin(a)arm.com> +Date: Mon, 3 Jun 2019 16:35:02 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 3/4] arm64: cpufeature: Fix missing + ZFR0 in __read_sysreg_by_encoding() + +mainline inclusion +from mainline-v5.2-rc4 +commit 78ed70bf3a923f1965e3c19f544677d418397108 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +In commit 06a916feca2b ("arm64: Expose SVE2 features for +userspace"), new hwcaps are added that are detected via fields in +the SVE-specific ID register ID_AA64ZFR0_EL1. + +In order to check compatibility of secondary cpus with the hwcaps +established at boot, the cpufeatures code uses +__read_sysreg_by_encoding() to read this ID register based on the +sys_reg field of the arm64_elf_hwcaps[] table. + +This leads to a kernel splat if an hwcap uses an ID register that +__read_sysreg_by_encoding() doesn't explicitly handle, as now +happens when exercising cpu hotplug on an SVE2-capable platform. + +So fix it by adding the required case in there. + +Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace") +Signed-off-by: Dave Martin <Dave.Martin(a)arm.com> +Signed-off-by: Will Deacon <will.deacon(a)arm.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + arch/arm64/kernel/cpufeature.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 4f384bbd86c7..8e7473df2660 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -828,6 +828,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) + + read_sysreg_case(SYS_ID_AA64PFR0_EL1); + read_sysreg_case(SYS_ID_AA64PFR1_EL1); ++ read_sysreg_case(SYS_ID_AA64ZFR0_EL1); + read_sysreg_case(SYS_ID_AA64DFR0_EL1); + read_sysreg_case(SYS_ID_AA64DFR1_EL1); + read_sysreg_case(SYS_ID_AA64MMFR0_EL1); +-- +2.25.1 + diff --git a/patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch b/patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch new file mode 100644 index 000000000000..7df40531adda --- /dev/null +++ b/patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch @@ -0,0 +1,67 @@ +From 515c2917ae3bc768e8793dac6b27ea4dff36b40c Mon Sep 17 00:00:00 2001 +From: Julien Grall <julien.grall(a)arm.com> +Date: Mon, 14 Oct 2019 11:21:13 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 4/4] arm64: cpufeature: Treat + ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled + +mainline inclusion +from mainline-v5.4-rc4 +commit ec52c7134b1fcef0edfc56d55072fd4f261ef198 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +If CONFIG_ARM64_SVE=n then we fail to report ID_AA64ZFR0_EL1 as 0 when +read by userspace, despite being required by the architecture. Although +this is theoretically a change in ABI, userspace will first check for +the presence of SVE via the HWCAP or the ID_AA64PFR0_EL1.SVE field +before probing the ID_AA64ZFR0_EL1 register. Given that these are +reported correctly for this configuration, we can safely tighten up the +current behaviour. + +Ensure ID_AA64ZFR0_EL1 is treated as RAZ when CONFIG_ARM64_SVE=n. + +Signed-off-by: Julien Grall <julien.grall(a)arm.com> +Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> +Reviewed-by: Mark Rutland <mark.rutland(a)arm.com> +Reviewed-by: Dave Martin <dave.martin(a)arm.com> +Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace") +Signed-off-by: Will Deacon <will(a)kernel.org> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + arch/arm64/kernel/cpufeature.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 8e7473df2660..98a8b2703f84 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -184,11 +184,16 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + }; + + static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), + ARM64_FTR_END, + }; + +-- +2.25.1 + diff --git a/series.conf b/series.conf index 4a8fef62b657..b4c8a39443d8 100644 --- a/series.conf +++ b/series.conf @@ -97,3 +97,7 @@ patches/0093-Revert-perf-smmuv3_pmu-Enable-HiSilicon-Erratum-1620.patch patches/0094-perf-smmuv3-Enable-HiSilicon-Erratum-162001800-quirk.patch patches/0095-perf-smmuv3-Enable-HiSilicon-Erratum-162001900-quirk.patch patches/0096-perf-smmuv3-Add-MODULE_ALIAS-for-module-auto-loading.patch +patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch +patches/0098-arm64-Expose-SVE2-features-for-userspace.patch +patches/0099-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch +patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch -- 2.25.1

2 1

[PATCH openEuler-20.03-LTS-SP4] Expose SVE2 features for userspace
by Yu Liao 03 Nov '23

03 Nov '23

--- kernel.spec | 7 +- ...-Fix-missing-ZFR0-in-__read_sysreg_b.patch | 55 +++ ...rm64-HWCAP-add-support-for-AT_HWCAP2.patch | 463 ++++++++++++++++++ ...4-Expose-SVE2-features-for-userspace.patch | 275 +++++++++++ ...-Expose-SVE2-features-for-userspace.patch} | 0 ...-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch | 67 +++ series.conf | 4 + 7 files changed, 870 insertions(+), 1 deletion(-) create mode 100644 patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch create mode 100644 patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch create mode 100644 patches/0098-arm64-Expose-SVE2-features-for-userspace.patch rename patches/{0044-Revert-perf-hisi-Add-support-for-HiSilicon-SoC-LPDDR.patch => 0099-Expose-SVE2-features-for-userspace.patch} (100%) create mode 100644 patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch diff --git a/kernel.spec b/kernel.spec index acf822fc666d..a1a1fad55bdd 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0231 +Release: %{hulkrelease}.0232 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -832,6 +832,11 @@ fi %changelog +* Fri Nov 3 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2310.4.0.0232 +- arm64: HWCAP: add support for AT_HWCAP2 +- arm64: Expose SVE2 features for userspace +- arm64: cpufeature: Fix missing ZFR0 in __read_sysreg_by_encoding() + * Wed Nov 1 2023 hongrongxuan <hongrongxuan(a)huawei.com> - 4.19.90-2311.1.0.0231 - perf/smmuv3: Add MODULE_ALIAS for module auto loading - perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09 diff --git a/patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch b/patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch new file mode 100644 index 000000000000..4ce008cecf19 --- /dev/null +++ b/patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch @@ -0,0 +1,55 @@ +From 9f8dff634365e7bfa0c764ccd31b54a4f0992bc8 Mon Sep 17 00:00:00 2001 +From: Dave Martin <Dave.Martin(a)arm.com> +Date: Mon, 3 Jun 2019 16:35:02 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 3/4] arm64: cpufeature: Fix missing + ZFR0 in __read_sysreg_by_encoding() + +mainline inclusion +from mainline-v5.2-rc4 +commit 78ed70bf3a923f1965e3c19f544677d418397108 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +In commit 06a916feca2b ("arm64: Expose SVE2 features for +userspace"), new hwcaps are added that are detected via fields in +the SVE-specific ID register ID_AA64ZFR0_EL1. + +In order to check compatibility of secondary cpus with the hwcaps +established at boot, the cpufeatures code uses +__read_sysreg_by_encoding() to read this ID register based on the +sys_reg field of the arm64_elf_hwcaps[] table. + +This leads to a kernel splat if an hwcap uses an ID register that +__read_sysreg_by_encoding() doesn't explicitly handle, as now +happens when exercising cpu hotplug on an SVE2-capable platform. + +So fix it by adding the required case in there. + +Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace") +Signed-off-by: Dave Martin <Dave.Martin(a)arm.com> +Signed-off-by: Will Deacon <will.deacon(a)arm.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + arch/arm64/kernel/cpufeature.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 4f384bbd86c7..8e7473df2660 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -828,6 +828,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) + + read_sysreg_case(SYS_ID_AA64PFR0_EL1); + read_sysreg_case(SYS_ID_AA64PFR1_EL1); ++ read_sysreg_case(SYS_ID_AA64ZFR0_EL1); + read_sysreg_case(SYS_ID_AA64DFR0_EL1); + read_sysreg_case(SYS_ID_AA64DFR1_EL1); + read_sysreg_case(SYS_ID_AA64MMFR0_EL1); +-- +2.25.1 + diff --git a/patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch b/patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch new file mode 100644 index 000000000000..46effba895fb --- /dev/null +++ b/patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch @@ -0,0 +1,463 @@ +From a97497b283894653e53f7eb83b5825f5564d1614 Mon Sep 17 00:00:00 2001 +From: Andrew Murray <andrew.murray(a)arm.com> +Date: Tue, 9 Apr 2019 10:52:40 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 1/4] arm64: HWCAP: add support for + AT_HWCAP2 + +mainline inclusion +from mainline-v5.2-rc1 +commit 06a916feca2b262ab0c1a2aeb68882f4b1108a07 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +As we will exhaust the first 32 bits of AT_HWCAP let's start +exposing AT_HWCAP2 to userspace to give us up to 64 caps. + +Whilst it's possible to use the remaining 32 bits of AT_HWCAP, we +prefer to expand into AT_HWCAP2 in order to provide a consistent +view to userspace between ILP32 and LP64. However internal to the +kernel we prefer to continue to use the full space of elf_hwcap. + +To reduce complexity and allow for future expansion, we now +represent hwcaps in the kernel as ordinals and use a +KERNEL_HWCAP_ prefix. This allows us to support automatic feature +based module loading for all our hwcaps. + +We introduce cpu_set_feature to set hwcaps which complements the +existing cpu_have_feature helper. These helpers allow us to clean +up existing direct uses of elf_hwcap and reduce any future effort +required to move beyond 64 caps. + +For convenience we also introduce cpu_{have,set}_named_feature which +makes use of the cpu_feature macro to allow providing a hwcap name +without a {KERNEL_}HWCAP_ prefix. + +Signed-off-by: Andrew Murray <andrew.murray(a)arm.com> +[will: use const_ilog2() and tweak documentation] +Signed-off-by: Will Deacon <will.deacon(a)arm.com> + +Conflicts: + Documentation/arm64/elf_hwcaps.txt + arch/arm64/crypto/chacha-neon-glue.c + arch/arm64/crypto/crct10dif-ce-glue.c + arch/arm64/crypto/ghash-ce-glue.c + arch/arm64/crypto/nhpoly1305-neon-glue.c + arch/arm64/kernel/cpufeature.c + drivers/clocksource/arm_arch_timer.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + Documentation/arm64/elf_hwcaps.txt | 13 ++++-- + arch/arm64/crypto/aes-ce-ccm-glue.c | 2 +- + arch/arm64/crypto/aes-neonbs-glue.c | 2 +- + arch/arm64/crypto/chacha20-neon-glue.c | 2 +- + arch/arm64/crypto/ghash-ce-glue.c | 6 +-- + arch/arm64/crypto/sha256-glue.c | 4 +- + arch/arm64/include/asm/cpufeature.h | 22 +++++----- + arch/arm64/include/asm/hwcap.h | 49 ++++++++++++++++++++- + arch/arm64/include/uapi/asm/hwcap.h | 2 +- + arch/arm64/kernel/cpufeature.c | 60 +++++++++++++------------- + arch/arm64/kernel/cpuinfo.c | 2 +- + arch/arm64/kernel/fpsimd.c | 4 +- + drivers/clocksource/arm_arch_timer.c | 8 ++++ + 13 files changed, 120 insertions(+), 56 deletions(-) + +diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt +index 6feaffe90e22..186feb16e2f2 100644 +--- a/Documentation/arm64/elf_hwcaps.txt ++++ b/Documentation/arm64/elf_hwcaps.txt +@@ -13,9 +13,9 @@ architected discovery mechanism available to userspace code at EL0. The + kernel exposes the presence of these features to userspace through a set + of flags called hwcaps, exposed in the auxilliary vector. + +-Userspace software can test for features by acquiring the AT_HWCAP entry +-of the auxilliary vector, and testing whether the relevant flags are +-set, e.g. ++Userspace software can test for features by acquiring the AT_HWCAP or ++AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant ++flags are set, e.g. + + bool floating_point_is_present(void) + { +@@ -182,3 +182,10 @@ HWCAP_FLAGM + HWCAP_SSBS + + Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010. ++ ++ ++4. Unused AT_HWCAP bits ++----------------------- ++ ++For interoperation with userspace, the kernel guarantees that bits 62 ++and 63 of AT_HWCAP will always be returned as 0. +diff --git a/arch/arm64/crypto/aes-ce-ccm-glue.c b/arch/arm64/crypto/aes-ce-ccm-glue.c +index 5fc6f51908fd..036ea77f83bc 100644 +--- a/arch/arm64/crypto/aes-ce-ccm-glue.c ++++ b/arch/arm64/crypto/aes-ce-ccm-glue.c +@@ -372,7 +372,7 @@ static struct aead_alg ccm_aes_alg = { + + static int __init aes_mod_init(void) + { +- if (!(elf_hwcap & HWCAP_AES)) ++ if (!cpu_have_named_feature(AES)) + return -ENODEV; + return crypto_register_aead(&ccm_aes_alg); + } +diff --git a/arch/arm64/crypto/aes-neonbs-glue.c b/arch/arm64/crypto/aes-neonbs-glue.c +index 5cc248967387..742359801559 100644 +--- a/arch/arm64/crypto/aes-neonbs-glue.c ++++ b/arch/arm64/crypto/aes-neonbs-glue.c +@@ -442,7 +442,7 @@ static int __init aes_init(void) + int err; + int i; + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + + err = crypto_register_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); +diff --git a/arch/arm64/crypto/chacha20-neon-glue.c b/arch/arm64/crypto/chacha20-neon-glue.c +index 727579c93ded..bb3314905bee 100644 +--- a/arch/arm64/crypto/chacha20-neon-glue.c ++++ b/arch/arm64/crypto/chacha20-neon-glue.c +@@ -114,7 +114,7 @@ static struct skcipher_alg alg = { + + static int __init chacha20_simd_mod_init(void) + { +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + + return crypto_register_skcipher(&alg); +diff --git a/arch/arm64/crypto/ghash-ce-glue.c b/arch/arm64/crypto/ghash-ce-glue.c +index 1ed227bf6106..cd9d743cb40f 100644 +--- a/arch/arm64/crypto/ghash-ce-glue.c ++++ b/arch/arm64/crypto/ghash-ce-glue.c +@@ -648,10 +648,10 @@ static int __init ghash_ce_mod_init(void) + { + int ret; + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + +- if (elf_hwcap & HWCAP_PMULL) ++ if (cpu_have_named_feature(PMULL)) + pmull_ghash_update = pmull_ghash_update_p64; + + else +@@ -661,7 +661,7 @@ static int __init ghash_ce_mod_init(void) + if (ret) + return ret; + +- if (elf_hwcap & HWCAP_PMULL) { ++ if (cpu_have_named_feature(PMULL)) { + ret = crypto_register_aead(&gcm_aes_alg); + if (ret) + crypto_unregister_shash(&ghash_alg); +diff --git a/arch/arm64/crypto/sha256-glue.c b/arch/arm64/crypto/sha256-glue.c +index 4aedeaefd61f..0cccdb9cc2c0 100644 +--- a/arch/arm64/crypto/sha256-glue.c ++++ b/arch/arm64/crypto/sha256-glue.c +@@ -173,7 +173,7 @@ static int __init sha256_mod_init(void) + if (ret) + return ret; + +- if (elf_hwcap & HWCAP_ASIMD) { ++ if (cpu_have_named_feature(ASIMD)) { + ret = crypto_register_shashes(neon_algs, ARRAY_SIZE(neon_algs)); + if (ret) + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); +@@ -183,7 +183,7 @@ static int __init sha256_mod_init(void) + + static void __exit sha256_mod_fini(void) + { +- if (elf_hwcap & HWCAP_ASIMD) ++ if (cpu_have_named_feature(ASIMD)) + crypto_unregister_shashes(neon_algs, ARRAY_SIZE(neon_algs)); + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); + } +diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h +index ffb0a1ec0088..eef5a9c9b823 100644 +--- a/arch/arm64/include/asm/cpufeature.h ++++ b/arch/arm64/include/asm/cpufeature.h +@@ -14,15 +14,8 @@ + #include <asm/hwcap.h> + #include <asm/sysreg.h> + +-/* +- * In the arm64 world (as in the ARM world), elf_hwcap is used both internally +- * in the kernel and for user space to keep track of which optional features +- * are supported by the current system. So let's map feature 'x' to HWCAP_x. +- * Note that HWCAP_x constants are bit fields so we need to take the log. +- */ +- +-#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap)) +-#define cpu_feature(x) ilog2(HWCAP_ ## x) ++#define MAX_CPU_FEATURES 64 ++#define cpu_feature(x) KERNEL_HWCAP_ ## x + + #ifndef __ASSEMBLY__ + +@@ -372,10 +365,19 @@ extern bool set_cap_spectre_bhb; + + bool this_cpu_has_cap(unsigned int cap); + ++static inline void cpu_set_feature(unsigned int num) ++{ ++ WARN_ON(num >= MAX_CPU_FEATURES); ++ elf_hwcap |= BIT(num); ++} ++#define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name)) ++ + static inline bool cpu_have_feature(unsigned int num) + { +- return elf_hwcap & (1UL << num); ++ WARN_ON(num >= MAX_CPU_FEATURES); ++ return elf_hwcap & BIT(num); + } ++#define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name)) + + /* System capability check for constant caps */ + static __always_inline bool __cpus_have_const_cap(int num) +diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h +index 428b745b5386..458ff2d7ece3 100644 +--- a/arch/arm64/include/asm/hwcap.h ++++ b/arch/arm64/include/asm/hwcap.h +@@ -40,11 +40,58 @@ + #define COMPAT_HWCAP2_CRC32 (1 << 4) + + #ifndef __ASSEMBLY__ ++#include <linux/kernel.h> ++#include <linux/log2.h> ++ ++/* ++ * For userspace we represent hwcaps as a collection of HWCAP{,2}_x bitfields ++ * as described in uapi/asm/hwcap.h. For the kernel we represent hwcaps as ++ * natural numbers (in a single range of size MAX_CPU_FEATURES) defined here ++ * with prefix KERNEL_HWCAP_ mapped to their HWCAP{,2}_x counterpart. ++ * ++ * Hwcaps should be set and tested within the kernel via the ++ * cpu_{set,have}_named_feature(feature) where feature is the unique suffix ++ * of KERNEL_HWCAP_{feature}. ++ */ ++#define __khwcap_feature(x) const_ilog2(HWCAP_ ## x) ++#define KERNEL_HWCAP_FP __khwcap_feature(FP) ++#define KERNEL_HWCAP_ASIMD __khwcap_feature(ASIMD) ++#define KERNEL_HWCAP_EVTSTRM __khwcap_feature(EVTSTRM) ++#define KERNEL_HWCAP_AES __khwcap_feature(AES) ++#define KERNEL_HWCAP_PMULL __khwcap_feature(PMULL) ++#define KERNEL_HWCAP_SHA1 __khwcap_feature(SHA1) ++#define KERNEL_HWCAP_SHA2 __khwcap_feature(SHA2) ++#define KERNEL_HWCAP_CRC32 __khwcap_feature(CRC32) ++#define KERNEL_HWCAP_ATOMICS __khwcap_feature(ATOMICS) ++#define KERNEL_HWCAP_FPHP __khwcap_feature(FPHP) ++#define KERNEL_HWCAP_ASIMDHP __khwcap_feature(ASIMDHP) ++#define KERNEL_HWCAP_CPUID __khwcap_feature(CPUID) ++#define KERNEL_HWCAP_ASIMDRDM __khwcap_feature(ASIMDRDM) ++#define KERNEL_HWCAP_JSCVT __khwcap_feature(JSCVT) ++#define KERNEL_HWCAP_FCMA __khwcap_feature(FCMA) ++#define KERNEL_HWCAP_LRCPC __khwcap_feature(LRCPC) ++#define KERNEL_HWCAP_DCPOP __khwcap_feature(DCPOP) ++#define KERNEL_HWCAP_SHA3 __khwcap_feature(SHA3) ++#define KERNEL_HWCAP_SM3 __khwcap_feature(SM3) ++#define KERNEL_HWCAP_SM4 __khwcap_feature(SM4) ++#define KERNEL_HWCAP_ASIMDDP __khwcap_feature(ASIMDDP) ++#define KERNEL_HWCAP_SHA512 __khwcap_feature(SHA512) ++#define KERNEL_HWCAP_SVE __khwcap_feature(SVE) ++#define KERNEL_HWCAP_ASIMDFHM __khwcap_feature(ASIMDFHM) ++#define KERNEL_HWCAP_DIT __khwcap_feature(DIT) ++#define KERNEL_HWCAP_USCAT __khwcap_feature(USCAT) ++#define KERNEL_HWCAP_ILRCPC __khwcap_feature(ILRCPC) ++#define KERNEL_HWCAP_FLAGM __khwcap_feature(FLAGM) ++#define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS) ++ ++#define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 32) ++ + /* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +-#define ELF_HWCAP (elf_hwcap) ++#define ELF_HWCAP lower_32_bits(elf_hwcap) ++#define ELF_HWCAP2 upper_32_bits(elf_hwcap) + + #ifdef CONFIG_AARCH32_EL0 + extern unsigned int a32_elf_hwcap, a32_elf_hwcap2; +diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h +index 2bcd6e4f3474..602158a55554 100644 +--- a/arch/arm64/include/uapi/asm/hwcap.h ++++ b/arch/arm64/include/uapi/asm/hwcap.h +@@ -18,7 +18,7 @@ + #define _UAPI__ASM_HWCAP_H + + /* +- * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP ++ * HWCAP flags - for AT_HWCAP + */ + #define HWCAP_FP (1 << 0) + #define HWCAP_ASIMD (1 << 1) +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 1c93cc3f7692..3a0e7e10f2d7 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1553,35 +1553,35 @@ static const struct arm64_cpu_capabilities arm64_features[] = { + } + + static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC), +- HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), ++ HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), + #ifdef CONFIG_ARM64_SVE +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), + #endif +- HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS), ++ HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), + {}, + }; + +@@ -1627,7 +1627,7 @@ static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) + { + switch (cap->hwcap_type) { + case CAP_HWCAP: +- elf_hwcap |= cap->hwcap; ++ cpu_set_feature(cap->hwcap); + break; + #ifdef CONFIG_AARCH32_EL0 + case CAP_COMPAT_HWCAP: +@@ -1650,7 +1650,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) + + switch (cap->hwcap_type) { + case CAP_HWCAP: +- rc = (elf_hwcap & cap->hwcap) != 0; ++ rc = cpu_have_feature(cap->hwcap); + break; + #ifdef CONFIG_AARCH32_EL0 + case CAP_COMPAT_HWCAP: +@@ -1671,7 +1671,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) + static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) + { + /* We support emulation of accesses to CPU ID feature registers */ +- elf_hwcap |= HWCAP_CPUID; ++ cpu_set_named_feature(CPUID); + for (; hwcaps->matches; hwcaps++) + if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) + cap_set_elf_hwcap(hwcaps); +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index 005d88db1082..bfe3bb8f05fe 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -164,7 +164,7 @@ static int c_show(struct seq_file *m, void *v) + #endif /* CONFIG_AARCH32_EL0 */ + } else { + for (j = 0; hwcap_str[j]; j++) +- if (elf_hwcap & (1 << j)) ++ if (cpu_have_feature(j)) + seq_printf(m, " %s", hwcap_str[j]); + } + seq_puts(m, "\n"); +diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c +index bb048144c3bd..6972de5681ec 100644 +--- a/arch/arm64/kernel/fpsimd.c ++++ b/arch/arm64/kernel/fpsimd.c +@@ -1302,14 +1302,14 @@ static inline void fpsimd_hotplug_init(void) { } + */ + static int __init fpsimd_init(void) + { +- if (elf_hwcap & HWCAP_FP) { ++ if (cpu_have_named_feature(FP)) { + fpsimd_pm_init(); + fpsimd_hotplug_init(); + } else { + pr_notice("Floating-point is not implemented\n"); + } + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + pr_notice("Advanced SIMD is not implemented\n"); + + return sve_sysctl_init(); +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index 58863fd9c91b..fbfc81932dea 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -825,7 +825,11 @@ static void arch_timer_evtstrm_enable(int divider) + cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) + | ARCH_TIMER_VIRT_EVT_EN; + arch_timer_set_cntkctl(cntkctl); ++#ifdef CONFIG_ARM64 ++ cpu_set_named_feature(EVTSTRM); ++#else + elf_hwcap |= HWCAP_EVTSTRM; ++#endif + #ifdef CONFIG_AARCH32_EL0 + a32_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; + #endif +@@ -1059,7 +1063,11 @@ static int arch_timer_cpu_pm_notify(struct notifier_block *self, + } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) { + arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl)); + ++#ifdef CONFIG_ARM64 ++ if (cpu_have_named_feature(EVTSTRM)) ++#else + if (elf_hwcap & HWCAP_EVTSTRM) ++#endif + cpumask_set_cpu(smp_processor_id(), &evtstrm_available); + } + return NOTIFY_OK; +-- +2.25.1 + diff --git a/patches/0098-arm64-Expose-SVE2-features-for-userspace.patch b/patches/0098-arm64-Expose-SVE2-features-for-userspace.patch new file mode 100644 index 000000000000..45f709f3fab0 --- /dev/null +++ b/patches/0098-arm64-Expose-SVE2-features-for-userspace.patch @@ -0,0 +1,275 @@ +From 2ba00283ddd367afa75f72e3b4de15f80b4a97a7 Mon Sep 17 00:00:00 2001 +From: Dave Martin <Dave.Martin(a)arm.com> +Date: Thu, 18 Apr 2019 18:41:38 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 2/4] arm64: Expose SVE2 features for + userspace + +mainline inclusion +from mainline-v5.2-rc1 +commit 06a916feca2b262ab0c1a2aeb68882f4b1108a07 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +This patch provides support for reporting the presence of SVE2 and +its optional features to userspace. + +This will also enable visibility of SVE2 for guests, when KVM +support for SVE-enabled guests is available. + +Signed-off-by: Dave Martin <Dave.Martin(a)arm.com> +Signed-off-by: Will Deacon <will.deacon(a)arm.com> + +Conflicts: + arch/arm64/include/asm/hwcap.h + arch/arm64/include/uapi/asm/hwcap.h + arch/arm64/kernel/cpuinfo.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + Documentation/arm64/cpu-feature-registers.txt | 16 +++++++++++++ + Documentation/arm64/elf_hwcaps.txt | 24 +++++++++++++++++++ + Documentation/arm64/sve.txt | 17 +++++++++++++ + arch/arm64/Kconfig | 3 +++ + arch/arm64/include/asm/hwcap.h | 6 +++++ + arch/arm64/include/asm/sysreg.h | 14 +++++++++++ + arch/arm64/include/uapi/asm/hwcap.h | 10 ++++++++ + arch/arm64/kernel/cpufeature.c | 17 ++++++++++++- + arch/arm64/kernel/cpuinfo.c | 10 ++++++++ + 9 files changed, 116 insertions(+), 1 deletion(-) + +diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt +index 7964f03846b1..fcd2e1deb886 100644 +--- a/Documentation/arm64/cpu-feature-registers.txt ++++ b/Documentation/arm64/cpu-feature-registers.txt +@@ -201,6 +201,22 @@ infrastructure: + | AT | [35-32] | y | + x--------------------------------------------------x + ++ 6) ID_AA64ZFR0_EL1 - SVE feature ID register 0 ++ ++ x--------------------------------------------------x ++ | Name | bits | visible | ++ |--------------------------------------------------| ++ | SM4 | [43-40] | y | ++ |--------------------------------------------------| ++ | SHA3 | [35-32] | y | ++ |--------------------------------------------------| ++ | BitPerm | [19-16] | y | ++ |--------------------------------------------------| ++ | AES | [7-4] | y | ++ |--------------------------------------------------| ++ | SVEVer | [3-0] | y | ++ x--------------------------------------------------x ++ + Appendix I: Example + --------------------------- + +diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt +index 186feb16e2f2..e2ce14dfccf2 100644 +--- a/Documentation/arm64/elf_hwcaps.txt ++++ b/Documentation/arm64/elf_hwcaps.txt +@@ -159,6 +159,30 @@ HWCAP_SVE + + Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001. + ++HWCAP2_SVE2 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. ++ ++HWCAP2_SVEAES ++ ++ Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. ++ ++HWCAP2_SVEPMULL ++ ++ Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. ++ ++HWCAP2_SVEBITPERM ++ ++ Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. ++ ++HWCAP2_SVESHA3 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. ++ ++HWCAP2_SVESM4 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. ++ + HWCAP_ASIMDFHM + + Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001. +diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt +index 2001d84384ca..5689fc9a976a 100644 +--- a/Documentation/arm64/sve.txt ++++ b/Documentation/arm64/sve.txt +@@ -34,6 +34,23 @@ model features for SVE is included in Appendix A. + following sections: software that needs to verify that those interfaces are + present must check for HWCAP_SVE instead. + ++* On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also ++ be reported in the AT_HWCAP2 aux vector entry. In addition to this, ++ optional extensions to SVE2 may be reported by the presence of: ++ ++ HWCAP2_SVE2 ++ HWCAP2_SVEAES ++ HWCAP2_SVEPMULL ++ HWCAP2_SVEBITPERM ++ HWCAP2_SVESHA3 ++ HWCAP2_SVESM4 ++ ++ This list may be extended over time as the SVE architecture evolves. ++ ++ These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1, ++ which userspace can read using an MRS instruction. See elf_hwcaps.txt and ++ cpu-feature-registers.txt for details. ++ + * Debuggers should restrict themselves to interacting with the target via the + NT_ARM_SVE regset. The recommended way of detecting support for this regset + is to connect to a target process first and then attempt a +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 88b8031a93b2..f7398a1904a2 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1316,6 +1316,9 @@ config ARM64_SVE + + To enable use of this extension on CPUs that implement it, say Y. + ++ On CPUs that support the SVE2 extensions, this option will enable ++ those too. ++ + Note that for architectural reasons, firmware _must_ implement SVE + support when running on SVE capable hardware. The required support + is present in: +diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h +index 458ff2d7ece3..08315a3bf387 100644 +--- a/arch/arm64/include/asm/hwcap.h ++++ b/arch/arm64/include/asm/hwcap.h +@@ -85,6 +85,12 @@ + #define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS) + + #define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 32) ++#define KERNEL_HWCAP_SVE2 __khwcap2_feature(SVE2) ++#define KERNEL_HWCAP_SVEAES __khwcap2_feature(SVEAES) ++#define KERNEL_HWCAP_SVEPMULL __khwcap2_feature(SVEPMULL) ++#define KERNEL_HWCAP_SVEBITPERM __khwcap2_feature(SVEBITPERM) ++#define KERNEL_HWCAP_SVESHA3 __khwcap2_feature(SVESHA3) ++#define KERNEL_HWCAP_SVESM4 __khwcap2_feature(SVESM4) + + /* + * This yields a mask that user programs can use to figure out what +diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h +index 0fd51d253648..69618e602ed8 100644 +--- a/arch/arm64/include/asm/sysreg.h ++++ b/arch/arm64/include/asm/sysreg.h +@@ -564,6 +564,20 @@ + #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 + #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 + ++/* id_aa64zfr0 */ ++#define ID_AA64ZFR0_SM4_SHIFT 40 ++#define ID_AA64ZFR0_SHA3_SHIFT 32 ++#define ID_AA64ZFR0_BITPERM_SHIFT 16 ++#define ID_AA64ZFR0_AES_SHIFT 4 ++#define ID_AA64ZFR0_SVEVER_SHIFT 0 ++ ++#define ID_AA64ZFR0_SM4 0x1 ++#define ID_AA64ZFR0_SHA3 0x1 ++#define ID_AA64ZFR0_BITPERM 0x1 ++#define ID_AA64ZFR0_AES 0x1 ++#define ID_AA64ZFR0_AES_PMULL 0x2 ++#define ID_AA64ZFR0_SVEVER_SVE2 0x1 ++ + /* id_aa64mmfr0 */ + #define ID_AA64MMFR0_TGRAN4_SHIFT 28 + #define ID_AA64MMFR0_TGRAN64_SHIFT 24 +diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h +index 602158a55554..fea93415b493 100644 +--- a/arch/arm64/include/uapi/asm/hwcap.h ++++ b/arch/arm64/include/uapi/asm/hwcap.h +@@ -50,4 +50,14 @@ + #define HWCAP_FLAGM (1 << 27) + #define HWCAP_SSBS (1 << 28) + ++/* ++ * HWCAP2 flags - for AT_HWCAP2 ++ */ ++#define HWCAP2_SVE2 (1 << 1) ++#define HWCAP2_SVEAES (1 << 2) ++#define HWCAP2_SVEPMULL (1 << 3) ++#define HWCAP2_SVEBITPERM (1 << 4) ++#define HWCAP2_SVESHA3 (1 << 5) ++#define HWCAP2_SVESM4 (1 << 6) ++ + #endif /* _UAPI__ASM_HWCAP_H */ +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 3a0e7e10f2d7..4f384bbd86c7 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -183,6 +183,15 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + ARM64_FTR_END, + }; + ++static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), ++ ARM64_FTR_END, ++}; ++ + static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { + /* + * We already refuse to boot CPUs that don't support our configured +@@ -399,7 +408,7 @@ static const struct __ftr_reg_entry { + /* Op1 = 0, CRn = 0, CRm = 4 */ + ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), + ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), +- ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), ++ ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), + + /* Op1 = 0, CRn = 0, CRm = 5 */ + ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), +@@ -1580,6 +1589,12 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { + HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), + #ifdef CONFIG_ARM64_SVE + HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), + #endif + HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), + {}, +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index bfe3bb8f05fe..c8e4ddd23f0c 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -82,6 +82,16 @@ static const char *const hwcap_str[] = { + "ilrcpc", + "flagm", + "ssbs", ++ "sb", ++ "paca", ++ "pacg", ++ "dcpodp", ++ "sve2", ++ "sveaes", ++ "svepmull", ++ "svebitperm", ++ "svesha3", ++ "svesm4", + NULL + }; + +-- +2.25.1 + diff --git a/patches/0044-Revert-perf-hisi-Add-support-for-HiSilicon-SoC-LPDDR.patch b/patches/0099-Expose-SVE2-features-for-userspace.patch similarity index 100% rename from patches/0044-Revert-perf-hisi-Add-support-for-HiSilicon-SoC-LPDDR.patch rename to patches/0099-Expose-SVE2-features-for-userspace.patch diff --git a/patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch b/patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch new file mode 100644 index 000000000000..7df40531adda --- /dev/null +++ b/patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch @@ -0,0 +1,67 @@ +From 515c2917ae3bc768e8793dac6b27ea4dff36b40c Mon Sep 17 00:00:00 2001 +From: Julien Grall <julien.grall(a)arm.com> +Date: Mon, 14 Oct 2019 11:21:13 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 4/4] arm64: cpufeature: Treat + ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled + +mainline inclusion +from mainline-v5.4-rc4 +commit ec52c7134b1fcef0edfc56d55072fd4f261ef198 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +If CONFIG_ARM64_SVE=n then we fail to report ID_AA64ZFR0_EL1 as 0 when +read by userspace, despite being required by the architecture. Although +this is theoretically a change in ABI, userspace will first check for +the presence of SVE via the HWCAP or the ID_AA64PFR0_EL1.SVE field +before probing the ID_AA64ZFR0_EL1 register. Given that these are +reported correctly for this configuration, we can safely tighten up the +current behaviour. + +Ensure ID_AA64ZFR0_EL1 is treated as RAZ when CONFIG_ARM64_SVE=n. + +Signed-off-by: Julien Grall <julien.grall(a)arm.com> +Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> +Reviewed-by: Mark Rutland <mark.rutland(a)arm.com> +Reviewed-by: Dave Martin <dave.martin(a)arm.com> +Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace") +Signed-off-by: Will Deacon <will(a)kernel.org> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + arch/arm64/kernel/cpufeature.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 8e7473df2660..98a8b2703f84 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -184,11 +184,16 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + }; + + static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), + ARM64_FTR_END, + }; + +-- +2.25.1 + diff --git a/series.conf b/series.conf index 987dcc1adad1..acdead12c1e2 100644 --- a/series.conf +++ b/series.conf @@ -98,3 +98,7 @@ patches/0093-Revert-perf-smmuv3_pmu-Enable-HiSilicon-Erratum-1620.patch patches/0094-perf-smmuv3-Enable-HiSilicon-Erratum-162001800-quirk.patch patches/0095-perf-smmuv3-Enable-HiSilicon-Erratum-162001900-quirk.patch patches/0096-perf-smmuv3-Add-MODULE_ALIAS-for-module-auto-loading.patch +patches/0097-arm64-HWCAP-add-support-for-AT_HWCAP2.patch +patches/0098-arm64-Expose-SVE2-features-for-userspace.patch +patches/0099-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch +patches/0100-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch -- 2.25.1

2 1

[PATCH openEuler-20.03-LTS-SP4] support CPU turbo
by Yu Liao 01 Nov '23

01 Nov '23

--- kernel.spec | 8 +- ...rm64-HWCAP-add-support-for-AT_HWCAP2.patch | 463 ++++++++++++++++++ ...4-Expose-SVE2-features-for-userspace.patch | 275 +++++++++++ ...-Fix-missing-ZFR0-in-__read_sysreg_b.patch | 55 +++ ...-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch | 67 +++ series.conf | 4 + 6 files changed, 871 insertions(+), 1 deletion(-) create mode 100644 patches/0042-arm64-HWCAP-add-support-for-AT_HWCAP2.patch create mode 100644 patches/0043-arm64-Expose-SVE2-features-for-userspace.patch create mode 100644 patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch create mode 100644 patches/0045-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch diff --git a/kernel.spec b/kernel.spec index 1a8ad37c95d8..e3d408f7b6b4 100644 --- a/kernel.spec +++ b/kernel.spec @@ -32,7 +32,7 @@ Name: kernel Version: 4.19.90 -Release: %{hulkrelease}.0229 +Release: %{hulkrelease}.0230 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -832,6 +832,12 @@ fi %changelog +* Wed Nov 1 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2310.4.0.0230 +- arm64: HWCAP: add support for AT_HWCAP2 +- arm64: Expose SVE2 features for userspace +- arm64: cpufeature: Fix missing ZFR0 in __read_sysreg_by_encoding() +- arm64: cpufeature: Treat ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled + * Tue Oct 31 2023 Yu Liao <liaoyu15(a)huawei.com> - 4.19.90-2310.4.0.0229 - add new line at the end of series.conf diff --git a/patches/0042-arm64-HWCAP-add-support-for-AT_HWCAP2.patch b/patches/0042-arm64-HWCAP-add-support-for-AT_HWCAP2.patch new file mode 100644 index 000000000000..46effba895fb --- /dev/null +++ b/patches/0042-arm64-HWCAP-add-support-for-AT_HWCAP2.patch @@ -0,0 +1,463 @@ +From a97497b283894653e53f7eb83b5825f5564d1614 Mon Sep 17 00:00:00 2001 +From: Andrew Murray <andrew.murray(a)arm.com> +Date: Tue, 9 Apr 2019 10:52:40 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 1/4] arm64: HWCAP: add support for + AT_HWCAP2 + +mainline inclusion +from mainline-v5.2-rc1 +commit 06a916feca2b262ab0c1a2aeb68882f4b1108a07 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +As we will exhaust the first 32 bits of AT_HWCAP let's start +exposing AT_HWCAP2 to userspace to give us up to 64 caps. + +Whilst it's possible to use the remaining 32 bits of AT_HWCAP, we +prefer to expand into AT_HWCAP2 in order to provide a consistent +view to userspace between ILP32 and LP64. However internal to the +kernel we prefer to continue to use the full space of elf_hwcap. + +To reduce complexity and allow for future expansion, we now +represent hwcaps in the kernel as ordinals and use a +KERNEL_HWCAP_ prefix. This allows us to support automatic feature +based module loading for all our hwcaps. + +We introduce cpu_set_feature to set hwcaps which complements the +existing cpu_have_feature helper. These helpers allow us to clean +up existing direct uses of elf_hwcap and reduce any future effort +required to move beyond 64 caps. + +For convenience we also introduce cpu_{have,set}_named_feature which +makes use of the cpu_feature macro to allow providing a hwcap name +without a {KERNEL_}HWCAP_ prefix. + +Signed-off-by: Andrew Murray <andrew.murray(a)arm.com> +[will: use const_ilog2() and tweak documentation] +Signed-off-by: Will Deacon <will.deacon(a)arm.com> + +Conflicts: + Documentation/arm64/elf_hwcaps.txt + arch/arm64/crypto/chacha-neon-glue.c + arch/arm64/crypto/crct10dif-ce-glue.c + arch/arm64/crypto/ghash-ce-glue.c + arch/arm64/crypto/nhpoly1305-neon-glue.c + arch/arm64/kernel/cpufeature.c + drivers/clocksource/arm_arch_timer.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + Documentation/arm64/elf_hwcaps.txt | 13 ++++-- + arch/arm64/crypto/aes-ce-ccm-glue.c | 2 +- + arch/arm64/crypto/aes-neonbs-glue.c | 2 +- + arch/arm64/crypto/chacha20-neon-glue.c | 2 +- + arch/arm64/crypto/ghash-ce-glue.c | 6 +-- + arch/arm64/crypto/sha256-glue.c | 4 +- + arch/arm64/include/asm/cpufeature.h | 22 +++++----- + arch/arm64/include/asm/hwcap.h | 49 ++++++++++++++++++++- + arch/arm64/include/uapi/asm/hwcap.h | 2 +- + arch/arm64/kernel/cpufeature.c | 60 +++++++++++++------------- + arch/arm64/kernel/cpuinfo.c | 2 +- + arch/arm64/kernel/fpsimd.c | 4 +- + drivers/clocksource/arm_arch_timer.c | 8 ++++ + 13 files changed, 120 insertions(+), 56 deletions(-) + +diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt +index 6feaffe90e22..186feb16e2f2 100644 +--- a/Documentation/arm64/elf_hwcaps.txt ++++ b/Documentation/arm64/elf_hwcaps.txt +@@ -13,9 +13,9 @@ architected discovery mechanism available to userspace code at EL0. The + kernel exposes the presence of these features to userspace through a set + of flags called hwcaps, exposed in the auxilliary vector. + +-Userspace software can test for features by acquiring the AT_HWCAP entry +-of the auxilliary vector, and testing whether the relevant flags are +-set, e.g. ++Userspace software can test for features by acquiring the AT_HWCAP or ++AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant ++flags are set, e.g. + + bool floating_point_is_present(void) + { +@@ -182,3 +182,10 @@ HWCAP_FLAGM + HWCAP_SSBS + + Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010. ++ ++ ++4. Unused AT_HWCAP bits ++----------------------- ++ ++For interoperation with userspace, the kernel guarantees that bits 62 ++and 63 of AT_HWCAP will always be returned as 0. +diff --git a/arch/arm64/crypto/aes-ce-ccm-glue.c b/arch/arm64/crypto/aes-ce-ccm-glue.c +index 5fc6f51908fd..036ea77f83bc 100644 +--- a/arch/arm64/crypto/aes-ce-ccm-glue.c ++++ b/arch/arm64/crypto/aes-ce-ccm-glue.c +@@ -372,7 +372,7 @@ static struct aead_alg ccm_aes_alg = { + + static int __init aes_mod_init(void) + { +- if (!(elf_hwcap & HWCAP_AES)) ++ if (!cpu_have_named_feature(AES)) + return -ENODEV; + return crypto_register_aead(&ccm_aes_alg); + } +diff --git a/arch/arm64/crypto/aes-neonbs-glue.c b/arch/arm64/crypto/aes-neonbs-glue.c +index 5cc248967387..742359801559 100644 +--- a/arch/arm64/crypto/aes-neonbs-glue.c ++++ b/arch/arm64/crypto/aes-neonbs-glue.c +@@ -442,7 +442,7 @@ static int __init aes_init(void) + int err; + int i; + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + + err = crypto_register_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); +diff --git a/arch/arm64/crypto/chacha20-neon-glue.c b/arch/arm64/crypto/chacha20-neon-glue.c +index 727579c93ded..bb3314905bee 100644 +--- a/arch/arm64/crypto/chacha20-neon-glue.c ++++ b/arch/arm64/crypto/chacha20-neon-glue.c +@@ -114,7 +114,7 @@ static struct skcipher_alg alg = { + + static int __init chacha20_simd_mod_init(void) + { +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + + return crypto_register_skcipher(&alg); +diff --git a/arch/arm64/crypto/ghash-ce-glue.c b/arch/arm64/crypto/ghash-ce-glue.c +index 1ed227bf6106..cd9d743cb40f 100644 +--- a/arch/arm64/crypto/ghash-ce-glue.c ++++ b/arch/arm64/crypto/ghash-ce-glue.c +@@ -648,10 +648,10 @@ static int __init ghash_ce_mod_init(void) + { + int ret; + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + return -ENODEV; + +- if (elf_hwcap & HWCAP_PMULL) ++ if (cpu_have_named_feature(PMULL)) + pmull_ghash_update = pmull_ghash_update_p64; + + else +@@ -661,7 +661,7 @@ static int __init ghash_ce_mod_init(void) + if (ret) + return ret; + +- if (elf_hwcap & HWCAP_PMULL) { ++ if (cpu_have_named_feature(PMULL)) { + ret = crypto_register_aead(&gcm_aes_alg); + if (ret) + crypto_unregister_shash(&ghash_alg); +diff --git a/arch/arm64/crypto/sha256-glue.c b/arch/arm64/crypto/sha256-glue.c +index 4aedeaefd61f..0cccdb9cc2c0 100644 +--- a/arch/arm64/crypto/sha256-glue.c ++++ b/arch/arm64/crypto/sha256-glue.c +@@ -173,7 +173,7 @@ static int __init sha256_mod_init(void) + if (ret) + return ret; + +- if (elf_hwcap & HWCAP_ASIMD) { ++ if (cpu_have_named_feature(ASIMD)) { + ret = crypto_register_shashes(neon_algs, ARRAY_SIZE(neon_algs)); + if (ret) + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); +@@ -183,7 +183,7 @@ static int __init sha256_mod_init(void) + + static void __exit sha256_mod_fini(void) + { +- if (elf_hwcap & HWCAP_ASIMD) ++ if (cpu_have_named_feature(ASIMD)) + crypto_unregister_shashes(neon_algs, ARRAY_SIZE(neon_algs)); + crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); + } +diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h +index ffb0a1ec0088..eef5a9c9b823 100644 +--- a/arch/arm64/include/asm/cpufeature.h ++++ b/arch/arm64/include/asm/cpufeature.h +@@ -14,15 +14,8 @@ + #include <asm/hwcap.h> + #include <asm/sysreg.h> + +-/* +- * In the arm64 world (as in the ARM world), elf_hwcap is used both internally +- * in the kernel and for user space to keep track of which optional features +- * are supported by the current system. So let's map feature 'x' to HWCAP_x. +- * Note that HWCAP_x constants are bit fields so we need to take the log. +- */ +- +-#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap)) +-#define cpu_feature(x) ilog2(HWCAP_ ## x) ++#define MAX_CPU_FEATURES 64 ++#define cpu_feature(x) KERNEL_HWCAP_ ## x + + #ifndef __ASSEMBLY__ + +@@ -372,10 +365,19 @@ extern bool set_cap_spectre_bhb; + + bool this_cpu_has_cap(unsigned int cap); + ++static inline void cpu_set_feature(unsigned int num) ++{ ++ WARN_ON(num >= MAX_CPU_FEATURES); ++ elf_hwcap |= BIT(num); ++} ++#define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name)) ++ + static inline bool cpu_have_feature(unsigned int num) + { +- return elf_hwcap & (1UL << num); ++ WARN_ON(num >= MAX_CPU_FEATURES); ++ return elf_hwcap & BIT(num); + } ++#define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name)) + + /* System capability check for constant caps */ + static __always_inline bool __cpus_have_const_cap(int num) +diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h +index 428b745b5386..458ff2d7ece3 100644 +--- a/arch/arm64/include/asm/hwcap.h ++++ b/arch/arm64/include/asm/hwcap.h +@@ -40,11 +40,58 @@ + #define COMPAT_HWCAP2_CRC32 (1 << 4) + + #ifndef __ASSEMBLY__ ++#include <linux/kernel.h> ++#include <linux/log2.h> ++ ++/* ++ * For userspace we represent hwcaps as a collection of HWCAP{,2}_x bitfields ++ * as described in uapi/asm/hwcap.h. For the kernel we represent hwcaps as ++ * natural numbers (in a single range of size MAX_CPU_FEATURES) defined here ++ * with prefix KERNEL_HWCAP_ mapped to their HWCAP{,2}_x counterpart. ++ * ++ * Hwcaps should be set and tested within the kernel via the ++ * cpu_{set,have}_named_feature(feature) where feature is the unique suffix ++ * of KERNEL_HWCAP_{feature}. ++ */ ++#define __khwcap_feature(x) const_ilog2(HWCAP_ ## x) ++#define KERNEL_HWCAP_FP __khwcap_feature(FP) ++#define KERNEL_HWCAP_ASIMD __khwcap_feature(ASIMD) ++#define KERNEL_HWCAP_EVTSTRM __khwcap_feature(EVTSTRM) ++#define KERNEL_HWCAP_AES __khwcap_feature(AES) ++#define KERNEL_HWCAP_PMULL __khwcap_feature(PMULL) ++#define KERNEL_HWCAP_SHA1 __khwcap_feature(SHA1) ++#define KERNEL_HWCAP_SHA2 __khwcap_feature(SHA2) ++#define KERNEL_HWCAP_CRC32 __khwcap_feature(CRC32) ++#define KERNEL_HWCAP_ATOMICS __khwcap_feature(ATOMICS) ++#define KERNEL_HWCAP_FPHP __khwcap_feature(FPHP) ++#define KERNEL_HWCAP_ASIMDHP __khwcap_feature(ASIMDHP) ++#define KERNEL_HWCAP_CPUID __khwcap_feature(CPUID) ++#define KERNEL_HWCAP_ASIMDRDM __khwcap_feature(ASIMDRDM) ++#define KERNEL_HWCAP_JSCVT __khwcap_feature(JSCVT) ++#define KERNEL_HWCAP_FCMA __khwcap_feature(FCMA) ++#define KERNEL_HWCAP_LRCPC __khwcap_feature(LRCPC) ++#define KERNEL_HWCAP_DCPOP __khwcap_feature(DCPOP) ++#define KERNEL_HWCAP_SHA3 __khwcap_feature(SHA3) ++#define KERNEL_HWCAP_SM3 __khwcap_feature(SM3) ++#define KERNEL_HWCAP_SM4 __khwcap_feature(SM4) ++#define KERNEL_HWCAP_ASIMDDP __khwcap_feature(ASIMDDP) ++#define KERNEL_HWCAP_SHA512 __khwcap_feature(SHA512) ++#define KERNEL_HWCAP_SVE __khwcap_feature(SVE) ++#define KERNEL_HWCAP_ASIMDFHM __khwcap_feature(ASIMDFHM) ++#define KERNEL_HWCAP_DIT __khwcap_feature(DIT) ++#define KERNEL_HWCAP_USCAT __khwcap_feature(USCAT) ++#define KERNEL_HWCAP_ILRCPC __khwcap_feature(ILRCPC) ++#define KERNEL_HWCAP_FLAGM __khwcap_feature(FLAGM) ++#define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS) ++ ++#define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 32) ++ + /* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +-#define ELF_HWCAP (elf_hwcap) ++#define ELF_HWCAP lower_32_bits(elf_hwcap) ++#define ELF_HWCAP2 upper_32_bits(elf_hwcap) + + #ifdef CONFIG_AARCH32_EL0 + extern unsigned int a32_elf_hwcap, a32_elf_hwcap2; +diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h +index 2bcd6e4f3474..602158a55554 100644 +--- a/arch/arm64/include/uapi/asm/hwcap.h ++++ b/arch/arm64/include/uapi/asm/hwcap.h +@@ -18,7 +18,7 @@ + #define _UAPI__ASM_HWCAP_H + + /* +- * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP ++ * HWCAP flags - for AT_HWCAP + */ + #define HWCAP_FP (1 << 0) + #define HWCAP_ASIMD (1 << 1) +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 1c93cc3f7692..3a0e7e10f2d7 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1553,35 +1553,35 @@ static const struct arm64_cpu_capabilities arm64_features[] = { + } + + static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM), +- HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), +- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC), +- HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), ++ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), ++ HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), + #ifdef CONFIG_ARM64_SVE +- HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), ++ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), + #endif +- HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS), ++ HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), + {}, + }; + +@@ -1627,7 +1627,7 @@ static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) + { + switch (cap->hwcap_type) { + case CAP_HWCAP: +- elf_hwcap |= cap->hwcap; ++ cpu_set_feature(cap->hwcap); + break; + #ifdef CONFIG_AARCH32_EL0 + case CAP_COMPAT_HWCAP: +@@ -1650,7 +1650,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) + + switch (cap->hwcap_type) { + case CAP_HWCAP: +- rc = (elf_hwcap & cap->hwcap) != 0; ++ rc = cpu_have_feature(cap->hwcap); + break; + #ifdef CONFIG_AARCH32_EL0 + case CAP_COMPAT_HWCAP: +@@ -1671,7 +1671,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) + static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) + { + /* We support emulation of accesses to CPU ID feature registers */ +- elf_hwcap |= HWCAP_CPUID; ++ cpu_set_named_feature(CPUID); + for (; hwcaps->matches; hwcaps++) + if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) + cap_set_elf_hwcap(hwcaps); +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index 005d88db1082..bfe3bb8f05fe 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -164,7 +164,7 @@ static int c_show(struct seq_file *m, void *v) + #endif /* CONFIG_AARCH32_EL0 */ + } else { + for (j = 0; hwcap_str[j]; j++) +- if (elf_hwcap & (1 << j)) ++ if (cpu_have_feature(j)) + seq_printf(m, " %s", hwcap_str[j]); + } + seq_puts(m, "\n"); +diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c +index bb048144c3bd..6972de5681ec 100644 +--- a/arch/arm64/kernel/fpsimd.c ++++ b/arch/arm64/kernel/fpsimd.c +@@ -1302,14 +1302,14 @@ static inline void fpsimd_hotplug_init(void) { } + */ + static int __init fpsimd_init(void) + { +- if (elf_hwcap & HWCAP_FP) { ++ if (cpu_have_named_feature(FP)) { + fpsimd_pm_init(); + fpsimd_hotplug_init(); + } else { + pr_notice("Floating-point is not implemented\n"); + } + +- if (!(elf_hwcap & HWCAP_ASIMD)) ++ if (!cpu_have_named_feature(ASIMD)) + pr_notice("Advanced SIMD is not implemented\n"); + + return sve_sysctl_init(); +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index 58863fd9c91b..fbfc81932dea 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -825,7 +825,11 @@ static void arch_timer_evtstrm_enable(int divider) + cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) + | ARCH_TIMER_VIRT_EVT_EN; + arch_timer_set_cntkctl(cntkctl); ++#ifdef CONFIG_ARM64 ++ cpu_set_named_feature(EVTSTRM); ++#else + elf_hwcap |= HWCAP_EVTSTRM; ++#endif + #ifdef CONFIG_AARCH32_EL0 + a32_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; + #endif +@@ -1059,7 +1063,11 @@ static int arch_timer_cpu_pm_notify(struct notifier_block *self, + } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) { + arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl)); + ++#ifdef CONFIG_ARM64 ++ if (cpu_have_named_feature(EVTSTRM)) ++#else + if (elf_hwcap & HWCAP_EVTSTRM) ++#endif + cpumask_set_cpu(smp_processor_id(), &evtstrm_available); + } + return NOTIFY_OK; +-- +2.25.1 + diff --git a/patches/0043-arm64-Expose-SVE2-features-for-userspace.patch b/patches/0043-arm64-Expose-SVE2-features-for-userspace.patch new file mode 100644 index 000000000000..45f709f3fab0 --- /dev/null +++ b/patches/0043-arm64-Expose-SVE2-features-for-userspace.patch @@ -0,0 +1,275 @@ +From 2ba00283ddd367afa75f72e3b4de15f80b4a97a7 Mon Sep 17 00:00:00 2001 +From: Dave Martin <Dave.Martin(a)arm.com> +Date: Thu, 18 Apr 2019 18:41:38 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 2/4] arm64: Expose SVE2 features for + userspace + +mainline inclusion +from mainline-v5.2-rc1 +commit 06a916feca2b262ab0c1a2aeb68882f4b1108a07 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +This patch provides support for reporting the presence of SVE2 and +its optional features to userspace. + +This will also enable visibility of SVE2 for guests, when KVM +support for SVE-enabled guests is available. + +Signed-off-by: Dave Martin <Dave.Martin(a)arm.com> +Signed-off-by: Will Deacon <will.deacon(a)arm.com> + +Conflicts: + arch/arm64/include/asm/hwcap.h + arch/arm64/include/uapi/asm/hwcap.h + arch/arm64/kernel/cpuinfo.c + +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + Documentation/arm64/cpu-feature-registers.txt | 16 +++++++++++++ + Documentation/arm64/elf_hwcaps.txt | 24 +++++++++++++++++++ + Documentation/arm64/sve.txt | 17 +++++++++++++ + arch/arm64/Kconfig | 3 +++ + arch/arm64/include/asm/hwcap.h | 6 +++++ + arch/arm64/include/asm/sysreg.h | 14 +++++++++++ + arch/arm64/include/uapi/asm/hwcap.h | 10 ++++++++ + arch/arm64/kernel/cpufeature.c | 17 ++++++++++++- + arch/arm64/kernel/cpuinfo.c | 10 ++++++++ + 9 files changed, 116 insertions(+), 1 deletion(-) + +diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt +index 7964f03846b1..fcd2e1deb886 100644 +--- a/Documentation/arm64/cpu-feature-registers.txt ++++ b/Documentation/arm64/cpu-feature-registers.txt +@@ -201,6 +201,22 @@ infrastructure: + | AT | [35-32] | y | + x--------------------------------------------------x + ++ 6) ID_AA64ZFR0_EL1 - SVE feature ID register 0 ++ ++ x--------------------------------------------------x ++ | Name | bits | visible | ++ |--------------------------------------------------| ++ | SM4 | [43-40] | y | ++ |--------------------------------------------------| ++ | SHA3 | [35-32] | y | ++ |--------------------------------------------------| ++ | BitPerm | [19-16] | y | ++ |--------------------------------------------------| ++ | AES | [7-4] | y | ++ |--------------------------------------------------| ++ | SVEVer | [3-0] | y | ++ x--------------------------------------------------x ++ + Appendix I: Example + --------------------------- + +diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt +index 186feb16e2f2..e2ce14dfccf2 100644 +--- a/Documentation/arm64/elf_hwcaps.txt ++++ b/Documentation/arm64/elf_hwcaps.txt +@@ -159,6 +159,30 @@ HWCAP_SVE + + Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001. + ++HWCAP2_SVE2 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. ++ ++HWCAP2_SVEAES ++ ++ Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. ++ ++HWCAP2_SVEPMULL ++ ++ Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010. ++ ++HWCAP2_SVEBITPERM ++ ++ Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001. ++ ++HWCAP2_SVESHA3 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001. ++ ++HWCAP2_SVESM4 ++ ++ Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001. ++ + HWCAP_ASIMDFHM + + Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001. +diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt +index 2001d84384ca..5689fc9a976a 100644 +--- a/Documentation/arm64/sve.txt ++++ b/Documentation/arm64/sve.txt +@@ -34,6 +34,23 @@ model features for SVE is included in Appendix A. + following sections: software that needs to verify that those interfaces are + present must check for HWCAP_SVE instead. + ++* On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also ++ be reported in the AT_HWCAP2 aux vector entry. In addition to this, ++ optional extensions to SVE2 may be reported by the presence of: ++ ++ HWCAP2_SVE2 ++ HWCAP2_SVEAES ++ HWCAP2_SVEPMULL ++ HWCAP2_SVEBITPERM ++ HWCAP2_SVESHA3 ++ HWCAP2_SVESM4 ++ ++ This list may be extended over time as the SVE architecture evolves. ++ ++ These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1, ++ which userspace can read using an MRS instruction. See elf_hwcaps.txt and ++ cpu-feature-registers.txt for details. ++ + * Debuggers should restrict themselves to interacting with the target via the + NT_ARM_SVE regset. The recommended way of detecting support for this regset + is to connect to a target process first and then attempt a +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 88b8031a93b2..f7398a1904a2 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -1316,6 +1316,9 @@ config ARM64_SVE + + To enable use of this extension on CPUs that implement it, say Y. + ++ On CPUs that support the SVE2 extensions, this option will enable ++ those too. ++ + Note that for architectural reasons, firmware _must_ implement SVE + support when running on SVE capable hardware. The required support + is present in: +diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h +index 458ff2d7ece3..08315a3bf387 100644 +--- a/arch/arm64/include/asm/hwcap.h ++++ b/arch/arm64/include/asm/hwcap.h +@@ -85,6 +85,12 @@ + #define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS) + + #define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 32) ++#define KERNEL_HWCAP_SVE2 __khwcap2_feature(SVE2) ++#define KERNEL_HWCAP_SVEAES __khwcap2_feature(SVEAES) ++#define KERNEL_HWCAP_SVEPMULL __khwcap2_feature(SVEPMULL) ++#define KERNEL_HWCAP_SVEBITPERM __khwcap2_feature(SVEBITPERM) ++#define KERNEL_HWCAP_SVESHA3 __khwcap2_feature(SVESHA3) ++#define KERNEL_HWCAP_SVESM4 __khwcap2_feature(SVESM4) + + /* + * This yields a mask that user programs can use to figure out what +diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h +index 0fd51d253648..69618e602ed8 100644 +--- a/arch/arm64/include/asm/sysreg.h ++++ b/arch/arm64/include/asm/sysreg.h +@@ -564,6 +564,20 @@ + #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 + #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 + ++/* id_aa64zfr0 */ ++#define ID_AA64ZFR0_SM4_SHIFT 40 ++#define ID_AA64ZFR0_SHA3_SHIFT 32 ++#define ID_AA64ZFR0_BITPERM_SHIFT 16 ++#define ID_AA64ZFR0_AES_SHIFT 4 ++#define ID_AA64ZFR0_SVEVER_SHIFT 0 ++ ++#define ID_AA64ZFR0_SM4 0x1 ++#define ID_AA64ZFR0_SHA3 0x1 ++#define ID_AA64ZFR0_BITPERM 0x1 ++#define ID_AA64ZFR0_AES 0x1 ++#define ID_AA64ZFR0_AES_PMULL 0x2 ++#define ID_AA64ZFR0_SVEVER_SVE2 0x1 ++ + /* id_aa64mmfr0 */ + #define ID_AA64MMFR0_TGRAN4_SHIFT 28 + #define ID_AA64MMFR0_TGRAN64_SHIFT 24 +diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h +index 602158a55554..fea93415b493 100644 +--- a/arch/arm64/include/uapi/asm/hwcap.h ++++ b/arch/arm64/include/uapi/asm/hwcap.h +@@ -50,4 +50,14 @@ + #define HWCAP_FLAGM (1 << 27) + #define HWCAP_SSBS (1 << 28) + ++/* ++ * HWCAP2 flags - for AT_HWCAP2 ++ */ ++#define HWCAP2_SVE2 (1 << 1) ++#define HWCAP2_SVEAES (1 << 2) ++#define HWCAP2_SVEPMULL (1 << 3) ++#define HWCAP2_SVEBITPERM (1 << 4) ++#define HWCAP2_SVESHA3 (1 << 5) ++#define HWCAP2_SVESM4 (1 << 6) ++ + #endif /* _UAPI__ASM_HWCAP_H */ +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 3a0e7e10f2d7..4f384bbd86c7 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -183,6 +183,15 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + ARM64_FTR_END, + }; + ++static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), ++ ARM64_FTR_END, ++}; ++ + static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { + /* + * We already refuse to boot CPUs that don't support our configured +@@ -399,7 +408,7 @@ static const struct __ftr_reg_entry { + /* Op1 = 0, CRn = 0, CRm = 4 */ + ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), + ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), +- ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), ++ ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), + + /* Op1 = 0, CRn = 0, CRm = 5 */ + ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), +@@ -1580,6 +1589,12 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { + HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), + #ifdef CONFIG_ARM64_SVE + HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), ++ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), + #endif + HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), + {}, +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index bfe3bb8f05fe..c8e4ddd23f0c 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -82,6 +82,16 @@ static const char *const hwcap_str[] = { + "ilrcpc", + "flagm", + "ssbs", ++ "sb", ++ "paca", ++ "pacg", ++ "dcpodp", ++ "sve2", ++ "sveaes", ++ "svepmull", ++ "svebitperm", ++ "svesha3", ++ "svesm4", + NULL + }; + +-- +2.25.1 + diff --git a/patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch b/patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch new file mode 100644 index 000000000000..4ce008cecf19 --- /dev/null +++ b/patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch @@ -0,0 +1,55 @@ +From 9f8dff634365e7bfa0c764ccd31b54a4f0992bc8 Mon Sep 17 00:00:00 2001 +From: Dave Martin <Dave.Martin(a)arm.com> +Date: Mon, 3 Jun 2019 16:35:02 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 3/4] arm64: cpufeature: Fix missing + ZFR0 in __read_sysreg_by_encoding() + +mainline inclusion +from mainline-v5.2-rc4 +commit 78ed70bf3a923f1965e3c19f544677d418397108 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +In commit 06a916feca2b ("arm64: Expose SVE2 features for +userspace"), new hwcaps are added that are detected via fields in +the SVE-specific ID register ID_AA64ZFR0_EL1. + +In order to check compatibility of secondary cpus with the hwcaps +established at boot, the cpufeatures code uses +__read_sysreg_by_encoding() to read this ID register based on the +sys_reg field of the arm64_elf_hwcaps[] table. + +This leads to a kernel splat if an hwcap uses an ID register that +__read_sysreg_by_encoding() doesn't explicitly handle, as now +happens when exercising cpu hotplug on an SVE2-capable platform. + +So fix it by adding the required case in there. + +Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace") +Signed-off-by: Dave Martin <Dave.Martin(a)arm.com> +Signed-off-by: Will Deacon <will.deacon(a)arm.com> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + arch/arm64/kernel/cpufeature.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 4f384bbd86c7..8e7473df2660 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -828,6 +828,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) + + read_sysreg_case(SYS_ID_AA64PFR0_EL1); + read_sysreg_case(SYS_ID_AA64PFR1_EL1); ++ read_sysreg_case(SYS_ID_AA64ZFR0_EL1); + read_sysreg_case(SYS_ID_AA64DFR0_EL1); + read_sysreg_case(SYS_ID_AA64DFR1_EL1); + read_sysreg_case(SYS_ID_AA64MMFR0_EL1); +-- +2.25.1 + diff --git a/patches/0045-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch b/patches/0045-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch new file mode 100644 index 000000000000..7df40531adda --- /dev/null +++ b/patches/0045-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch @@ -0,0 +1,67 @@ +From 515c2917ae3bc768e8793dac6b27ea4dff36b40c Mon Sep 17 00:00:00 2001 +From: Julien Grall <julien.grall(a)arm.com> +Date: Mon, 14 Oct 2019 11:21:13 +0100 +Subject: [PATCH openEuler-20.03-LTS-SP4 4/4] arm64: cpufeature: Treat + ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled + +mainline inclusion +from mainline-v5.4-rc4 +commit ec52c7134b1fcef0edfc56d55072fd4f261ef198 +category: feature +bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O +CVE: NA + +Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… + +-------------------------------- + +If CONFIG_ARM64_SVE=n then we fail to report ID_AA64ZFR0_EL1 as 0 when +read by userspace, despite being required by the architecture. Although +this is theoretically a change in ABI, userspace will first check for +the presence of SVE via the HWCAP or the ID_AA64PFR0_EL1.SVE field +before probing the ID_AA64ZFR0_EL1 register. Given that these are +reported correctly for this configuration, we can safely tighten up the +current behaviour. + +Ensure ID_AA64ZFR0_EL1 is treated as RAZ when CONFIG_ARM64_SVE=n. + +Signed-off-by: Julien Grall <julien.grall(a)arm.com> +Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> +Reviewed-by: Mark Rutland <mark.rutland(a)arm.com> +Reviewed-by: Dave Martin <dave.martin(a)arm.com> +Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace") +Signed-off-by: Will Deacon <will(a)kernel.org> +Signed-off-by: Yu Liao <liaoyu15(a)huawei.com> +--- + arch/arm64/kernel/cpufeature.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 8e7473df2660..98a8b2703f84 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -184,11 +184,16 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + }; + + static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), +- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), ++ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), ++ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), + ARM64_FTR_END, + }; + +-- +2.25.1 + diff --git a/series.conf b/series.conf index 1470060a870a..32716ced5856 100644 --- a/series.conf +++ b/series.conf @@ -43,3 +43,7 @@ patches/0038-perf-arm-spe-Add-more-sub-classes-for-operation-pack.patch patches/0039-perf-arm_spe-Decode-memory-tagging-properties.patch patches/0040-perf-arm-spe-Add-support-for-ARMv8.3-SPE.patch patches/0041-drivers-perf-Add-support-for-ARMv8.3-SPE.patch +patches/0042-arm64-HWCAP-add-support-for-AT_HWCAP2.patch +patches/0043-arm64-Expose-SVE2-features-for-userspace.patch +patches/0044-arm64-cpufeature-Fix-missing-ZFR0-in-__read_sysreg_b.patch +patches/0045-arm64-cpufeature-Treat-ID_AA64ZFR0_EL1-as-RAZ-when-S.patch -- 2.25.1

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