August 2021 - Kernel - mailweb.openeuler.org

[PATCH kernel-4.19] selinux: fix NULL dereference in policydb_destroy()
by Yang Yingliang 12 Aug '21

12 Aug '21

From: Ondrej Mosnacek <omosnace(a)redhat.com> mainline inclusion from master commit 6a1afffb08ce5f9fb9ccc20f7ab24846c0142984 category: bugfix bugzilla: 120851 CVE: NA --------------------------- The conversion to kvmalloc() forgot to account for the possibility that p->type_attr_map_array might be null in policydb_destroy(). Fix this by destroying its contents only if it is not NULL. Also make sure ebitmap_init() is called on all entries before policydb_destroy() can be called. Right now this is a no-op, because both kvcalloc() and ebitmap_init() just zero out the whole struct, but let's rather not rely on a specific implementation. Reported-by: syzbot+a57b2aff60832666fc28(a)syzkaller.appspotmail.com Fixes: acdf52d97f82 ("selinux: convert to kvmalloc") Signed-off-by: Ondrej Mosnacek <omosnace(a)redhat.com> Acked-by: Stephen Smalley <sds(a)tycho.nsa.gov> Signed-off-by: Paul Moore <paul(a)paul-moore.com> Signed-off-by: Wang Weiyang <wangweiyang2(a)huawei.com> Conflicts: security/selinux/ss/policydb.c [ acdf52d97f82 is not applied so only half of this commit is used ] Reviewed-by: Xiu Jianfeng <xiujianfeng(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- security/selinux/ss/policydb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/security/selinux/ss/policydb.c b/security/selinux/ss/policydb.c index 91d259c87d10c..7fae43da8a647 100644 --- a/security/selinux/ss/policydb.c +++ b/security/selinux/ss/policydb.c @@ -2552,11 +2552,17 @@ int policydb_read(struct policydb *p, void *fp) if (rc) goto bad; + /* just in case ebitmap_init() becomes more than just a memset(0): */ for (i = 0; i < p->p_types.nprim; i++) { struct ebitmap *e = flex_array_get(p->type_attr_map_array, i); BUG_ON(!e); ebitmap_init(e); + } + + for (i = 0; i < p->p_types.nprim; i++) { + struct ebitmap *e = flex_array_get(p->type_attr_map_array, i); + if (p->policyvers >= POLICYDB_VERSION_AVTAB) { rc = ebitmap_read(e, fp); if (rc) -- 2.25.1

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Re: [kernel-4.19 2/2] uce: pagecache reading scenario support kernel recovery
by Xie XiuQi 11 Aug '21

11 Aug '21

Hi, Thanks for your patches. Overall it looks good to me, but it also needs committer's reviewed-by from memory and fs subsystem. Reviewed-by: Xie XiuQi <xiexiuqi(a)huawei.com> On 2021/8/11 11:37, Tong Tiangen wrote: > hulk inclusion > category: feature > bugzilla: https://gitee.com/openeuler/kernel/issues/I44REB > CVE: NA > > --------------------------- > > Support pagecache reading triggered by user-mode file access scenario > to kernel recovery. > > At the same time, in this patch, we solved the problem of process D > state caused by waiting for PG_writeback in memory_failure() (the > background writeback thread timed out while writing back to the disk on > the page with hardware error). In this case, our processing method is > panic system to avoid the business interruption for a long time caused > by the business process in D state. > > Signed-off-by: Tong Tiangen <tongtiangen(a)huawei.com> > Signed-off-by: Chen Huang <chenhuang5(a)huawei.com> > --- > arch/arm64/include/asm/exception.h | 1 + > arch/arm64/include/asm/thread_info.h | 8 + > arch/arm64/include/asm/uaccess.h | 8 + > arch/arm64/kernel/ras.c | 7 + > arch/arm64/lib/copy_template_generic_read.S | 193 ++++++++++++++++++++ > arch/arm64/lib/copy_to_user.S | 19 ++ > arch/arm64/mm/fault.c | 7 + > include/linux/mm.h | 3 + > include/linux/uio.h | 5 + > lib/iov_iter.c | 132 +++++++++++++ > mm/filemap.c | 8 +- > mm/internal.h | 1 + > mm/memory-failure.c | 7 + > 13 files changed, 398 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/lib/copy_template_generic_read.S > > diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h > index f938690c5ad6..559d86ad9e5d 100644 > --- a/arch/arm64/include/asm/exception.h > +++ b/arch/arm64/include/asm/exception.h > @@ -50,6 +50,7 @@ struct uce_kernel_recovery_info { > }; > > extern int copy_page_cow_sea_fallback(void); > +extern int copy_generic_read_sea_fallback(void); > #endif > > #endif /* __ASM_EXCEPTION_H */ > diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h > index 802a7d10ab82..b91fb7d6c18d 100644 > --- a/arch/arm64/include/asm/thread_info.h > +++ b/arch/arm64/include/asm/thread_info.h > @@ -93,6 +93,10 @@ void arch_release_task_struct(struct task_struct *tsk); > #define TIF_SVE_VL_INHERIT 24 /* Inherit sve_vl_onexec across exec */ > #define TIF_SSBD 25 /* Wants SSB mitigation */ > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +#define TIF_UCE_KERNEL_RECOVERY 26 > +#endif > + > #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) > #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) > #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) > @@ -110,6 +114,10 @@ void arch_release_task_struct(struct task_struct *tsk); > #define _TIF_SVE (1 << TIF_SVE) > #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +#define _TIF_UCE_KERNEL_RECOVERY (1 << TIF_UCE_KERNEL_RECOVERY) > +#endif > + > #define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \ > _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \ > _TIF_UPROBE | _TIF_FSCHECK | _TIF_SEA_NOTIFY) > diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h > index 35482c9076db..52d3c8c64849 100644 > --- a/arch/arm64/include/asm/uaccess.h > +++ b/arch/arm64/include/asm/uaccess.h > @@ -407,6 +407,14 @@ extern unsigned long __must_check __arch_copy_from_user(void *to, const void __u > __arch_copy_from_user((to), __uaccess_mask_ptr(from), (n)); \ > }) > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +extern unsigned long __must_check __arch_copy_to_user_generic_read(void __user *to, const void *from, unsigned long n); > +#define raw_copy_to_user_generic_read(to, from, n) \ > +({ \ > + __arch_copy_to_user_generic_read(__uaccess_mask_ptr(to), (from), (n)); \ > +}) > +#endif > + > extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); > #define raw_copy_to_user(to, from, n) \ > ({ \ > diff --git a/arch/arm64/kernel/ras.c b/arch/arm64/kernel/ras.c > index 181e609e1cd4..b57041f9e6e7 100644 > --- a/arch/arm64/kernel/ras.c > +++ b/arch/arm64/kernel/ras.c > @@ -92,6 +92,13 @@ void sea_notify_process(void) > if (!si) > panic("Lost physical address for consumed uncorrectable error"); > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > + if (test_thread_flag(TIF_UCE_KERNEL_RECOVERY)) { > + flags |= MF_UCE_KERNEL_RECOVERY; > + clear_thread_flag(TIF_UCE_KERNEL_RECOVERY); > + } > +#endif > + > clear_thread_flag(TIF_SEA_NOTIFY); > do { > pfn = si->paddr >> PAGE_SHIFT; > diff --git a/arch/arm64/lib/copy_template_generic_read.S b/arch/arm64/lib/copy_template_generic_read.S > new file mode 100644 > index 000000000000..287193527260 > --- /dev/null > +++ b/arch/arm64/lib/copy_template_generic_read.S > @@ -0,0 +1,193 @@ > +/* > + * Copyright (C) 2013 ARM Ltd. > + * Copyright (C) 2013 Linaro. > + * > + * This code is based on glibc cortex strings work originally authored by Linaro > + * and re-licensed under GPLv2 for the Linux kernel. The original code can > + * be found @ > + * > + * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/ > + * files/head:/src/aarch64/ > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > + > +/* > + * Copy a buffer from src to dest (alignment handled by the hardware) > + * > + * Parameters: > + * x0 - dest > + * x1 - src > + * x2 - n > + * Returns: > + * x0 - dest > + */ > +dstin .req x0 > +src .req x1 > +count .req x2 > +tmp1 .req x3 > +tmp1w .req w3 > +tmp2 .req x4 > +tmp2w .req w4 > +dst .req x6 > + > +A_l .req x7 > +A_h .req x8 > +B_l .req x9 > +B_h .req x10 > +C_l .req x11 > +C_h .req x12 > +D_l .req x13 > +D_h .req x14 > + > + mov dst, dstin > + cmp count, #16 > + /*When memory length is less than 16, the accessed are not aligned.*/ > + b.lo .Ltiny15_gr > + > + neg tmp2, src > + ands tmp2, tmp2, #15/* Bytes to reach alignment. */ > + b.eq .LSrcAligned_gr > + sub count, count, tmp2 > + /* > + * Copy the leading memory data from src to dst in an increasing > + * address order.By this way,the risk of overwriting the source > + * memory data is eliminated when the distance between src and > + * dst is less than 16. The memory accesses here are alignment. > + */ > + tbz tmp2, #0, 1f > + ldrb1 tmp1w, src, #1 > + strb1 tmp1w, dst, #1 > +1: > + tbz tmp2, #1, 2f > + ldrh1 tmp1w, src, #2 > + strh1 tmp1w, dst, #2 > +2: > + tbz tmp2, #2, 3f > + ldr1 tmp1w, src, #4 > + str1 tmp1w, dst, #4 > +3: > + tbz tmp2, #3, .LSrcAligned_gr > + ldr1 tmp1, src, #8 > + str1 tmp1, dst, #8 > + > +.LSrcAligned_gr: > + cmp count, #64 > + b.ge .Lcpy_over64_gr > + /* > + * Deal with small copies quickly by dropping straight into the > + * exit block. > + */ > +.Ltail63_gr: > + /* > + * Copy up to 48 bytes of data. At this point we only need the > + * bottom 6 bits of count to be accurate. > + */ > + ands tmp1, count, #0x30 > + b.eq .Ltiny15_gr > + cmp tmp1w, #0x20 > + b.eq 1f > + b.lt 2f > + ldp1 A_l, A_h, src, #16 > + stp1 A_l, A_h, dst, #16 > +1: > + ldp1 A_l, A_h, src, #16 > + stp1 A_l, A_h, dst, #16 > +2: > + ldp1 A_l, A_h, src, #16 > + stp1 A_l, A_h, dst, #16 > +.Ltiny15_gr: > + /* > + * Prefer to break one ldp/stp into several load/store to access > + * memory in an increasing address order,rather than to load/store 16 > + * bytes from (src-16) to (dst-16) and to backward the src to aligned > + * address,which way is used in original cortex memcpy. If keeping > + * the original memcpy process here, memmove need to satisfy the > + * precondition that src address is at least 16 bytes bigger than dst > + * address,otherwise some source data will be overwritten when memove > + * call memcpy directly. To make memmove simpler and decouple the > + * memcpy's dependency on memmove, withdrew the original process. > + */ > + tbz count, #3, 1f > + ldr1 tmp1, src, #8 > + str1 tmp1, dst, #8 > +1: > + tbz count, #2, 2f > + ldr1 tmp1w, src, #4 > + str1 tmp1w, dst, #4 > +2: > + tbz count, #1, 3f > + ldrh1 tmp1w, src, #2 > + strh1 tmp1w, dst, #2 > +3: > + tbz count, #0, .Lexitfunc_gr > + ldrb1 tmp1w, src, #1 > + strb1 tmp1w, dst, #1 > + > + b .Lexitfunc_gr > + > +.Lcpy_over64_gr: > + subs count, count, #128 > + b.ge .Lcpy_body_large_gr > + /* > + * Less than 128 bytes to copy, so handle 64 here and then jump > + * to the tail. > + */ > + ldp1 A_l, A_h, src, #16 > + stp1 A_l, A_h, dst, #16 > + ldp1 B_l, B_h, src, #16 > + ldp1 C_l, C_h, src, #16 > + stp1 B_l, B_h, dst, #16 > + stp1 C_l, C_h, dst, #16 > + ldp1 D_l, D_h, src, #16 > + stp1 D_l, D_h, dst, #16 > + > + tst count, #0x3f > + b.ne .Ltail63_gr > + b .Lexitfunc_gr > + > + /* > + * Critical loop. Start at a new cache line boundary. Assuming > + * 64 bytes per line this ensures the entire loop is in one line. > + */ > + .p2align L1_CACHE_SHIFT > +.Lcpy_body_large_gr: > + /* pre-get 64 bytes data. */ > + ldp1 A_l, A_h, src, #16 > + ldp1 B_l, B_h, src, #16 > + ldp1 C_l, C_h, src, #16 > + ldp1 D_l, D_h, src, #16 > +1: > + /* > + * interlace the load of next 64 bytes data block with store of the last > + * loaded 64 bytes data. > + */ > + stp1 A_l, A_h, dst, #16 > + ldp1 A_l, A_h, src, #16 > + stp1 B_l, B_h, dst, #16 > + ldp1 B_l, B_h, src, #16 > + stp1 C_l, C_h, dst, #16 > + ldp1 C_l, C_h, src, #16 > + stp1 D_l, D_h, dst, #16 > + ldp1 D_l, D_h, src, #16 > + subs count, count, #64 > + b.ge 1b > + stp1 A_l, A_h, dst, #16 > + stp1 B_l, B_h, dst, #16 > + stp1 C_l, C_h, dst, #16 > + stp1 D_l, D_h, dst, #16 > + > + tst count, #0x3f > + b.ne .Ltail63_gr > +.Lexitfunc_gr: > diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S > index 6b99b939c50f..769133236f4a 100644 > --- a/arch/arm64/lib/copy_to_user.S > +++ b/arch/arm64/lib/copy_to_user.S > @@ -71,6 +71,25 @@ ENTRY(__arch_copy_to_user) > ret > ENDPROC(__arch_copy_to_user) > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +ENTRY(__arch_copy_to_user_generic_read) > + uaccess_enable_not_uao x3, x4, x5 > + add end, x0, x2 > +#include "copy_template_generic_read.S" > + uaccess_disable_not_uao x3, x4 > + > + mov x0, #0 > + ret > + > + .global copy_generic_read_sea_fallback > +copy_generic_read_sea_fallback: > + uaccess_disable_not_uao x3, x4 > + > + mov x0, #-1 > + ret > +ENDPROC(__arch_copy_to_user_generic_read) > +#endif > + > .section .fixup,"ax" > .align 2 > 9998: sub x0, end, dst // bytes not copied > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > index 039802b047af..08040fe73199 100644 > --- a/arch/arm64/mm/fault.c > +++ b/arch/arm64/mm/fault.c > @@ -662,6 +662,7 @@ int kernel_access_sea_recovery; > #define UCE_KER_REC_NUM ARRAY_SIZE(reco_info) > static struct uce_kernel_recovery_info reco_info[] = { > {copy_page_cow_sea_fallback, "copy_page_cow", (unsigned long)copy_page_cow, 0}, > + {copy_generic_read_sea_fallback, "__arch_copy_to_user_generic_read", (unsigned long)__arch_copy_to_user_generic_read, 0}, > }; > > static int __init kernel_access_sea_recovery_init(void) > @@ -708,6 +709,11 @@ int is_cow_kernel_recovery_enable(void) > return kernel_access_sea_recovery & 0x1; > } > > +int is_pagecache_reading_kernel_recovery_enable(void) > +{ > + return kernel_access_sea_recovery & 0x2; > +} > + > /* > * what is kernel recovery? > * If the process's private data is accessed in the kernel mode to trigger > @@ -827,6 +833,7 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) > > idx = is_in_kernel_recovery(esr, regs); > if (idx >= 0 && idx < UCE_KER_REC_NUM) { > + set_thread_flag(TIF_UCE_KERNEL_RECOVERY); > clear_siginfo(&info); > info.si_signo = inf->sig; > info.si_errno = 0; > diff --git a/include/linux/mm.h b/include/linux/mm.h > index 8b5f9b8fb1a3..5bd84fa48a44 100644 > --- a/include/linux/mm.h > +++ b/include/linux/mm.h > @@ -2837,6 +2837,9 @@ enum mf_flags { > MF_ACTION_REQUIRED = 1 << 1, > MF_MUST_KILL = 1 << 2, > MF_SOFT_OFFLINE = 1 << 3, > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > + MF_UCE_KERNEL_RECOVERY = 1 << 4 > +#endif > }; > extern int memory_failure(unsigned long pfn, int flags); > extern void memory_failure_queue(unsigned long pfn, int flags); > diff --git a/include/linux/uio.h b/include/linux/uio.h > index 422b1c01ee0d..13c48b13f21e 100644 > --- a/include/linux/uio.h > +++ b/include/linux/uio.h > @@ -97,6 +97,11 @@ bool _copy_from_iter_full(void *addr, size_t bytes, struct iov_iter *i); > size_t _copy_from_iter_nocache(void *addr, size_t bytes, struct iov_iter *i); > bool _copy_from_iter_full_nocache(void *addr, size_t bytes, struct iov_iter *i); > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +size_t copy_page_to_iter_generic_read(struct page *page, size_t offset, > + size_t bytes, struct iov_iter *i); > +#endif > + > static __always_inline __must_check > size_t copy_to_iter(const void *addr, size_t bytes, struct iov_iter *i) > { > diff --git a/lib/iov_iter.c b/lib/iov_iter.c > index dd8385a20325..66c0a4afbc74 100644 > --- a/lib/iov_iter.c > +++ b/lib/iov_iter.c > @@ -130,6 +130,17 @@ > } \ > } > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +static int copyout_generic_read(void __user *to, const void *from, size_t n) > +{ > + if (access_ok(to, n)) { > + kasan_check_read(from, n); > + n = raw_copy_to_user_generic_read(to, from, n); > + } > + return n; > +} > +#endif > + > static int copyout(void __user *to, const void *from, size_t n) > { > if (access_ok(to, n)) { > @@ -148,6 +159,108 @@ static int copyin(void *to, const void __user *from, size_t n) > return n; > } > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +static size_t copy_page_to_iter_iovec_generic_read(struct page *page, size_t offset, size_t bytes, > + struct iov_iter *i) > +{ > + size_t skip, copy, left, wanted; > + const struct iovec *iov; > + char __user *buf; > + void *kaddr, *from; > + > + if (unlikely(bytes > i->count)) > + bytes = i->count; > + > + if (unlikely(!bytes)) > + return 0; > + > + might_fault(); > + wanted = bytes; > + iov = i->iov; > + skip = i->iov_offset; > + buf = iov->iov_base + skip; > + copy = min(bytes, iov->iov_len - skip); > + > + if (IS_ENABLED(CONFIG_HIGHMEM) && !fault_in_pages_writeable(buf, copy)) { > + kaddr = kmap_atomic(page); > + from = kaddr + offset; > + > + /* first chunk, usually the only one */ > + left = copyout_generic_read(buf, from, copy); > + if (left == -1) { > + kunmap_atomic(kaddr); > + goto done; > + } > + copy -= left; > + skip += copy; > + from += copy; > + bytes -= copy; > + > + while (unlikely(!left && bytes)) { > + iov++; > + buf = iov->iov_base; > + copy = min(bytes, iov->iov_len); > + left = copyout_generic_read(buf, from, copy); > + if (left == -1) { > + kunmap_atomic(kaddr); > + goto done; > + } > + copy -= left; > + skip = copy; > + from += copy; > + bytes -= copy; > + } > + if (likely(!bytes)) { > + kunmap_atomic(kaddr); > + goto done; > + } > + offset = from - kaddr; > + buf += copy; > + kunmap_atomic(kaddr); > + copy = min(bytes, iov->iov_len - skip); > + } > + /* Too bad - revert to non-atomic kmap */ > + > + kaddr = kmap(page); > + from = kaddr + offset; > + left = copyout_generic_read(buf, from, copy); > + if (left == -1) { > + kunmap(page); > + goto done; > + } > + copy -= left; > + skip += copy; > + from += copy; > + bytes -= copy; > + while (unlikely(!left && bytes)) { > + iov++; > + buf = iov->iov_base; > + copy = min(bytes, iov->iov_len); > + left = copyout_generic_read(buf, from, copy); > + if (left == -1) { > + kunmap(page); > + goto done; > + } > + copy -= left; > + skip = copy; > + from += copy; > + bytes -= copy; > + } > + kunmap(page); > + > +done: > + if (skip == iov->iov_len) { > + iov++; > + skip = 0; > + } > + i->count -= wanted - bytes; > + i->nr_segs -= iov - i->iov; > + i->iov = iov; > + i->iov_offset = skip; > + return wanted - bytes; > +} > +#endif > + > static size_t copy_page_to_iter_iovec(struct page *page, size_t offset, size_t bytes, > struct iov_iter *i) > { > @@ -839,6 +952,25 @@ static inline bool page_copy_sane(struct page *page, size_t offset, size_t n) > return false; > } > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +size_t copy_page_to_iter_generic_read(struct page *page, size_t offset, size_t bytes, > + struct iov_iter *i) > +{ > + if (unlikely(!page_copy_sane(page, offset, bytes))) > + return 0; > + if (i->type & (ITER_BVEC|ITER_KVEC)) { > + void *kaddr = kmap_atomic(page); > + size_t wanted = copy_to_iter(kaddr + offset, bytes, i); > + kunmap_atomic(kaddr); > + return wanted; > + } else if (likely(!(i->type & ITER_PIPE))) > + return copy_page_to_iter_iovec_generic_read(page, offset, bytes, i); > + else > + return copy_page_to_iter_pipe(page, offset, bytes, i); > +} > +EXPORT_SYMBOL(copy_page_to_iter_generic_read); > +#endif > + > size_t copy_page_to_iter(struct page *page, size_t offset, size_t bytes, > struct iov_iter *i) > { > diff --git a/mm/filemap.c b/mm/filemap.c > index 6a212192e1b7..5c33c40e8019 100644 > --- a/mm/filemap.c > +++ b/mm/filemap.c > @@ -2290,8 +2290,14 @@ static ssize_t generic_file_buffered_read(struct kiocb *iocb, > * Ok, we have the page, and it's up-to-date, so > * now we can copy it to user space... > */ > - > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > + if (is_pagecache_reading_kernel_recovery_enable()) > + ret = copy_page_to_iter_generic_read(page, offset, nr, iter); > + else > + ret = copy_page_to_iter(page, offset, nr, iter); > +#else > ret = copy_page_to_iter(page, offset, nr, iter); > +#endif > offset += ret; > index += offset >> PAGE_SHIFT; > offset &= ~PAGE_MASK; > diff --git a/mm/internal.h b/mm/internal.h > index b6d3b3660782..3bb7ca86e84e 100644 > --- a/mm/internal.h > +++ b/mm/internal.h > @@ -591,6 +591,7 @@ extern struct page *alloc_new_node_page(struct page *page, unsigned long node); > > #ifdef CONFIG_UCE_KERNEL_RECOVERY > extern int is_cow_kernel_recovery_enable(void); > +extern int is_pagecache_reading_kernel_recovery_enable(void); > #endif > > #endif /* __MM_INTERNAL_H */ > diff --git a/mm/memory-failure.c b/mm/memory-failure.c > index 145262227bb0..1316e86e0a16 100644 > --- a/mm/memory-failure.c > +++ b/mm/memory-failure.c > @@ -1395,6 +1395,13 @@ int memory_failure(unsigned long pfn, int flags) > if (!PageTransTail(p) && !PageLRU(p) && !PageWriteback(p)) > goto identify_page_state; > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > + if ((flags & MF_UCE_KERNEL_RECOVERY) && PageWriteback(p)) { > + panic("UCE in memory failure while Page writeback, panic on page %lx, flags %x", > + pfn, flags); > + } > +#endif > + > /* > * It's very difficult to mess with pages currently under IO > * and in many cases impossible, so we just avoid it here. >

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Re: [kernel-4.19 1/2] uce: cow scenario support kernel recovery
by Xie XiuQi 11 Aug '21

11 Aug '21

Hi, Thanks for your patches. There are trinval typo, otherwice, looks good to me. Reviewed-by: Xie XiuQi <xiexiuqi(a)huawei.com> On 2021/8/11 11:37, Tong Tiangen wrote: > hulk inclusion > category: feature > bugzilla: https://gitee.com/openeuler/kernel/issues/I44R9D > CVE: NA > > --------------------------- > > During kernel COW processing, the kernel triggers a RAS exception when reading > pages. In this solution, we identify this scenario in the kernel do_sea processing > process, send SIGBUS signals to the process that triggers COW and isolate memory > pages, preventing kernel panic. > > At the same time, we use both cmdline(uce_kernel_recovery) and proc(/proc/sys/ > kernel/uce_kernel_recovery) to control this feature on/off. > > We use customized functions to distinguish scenarios that need kernel recovery, > specifically copy_page_cow(). When hardware error occurs in this function, we > killing the process that triggers the hardware error to replace the kernel die. > > Signed-off-by: Tong Tiangen <tongtiangen(a)huawei.com> > Signed-off-by: Chen Huang <chenhuang5(a)huawei.com> > --- > arch/arm64/Kconfig | 10 ++ > arch/arm64/include/asm/exception.h | 11 +++ > arch/arm64/include/asm/page.h | 8 ++ > arch/arm64/lib/copy_page.S | 78 +++++++++++++++ > arch/arm64/mm/copypage.c | 14 +++ > arch/arm64/mm/fault.c | 153 +++++++++++++++++++++++++++++ > include/linux/highmem.h | 17 ++++ > include/linux/kernel.h | 4 + > kernel/sysctl.c | 13 +++ > mm/internal.h | 5 + > mm/memory.c | 8 ++ > 11 files changed, 321 insertions(+) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 99905ee64625..e968df599e31 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1755,6 +1755,16 @@ config ARCH_HIBERNATION_HEADER > config ARCH_SUSPEND_POSSIBLE > def_bool y > > +config UCE_KERNEL_RECOVERY > + bool "uce kernel recovery from special scenario" > + def_bool y > + depends on ARM64_ERR_RECOV > + help > + With ARM v8.2 RAS Extension, SEA are usually triggered when memory errors > + are consumed. In some cases, if the error address is in a user page there > + is a chance to recover. Such as error occurs in COW and pagecache reading > + cenario, we can isolate this page and killing process instead of die. s/cenario/scenario/ > + > endmenu > > menu "CPU Power Management" > diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h > index bc30429d8e91..f938690c5ad6 100644 > --- a/arch/arm64/include/asm/exception.h > +++ b/arch/arm64/include/asm/exception.h > @@ -41,4 +41,15 @@ static inline u32 disr_to_esr(u64 disr) > return esr; > } > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +struct uce_kernel_recovery_info { > + int (*fn)(void); > + const char *name; > + unsigned long addr; > + unsigned long size; > +}; > + > +extern int copy_page_cow_sea_fallback(void); > +#endif > + > #endif /* __ASM_EXCEPTION_H */ > diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h > index 60d02c81a3a2..725bff5bc0ad 100644 > --- a/arch/arm64/include/asm/page.h > +++ b/arch/arm64/include/asm/page.h > @@ -35,6 +35,14 @@ extern void clear_page(void *to); > #define clear_user_page(addr,vaddr,pg) __cpu_clear_user_page(addr, vaddr) > #define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr) > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +extern int copy_page_cow(void *to, const void *from); > +extern int __cpu_copy_user_page_cow(void *to, const void *from, > + unsigned long user); > +#define copy_user_page_cow(to, from, vaddr, pg) \ > + __cpu_copy_user_page_cow(to, from, vaddr) > +#endif > + > typedef struct page *pgtable_t; > > #ifdef CONFIG_HAVE_ARCH_PFN_VALID > diff --git a/arch/arm64/lib/copy_page.S b/arch/arm64/lib/copy_page.S > index 076c43715e64..649cf4eb96bf 100644 > --- a/arch/arm64/lib/copy_page.S > +++ b/arch/arm64/lib/copy_page.S > @@ -87,3 +87,81 @@ alternative_else_nop_endif > > ret > ENDPROC(copy_page) > + > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +#The difference between copy_page_cow and copy_page: > +# 1) copy_page_cow adds the recovery path of sea fault(copy_page_cow_sea_fallback). > +# 2) copy_page_cow with return value: 0 - copy success 1 - copy fail. > +/* > + * COW copy a page from src to dest (both are page aligned) > + * > + * Parameters: > + * x0 - dest > + * x1 - src > + */ > +ENTRY(copy_page_cow) > +alternative_if ARM64_HAS_NO_HW_PREFETCH > + // Prefetch three cache lines ahead. > + prfm pldl1strm, [x1, #128] > + prfm pldl1strm, [x1, #256] > + prfm pldl1strm, [x1, #384] > +alternative_else_nop_endif > + > + ldp x2, x3, [x1] > + ldp x4, x5, [x1, #16] > + ldp x6, x7, [x1, #32] > + ldp x8, x9, [x1, #48] > + ldp x10, x11, [x1, #64] > + ldp x12, x13, [x1, #80] > + ldp x14, x15, [x1, #96] > + ldp x16, x17, [x1, #112] > + > + mov x18, #(PAGE_SIZE - 128) > + add x1, x1, #128 > +1: > + subs x18, x18, #128 > + > +alternative_if ARM64_HAS_NO_HW_PREFETCH > + prfm pldl1strm, [x1, #384] > +alternative_else_nop_endif > + > + stnp x2, x3, [x0] > + ldp x2, x3, [x1] > + stnp x4, x5, [x0, #16] > + ldp x4, x5, [x1, #16] > + stnp x6, x7, [x0, #32] > + ldp x6, x7, [x1, #32] > + stnp x8, x9, [x0, #48] > + ldp x8, x9, [x1, #48] > + stnp x10, x11, [x0, #64] > + ldp x10, x11, [x1, #64] > + stnp x12, x13, [x0, #80] > + ldp x12, x13, [x1, #80] > + stnp x14, x15, [x0, #96] > + ldp x14, x15, [x1, #96] > + stnp x16, x17, [x0, #112] > + ldp x16, x17, [x1, #112] > + > + add x0, x0, #128 > + add x1, x1, #128 > + > + b.gt 1b > + > + stnp x2, x3, [x0] > + stnp x4, x5, [x0, #16] > + stnp x6, x7, [x0, #32] > + stnp x8, x9, [x0, #48] > + stnp x10, x11, [x0, #64] > + stnp x12, x13, [x0, #80] > + stnp x14, x15, [x0, #96] > + stnp x16, x17, [x0, #112] > + > + mov x0, #0 > + ret > + > + .global copy_page_cow_sea_fallback > +copy_page_cow_sea_fallback: > + mov x0, #1 > + ret > +ENDPROC(copy_page_cow) > +#endif > diff --git a/arch/arm64/mm/copypage.c b/arch/arm64/mm/copypage.c > index 22e4cb4d6f53..506d166d1dec 100644 > --- a/arch/arm64/mm/copypage.c > +++ b/arch/arm64/mm/copypage.c > @@ -30,6 +30,20 @@ void __cpu_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) > } > EXPORT_SYMBOL_GPL(__cpu_copy_user_page); > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +int __cpu_copy_user_page_cow(void *kto, const void *kfrom, unsigned long vaddr) > +{ > + int ret; > + > + struct page *page = virt_to_page(kto); > + ret = copy_page_cow(kto, kfrom); > + flush_dcache_page(page); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(__cpu_copy_user_page_cow); > +#endif > + > void __cpu_clear_user_page(void *kaddr, unsigned long vaddr) > { > clear_page(kaddr); > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > index 6cd448d9835c..039802b047af 100644 > --- a/arch/arm64/mm/fault.c > +++ b/arch/arm64/mm/fault.c > @@ -656,6 +656,126 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) > return 1; /* "fault" */ > } > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +int kernel_access_sea_recovery; > + > +#define UCE_KER_REC_NUM ARRAY_SIZE(reco_info) > +static struct uce_kernel_recovery_info reco_info[] = { > + {copy_page_cow_sea_fallback, "copy_page_cow", (unsigned long)copy_page_cow, 0}, > +}; > + > +static int __init kernel_access_sea_recovery_init(void) > +{ > + unsigned long addr, size, offset; > + unsigned int i; > + > + for (i = 0; i < UCE_KER_REC_NUM; i++) { > + addr = reco_info[i].addr; > + if (!kallsyms_lookup_size_offset(addr, &size, &offset)) { > + pr_info("UCE: symbol %s lookup addr fail.\n", > + reco_info[i].name); > + size = 0; > + } > + > + reco_info[i].size = size; > + } > + > + return 1; > +} > +fs_initcall(kernel_access_sea_recovery_init); > + > +static int __init enable_kernel_access_sea_recovery(char *str) > +{ > + int max = (1 << UCE_KER_REC_NUM) - 1; > + int val; > + > + if (kstrtoint(str, 0, &val)) > + return -EINVAL; > + > + if (val < 0 || val > max) { > + pr_info("UCE: invalid uce_kernel_recovery value %d", val); > + return -EINVAL; > + } > + > + kernel_access_sea_recovery = val; > + > + return 1; > +} > +__setup("uce_kernel_recovery=", enable_kernel_access_sea_recovery); > + > +int is_cow_kernel_recovery_enable(void) > +{ > + return kernel_access_sea_recovery & 0x1; > +} > + > +/* > + * what is kernel recovery? > + * If the process's private data is accessed in the kernel mode to trigger > + * special sea fault, it can controlled by killing the process and isolating > + * the failure pages instead of die. > + */ > +static int is_in_kernel_recovery(unsigned int esr, struct pt_regs *regs) > +{ > + /* > + * target insn: ldp-pre, ldp-post, ldp-offset, > + * ldr-64bit-pre/pose, ldr-32bit-pre/post, ldrb-pre/post, ldrh-pre/post > + */ > + u32 target_insn[] = {0xa8c, 0xa9c, 0xa94, 0xf84, 0x784, 0x384, 0xb84}; > + void *pc = (void *)instruction_pointer(regs); > + struct uce_kernel_recovery_info *info; > + bool insn_match = false; > + u32 insn; > + int i; > + > + pr_emerg("UCE: %s-%d, kernel recovery: 0x%x, esr: 0x%08x -- %s, %pS\n", > + current->comm, current->pid, kernel_access_sea_recovery, esr, > + esr_get_class_string(esr), pc); > + > + if (aarch64_insn_read((void *)pc, &insn)) { > + pr_emerg("UCE: insn read fail.\n"); > + return -EFAULT; > + } > + > + /* > + * We process special ESR: > + * EC : 0b100101 Data Abort taken without a change in Exception level. > + * DFSC : 0b010000 Synchronous External abort, not on translation table > + * walk or hardware update of translation table. > + * eg: 0x96000610 > + */ > + if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR || > + (esr & ESR_ELx_FSC) != ESR_ELx_FSC_EXTABT) { > + pr_emerg("UCE: esr not match.\n"); > + return -EINVAL; > + } > + > + insn = (insn >> 20) & 0xffc; > + for (i = 0; i < ARRAY_SIZE(target_insn); i++) { > + if (insn == target_insn[i]) { > + insn_match = true; > + break; > + } > + } > + > + if (!insn_match) { > + pr_emerg("UCE: insn 0x%x is not match.\n", insn); > + return -EINVAL; > + } > + > + for (i = 0; i < UCE_KER_REC_NUM; i++) { > + info = &reco_info[i]; > + if (info->fn && regs->pc >= info->addr && > + regs->pc < (info->addr + info->size)) { > + pr_emerg("UCE: total match %s success.\n", info->name); > + return i; > + } > + } > + > + pr_emerg("UCE: symbol is not match.\n"); > + return -EINVAL; > +} > +#endif > + > static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) > { > struct siginfo info; > @@ -693,8 +813,41 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) > > arm64_notify_die(inf->name, regs, &info, esr); > } else { > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > + int idx; > + > + if (!current->mm || !kernel_access_sea_recovery) { > + pr_emerg("UCE: kernel recovery %d, %s-%d is %s-thread.\n", > + kernel_access_sea_recovery, > + current->comm, current->pid, > + (current->mm) ? "user" : "kernel"); > + die("Uncorrected hardware memory error in kernel-access\n", > + regs, esr); > + } > + > + idx = is_in_kernel_recovery(esr, regs); > + if (idx >= 0 && idx < UCE_KER_REC_NUM) { > + clear_siginfo(&info); > + info.si_signo = inf->sig; > + info.si_errno = 0; > + info.si_code = inf->code; > + info.si_addr = NULL; > + > + current->thread.fault_address = regs->pc; > + current->thread.fault_code = esr; > + regs->pc = (unsigned long)reco_info[idx].fn; > + arm64_force_sig_info(&info, > + "Uncorrected hardware memory use with kernel recovery in kernel-access\n", > + current); > + } else { > + die("Uncorrected hardware memory error (kernel recovery on but not match idx) in kernel-access\n", > + regs, esr); Do you mean "kernel recovery is enabled, but not match the idx" ? This path is the common case if in-kernel access uce. So we could just use the default message, or "Uncorrected hardware memory error without kernel recovery in kernel-access" ? > + } > + > +#else > die("Uncorrected hardware memory error in kernel-access\n", > regs, esr); > +#endif > } > > return 0; > diff --git a/include/linux/highmem.h b/include/linux/highmem.h > index 0690679832d4..1fed918bb1e5 100644 > --- a/include/linux/highmem.h > +++ b/include/linux/highmem.h > @@ -235,6 +235,23 @@ static inline void copy_user_highpage(struct page *to, struct page *from, > kunmap_atomic(vfrom); > } > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +static inline int copy_user_highpage_cow(struct page *to, struct page *from, > + unsigned long vaddr, struct vm_area_struct *vma) > +{ > + char *vfrom, *vto; > + int ret; > + > + vfrom = kmap_atomic(from); > + vto = kmap_atomic(to); > + ret = copy_user_page_cow(vto, vfrom, vaddr, to); > + kunmap_atomic(vto); > + kunmap_atomic(vfrom); > + > + return ret; > +} > +#endif > + > #endif > > #ifndef __HAVE_ARCH_COPY_HIGHPAGE > diff --git a/include/linux/kernel.h b/include/linux/kernel.h > index f24fd248b3ac..122f77b8b0ea 100644 > --- a/include/linux/kernel.h > +++ b/include/linux/kernel.h > @@ -531,6 +531,10 @@ extern int sysctl_panic_on_stackoverflow; > > extern bool crash_kexec_post_notifiers; > > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +extern int kernel_access_sea_recovery; > +#endif > + > /* > * panic_cpu is used for synchronizing panic() and crash_kexec() execution. It > * holds a CPU number which is executing panic() currently. A value of > diff --git a/kernel/sysctl.c b/kernel/sysctl.c > index 116fe8a13236..53ddcd74b5c3 100644 > --- a/kernel/sysctl.c > +++ b/kernel/sysctl.c > @@ -127,6 +127,7 @@ static int __maybe_unused neg_one = -1; > static int zero; > static int __maybe_unused one = 1; > static int __maybe_unused two = 2; > +static int __maybe_unused three = 3; > static int __maybe_unused four = 4; > static unsigned long zero_ul; > static unsigned long one_ul = 1; > @@ -1254,6 +1255,18 @@ static struct ctl_table kern_table[] = { > .extra1 = &zero, > .extra2 = &one, > }, > +#if defined(CONFIG_UCE_KERNEL_RECOVERY) > + { > + .procname = "uce_kernel_recovery", > + .data = &kernel_access_sea_recovery, > + .maxlen = sizeof(kernel_access_sea_recovery), > + .mode = 0644, > + .proc_handler = proc_dointvec_minmax, > + .extra1 = &zero, > + .extra2 = &three, > + }, > + > +#endif > { } > }; > > diff --git a/mm/internal.h b/mm/internal.h > index bfa97c43a3fc..b6d3b3660782 100644 > --- a/mm/internal.h > +++ b/mm/internal.h > @@ -588,4 +588,9 @@ static inline bool is_migrate_highatomic_page(struct page *page) > > void setup_zone_pageset(struct zone *zone); > extern struct page *alloc_new_node_page(struct page *page, unsigned long node); > + > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > +extern int is_cow_kernel_recovery_enable(void); > +#endif > + > #endif /* __MM_INTERNAL_H */ > diff --git a/mm/memory.c b/mm/memory.c > index d9f4e7dd17a6..174b0baf197e 100644 > --- a/mm/memory.c > +++ b/mm/memory.c > @@ -2212,7 +2212,15 @@ static inline bool cow_user_page(struct page *dst, struct page *src, > debug_dma_assert_idle(src); > > if (likely(src)) { > +#ifdef CONFIG_UCE_KERNEL_RECOVERY > + if (is_cow_kernel_recovery_enable()) { > + if (copy_user_highpage_cow(dst, src, addr, vma)) > + return false; > + } else > + copy_user_highpage(dst, src, addr, vma); > +#else > copy_user_highpage(dst, src, addr, vma); > +#endif > return true; > } > >

1 0

[PATCH OLK-5.10] USB: fix some clerical mistakes
by LeoLiuoc 11 Aug '21

11 Aug '21

Fix some clerical mistakes in previous patch<71fb26516dc8bb3050fa96a4290db64fc9d6c54b>. Signed-off-by: LeoLiu-oc <LeoLiu-oc(a)zhaoxin.com> --- drivers/usb/core/hcd-pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c index 000ee7a6731f..bbf9bd2d4b08 100644 --- a/drivers/usb/core/hcd-pci.c +++ b/drivers/usb/core/hcd-pci.c @@ -67,8 +67,8 @@ static void for_each_companion(struct pci_dev *pdev, struct usb_hcd *hcd, continue; if (strncmp(drv->name, "uhci_hcd", sizeof("uhci_hcd") - 1) && - strncmp(drv->name, "ooci_hcd", sizeof("uhci_hcd") - 1) && - strncmp(drv->name, "ehci_hcd", sizeof("uhci_hcd") - 1)) + strncmp(drv->name, "ohci-pci", sizeof("ohci-pci") - 1) && + strncmp(drv->name, "ehci-pci", sizeof("ehci-pci") - 1)) continue; /* -- 2.20.1

2 1

[PATCH kernel-4.19] USB: fix some clerical mistakes
by LeoLiuoc 11 Aug '21

11 Aug '21

Fix some clerical mistakes in previous patch<4d6c910e0825f397ea3b7cdfd639bdc12d878d27> Signed-off-by: LeoLiu-oc <LeoLiu-oc(a)zhaoxin.com> --- drivers/usb/core/hcd-pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c index c3cddaab708d..d4234f81b791 100644 --- a/drivers/usb/core/hcd-pci.c +++ b/drivers/usb/core/hcd-pci.c @@ -67,8 +67,8 @@ static void for_each_companion(struct pci_dev *pdev, struct usb_hcd *hcd, continue; if (strncmp(drv->name, "uhci_hcd", sizeof("uhci_hcd") - 1) && - strncmp(drv->name, "ooci_hcd", sizeof("uhci_hcd") - 1) && - strncmp(drv->name, "ehci_hcd", sizeof("uhci_hcd") - 1)) + strncmp(drv->name, "ohci-pci", sizeof("ohci-pci") - 1) && + strncmp(drv->name, "ehci-pci", sizeof("ehci-pci") - 1)) continue; /* -- 2.20.1

2 1

[PATCH kernel-4.19] livepatch/x86: Ignore return code of save_stack_trace_tsk_reliable()
by Yang Yingliang 10 Aug '21

10 Aug '21

From: Wang ShaoBo <bobo.shaobowang(a)huawei.com> hulk inclusion category: bugfix bugzilla: 175666 CVE: NA --------------------------- Checking return code of save_stack_trace_tsk_reliable() can be relaxed for safety validation when appling livepatch, so we ignore it's return code in klp_check_stack(). Signed-off-by: Wang ShaoBo <bobo.shaobowang(a)huawei.com> Reviewed-by: Jian Cheng <cj.chengjian(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- arch/x86/kernel/livepatch.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/livepatch.c b/arch/x86/kernel/livepatch.c index e927624d5016f..4d5599e443884 100644 --- a/arch/x86/kernel/livepatch.c +++ b/arch/x86/kernel/livepatch.c @@ -210,9 +210,8 @@ static int klp_check_stack(struct task_struct *task, ret = save_stack_trace_tsk_reliable(task, &trace); WARN_ON_ONCE(ret == -ENOSYS); if (ret) { - pr_info("%s: %s:%d has an unreliable stack\n", + pr_debug("%s: %s:%d has an unreliable stack\n", __func__, task->comm, task->pid); - return ret; } klp_for_each_object(patch, obj) { -- 2.25.1

1 0

[PATCH openEuler-1.0-LTS 1/3] arm64: mm: account for hotplug memory when randomizing the linear region
by Yang Yingliang 10 Aug '21

10 Aug '21

From: Ard Biesheuvel <ardb(a)kernel.org> mainline inclusion from mainline-v5.11-rc1 commit 97d6786e0669daa5c2f2d07a057f574e849dfd3e category: bugfix bugzilla: 175103 CVE: NA ----------------------------------------------- As a hardening measure, we currently randomize the placement of physical memory inside the linear region when KASLR is in effect. Since the random offset at which to place the available physical memory inside the linear region is chosen early at boot, it is based on the memblock description of memory, which does not cover hotplug memory. The consequence of this is that the randomization offset may be chosen such that any hotplugged memory located above memblock_end_of_DRAM() that appears later is pushed off the end of the linear region, where it cannot be accessed. So let's limit this randomization of the linear region to ensure that this can no longer happen, by using the CPU's addressable PA range instead. As it is guaranteed that no hotpluggable memory will appear that falls outside of that range, we can safely put this PA range sized window anywhere in the linear region. Signed-off-by: Ard Biesheuvel <ardb(a)kernel.org> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Cc: Steven Price <steven.price(a)arm.com> Cc: Robin Murphy <robin.murphy(a)arm.com> Link: https://lore.kernel.org/r/20201014081857.3288-1-ardb@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas(a)arm.com> Signed-off-by: Peng Liu <liupeng256(a)huawei.com> Reviewed-by: wangkefeng 00584194 <wangkefeng.wang(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- arch/arm64/mm/init.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 554824ce0f286..5449ae2d26bee 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -683,15 +683,18 @@ void __init arm64_memblock_init(void) if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { extern u16 memstart_offset_seed; - u64 range = linear_region_size - - (memblock_end_of_DRAM() - memblock_start_of_DRAM()); + u64 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); + int parange = cpuid_feature_extract_unsigned_field( + mmfr0, ID_AA64MMFR0_PARANGE_SHIFT); + s64 range = linear_region_size - + BIT(id_aa64mmfr0_parange_to_phys_shift(parange)); /* * If the size of the linear region exceeds, by a sufficient - * margin, the size of the region that the available physical - * memory spans, randomize the linear region as well. + * margin, the size of the region that the physical memory can + * span, randomize the linear region as well. */ - if (memstart_offset_seed > 0 && range >= ARM64_MEMSTART_ALIGN) { + if (memstart_offset_seed > 0 && range >= (s64)ARM64_MEMSTART_ALIGN) { range /= ARM64_MEMSTART_ALIGN; memstart_addr -= ARM64_MEMSTART_ALIGN * ((range * memstart_offset_seed) >> 16); -- 2.25.1

1 2

[PATCH kernel-4.19 1/3] arm64: mm: account for hotplug memory when randomizing the linear region
by Yang Yingliang 10 Aug '21

10 Aug '21

From: Ard Biesheuvel <ardb(a)kernel.org> mainline inclusion from mainline-v5.11-rc1 commit 97d6786e0669daa5c2f2d07a057f574e849dfd3e category: bugfix bugzilla: 175103 CVE: NA ----------------------------------------------- As a hardening measure, we currently randomize the placement of physical memory inside the linear region when KASLR is in effect. Since the random offset at which to place the available physical memory inside the linear region is chosen early at boot, it is based on the memblock description of memory, which does not cover hotplug memory. The consequence of this is that the randomization offset may be chosen such that any hotplugged memory located above memblock_end_of_DRAM() that appears later is pushed off the end of the linear region, where it cannot be accessed. So let's limit this randomization of the linear region to ensure that this can no longer happen, by using the CPU's addressable PA range instead. As it is guaranteed that no hotpluggable memory will appear that falls outside of that range, we can safely put this PA range sized window anywhere in the linear region. Signed-off-by: Ard Biesheuvel <ardb(a)kernel.org> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Cc: Steven Price <steven.price(a)arm.com> Cc: Robin Murphy <robin.murphy(a)arm.com> Link: https://lore.kernel.org/r/20201014081857.3288-1-ardb@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas(a)arm.com> Signed-off-by: Peng Liu <liupeng256(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- arch/arm64/mm/init.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 957cc293226aa..2399a257eaf33 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -683,15 +683,18 @@ void __init arm64_memblock_init(void) if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { extern u16 memstart_offset_seed; - u64 range = linear_region_size - - (memblock_end_of_DRAM() - memblock_start_of_DRAM()); + u64 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); + int parange = cpuid_feature_extract_unsigned_field( + mmfr0, ID_AA64MMFR0_PARANGE_SHIFT); + s64 range = linear_region_size - + BIT(id_aa64mmfr0_parange_to_phys_shift(parange)); /* * If the size of the linear region exceeds, by a sufficient - * margin, the size of the region that the available physical - * memory spans, randomize the linear region as well. + * margin, the size of the region that the physical memory can + * span, randomize the linear region as well. */ - if (memstart_offset_seed > 0 && range >= ARM64_MEMSTART_ALIGN) { + if (memstart_offset_seed > 0 && range >= (s64)ARM64_MEMSTART_ALIGN) { range /= ARM64_MEMSTART_ALIGN; memstart_addr -= ARM64_MEMSTART_ALIGN * ((range * memstart_offset_seed) >> 16); -- 2.25.1

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[PATCH openEuler-21.09 1/4] spi: Add HiSilicon SPI Controller Driver for Kunpeng SoCs
by Zheng Zengkai 09 Aug '21

09 Aug '21

From: Jay Fang <f.fangjian(a)huawei.com> mainline inclusion from mainline-v5.13-rc1 commit c770d8631e1810d8f1ce21b18ad5dd67eeb39e5c category: feature bugzilla: 175249 CVE: NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… ---------------------------------------------------------------------- This driver supports SPI Controller for HiSilicon Kunpeng SoCs. This driver supports SPI operations using FIFO mode of transfer. DMA is not supported, and we just use IRQ mode for operation completion notification. Only ACPI firmware is supported. Signed-off-by: Jay Fang <f.fangjian(a)huawei.com> Link: https://lore.kernel.org/r/1616836200-45827-1-git-send-email-f.fangjian@huaw… Signed-off-by: Mark Brown <broonie(a)kernel.org> Reviewed-by: Chengwen Feng <fengchengwen(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- MAINTAINERS | 7 + drivers/spi/Kconfig | 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-hisi-kunpeng.c | 505 +++++++++++++++++++++++++++++++++ 4 files changed, 523 insertions(+) create mode 100644 drivers/spi/spi-hisi-kunpeng.c diff --git a/MAINTAINERS b/MAINTAINERS index a032b00f1380..a12ecc71e1e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8007,6 +8007,13 @@ F: drivers/crypto/hisilicon/sec2/sec_crypto.c F: drivers/crypto/hisilicon/sec2/sec_crypto.h F: drivers/crypto/hisilicon/sec2/sec_main.c +HISILICON SPI Controller DRIVER FOR KUNPENG SOCS +M: Jay Fang <f.fangjian(a)huawei.com> +L: linux-spi(a)vger.kernel.org +S: Maintained +W: http://www.hisilicon.com +F: drivers/spi/spi-hisi-kunpeng.c + HISILICON STAGING DRIVERS FOR HIKEY 960/970 M: Mauro Carvalho Chehab <mchehab+huawei(a)kernel.org> S: Maintained diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index aadaea052f51..2e284cae97e3 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -339,6 +339,16 @@ config SPI_FSL_QUADSPI This controller does not support generic SPI messages. It only supports the high-level SPI memory interface. +config SPI_HISI_KUNPENG + tristate "HiSilicon SPI Controller for Kunpeng SoCs" + depends on (ARM64 && ACPI) || COMPILE_TEST + help + This enables support for HiSilicon SPI controller found on + Kunpeng SoCs. + + This driver can also be built as a module. If so, the module + will be called hisi-kunpeng-spi. + config SPI_HISI_SFC_V3XX tristate "HiSilicon SPI NOR Flash Controller for Hi16XX chipsets" depends on (ARM64 && ACPI) || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 6fea5821662e..04291ff89e16 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o obj-$(CONFIG_SPI_FSL_QUADSPI) += spi-fsl-qspi.o obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o obj-$(CONFIG_SPI_GPIO) += spi-gpio.o +obj-$(CONFIG_SPI_HISI_KUNPENG) += spi-hisi-kunpeng.o obj-$(CONFIG_SPI_HISI_SFC_V3XX) += spi-hisi-sfc-v3xx.o obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o obj-$(CONFIG_SPI_IMX) += spi-imx.o diff --git a/drivers/spi/spi-hisi-kunpeng.c b/drivers/spi/spi-hisi-kunpeng.c new file mode 100644 index 000000000000..abc0cd54eee6 --- /dev/null +++ b/drivers/spi/spi-hisi-kunpeng.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// HiSilicon SPI Controller Driver for Kunpeng SoCs +// +// Copyright (c) 2021 HiSilicon Technologies Co., Ltd. +// Author: Jay Fang <f.fangjian(a)huawei.com> +// +// This code is based on spi-dw-core.c. + +#include <linux/acpi.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/property.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spi/spi.h> + +/* Register offsets */ +#define HISI_SPI_CSCR 0x00 /* cs control register */ +#define HISI_SPI_CR 0x04 /* spi common control register */ +#define HISI_SPI_ENR 0x08 /* spi enable register */ +#define HISI_SPI_FIFOC 0x0c /* fifo level control register */ +#define HISI_SPI_IMR 0x10 /* interrupt mask register */ +#define HISI_SPI_DIN 0x14 /* data in register */ +#define HISI_SPI_DOUT 0x18 /* data out register */ +#define HISI_SPI_SR 0x1c /* status register */ +#define HISI_SPI_RISR 0x20 /* raw interrupt status register */ +#define HISI_SPI_ISR 0x24 /* interrupt status register */ +#define HISI_SPI_ICR 0x28 /* interrupt clear register */ +#define HISI_SPI_VERSION 0xe0 /* version register */ + +/* Bit fields in HISI_SPI_CR */ +#define CR_LOOP_MASK GENMASK(1, 1) +#define CR_CPOL_MASK GENMASK(2, 2) +#define CR_CPHA_MASK GENMASK(3, 3) +#define CR_DIV_PRE_MASK GENMASK(11, 4) +#define CR_DIV_POST_MASK GENMASK(19, 12) +#define CR_BPW_MASK GENMASK(24, 20) +#define CR_SPD_MODE_MASK GENMASK(25, 25) + +/* Bit fields in HISI_SPI_FIFOC */ +#define FIFOC_TX_MASK GENMASK(5, 3) +#define FIFOC_RX_MASK GENMASK(11, 9) + +/* Bit fields in HISI_SPI_IMR, 4 bits */ +#define IMR_RXOF BIT(0) /* Receive Overflow */ +#define IMR_RXTO BIT(1) /* Receive Timeout */ +#define IMR_RX BIT(2) /* Receive */ +#define IMR_TX BIT(3) /* Transmit */ +#define IMR_MASK (IMR_RXOF | IMR_RXTO | IMR_RX | IMR_TX) + +/* Bit fields in HISI_SPI_SR, 5 bits */ +#define SR_TXE BIT(0) /* Transmit FIFO empty */ +#define SR_TXNF BIT(1) /* Transmit FIFO not full */ +#define SR_RXNE BIT(2) /* Receive FIFO not empty */ +#define SR_RXF BIT(3) /* Receive FIFO full */ +#define SR_BUSY BIT(4) /* Busy Flag */ + +/* Bit fields in HISI_SPI_ISR, 4 bits */ +#define ISR_RXOF BIT(0) /* Receive Overflow */ +#define ISR_RXTO BIT(1) /* Receive Timeout */ +#define ISR_RX BIT(2) /* Receive */ +#define ISR_TX BIT(3) /* Transmit */ +#define ISR_MASK (ISR_RXOF | ISR_RXTO | ISR_RX | ISR_TX) + +/* Bit fields in HISI_SPI_ICR, 2 bits */ +#define ICR_RXOF BIT(0) /* Receive Overflow */ +#define ICR_RXTO BIT(1) /* Receive Timeout */ +#define ICR_MASK (ICR_RXOF | ICR_RXTO) + +#define DIV_POST_MAX 0xFF +#define DIV_POST_MIN 0x00 +#define DIV_PRE_MAX 0xFE +#define DIV_PRE_MIN 0x02 +#define CLK_DIV_MAX ((1 + DIV_POST_MAX) * DIV_PRE_MAX) +#define CLK_DIV_MIN ((1 + DIV_POST_MIN) * DIV_PRE_MIN) + +#define DEFAULT_NUM_CS 1 + +#define HISI_SPI_WAIT_TIMEOUT_MS 10UL + +enum hisi_spi_rx_level_trig { + HISI_SPI_RX_1, + HISI_SPI_RX_4, + HISI_SPI_RX_8, + HISI_SPI_RX_16, + HISI_SPI_RX_32, + HISI_SPI_RX_64, + HISI_SPI_RX_128 +}; + +enum hisi_spi_tx_level_trig { + HISI_SPI_TX_1_OR_LESS, + HISI_SPI_TX_4_OR_LESS, + HISI_SPI_TX_8_OR_LESS, + HISI_SPI_TX_16_OR_LESS, + HISI_SPI_TX_32_OR_LESS, + HISI_SPI_TX_64_OR_LESS, + HISI_SPI_TX_128_OR_LESS +}; + +enum hisi_spi_frame_n_bytes { + HISI_SPI_N_BYTES_NULL, + HISI_SPI_N_BYTES_U8, + HISI_SPI_N_BYTES_U16, + HISI_SPI_N_BYTES_U32 = 4 +}; + +/* Slave spi_dev related */ +struct hisi_chip_data { + u32 cr; + u32 speed_hz; /* baud rate */ + u16 clk_div; /* baud rate divider */ + + /* clk_div = (1 + div_post) * div_pre */ + u8 div_post; /* value from 0 to 255 */ + u8 div_pre; /* value from 2 to 254 (even only!) */ +}; + +struct hisi_spi { + struct device *dev; + + void __iomem *regs; + int irq; + u32 fifo_len; /* depth of the FIFO buffer */ + + /* Current message transfer state info */ + const void *tx; + unsigned int tx_len; + void *rx; + unsigned int rx_len; + u8 n_bytes; /* current is a 1/2/4 bytes op */ +}; + +static u32 hisi_spi_busy(struct hisi_spi *hs) +{ + return readl(hs->regs + HISI_SPI_SR) & SR_BUSY; +} + +static u32 hisi_spi_rx_not_empty(struct hisi_spi *hs) +{ + return readl(hs->regs + HISI_SPI_SR) & SR_RXNE; +} + +static u32 hisi_spi_tx_not_full(struct hisi_spi *hs) +{ + return readl(hs->regs + HISI_SPI_SR) & SR_TXNF; +} + +static void hisi_spi_flush_fifo(struct hisi_spi *hs) +{ + unsigned long limit = loops_per_jiffy << 1; + + do { + while (hisi_spi_rx_not_empty(hs)) + readl(hs->regs + HISI_SPI_DOUT); + } while (hisi_spi_busy(hs) && limit--); +} + +/* Disable the controller and all interrupts */ +static void hisi_spi_disable(struct hisi_spi *hs) +{ + writel(0, hs->regs + HISI_SPI_ENR); + writel(IMR_MASK, hs->regs + HISI_SPI_IMR); + writel(ICR_MASK, hs->regs + HISI_SPI_ICR); +} + +static u8 hisi_spi_n_bytes(struct spi_transfer *transfer) +{ + if (transfer->bits_per_word <= 8) + return HISI_SPI_N_BYTES_U8; + else if (transfer->bits_per_word <= 16) + return HISI_SPI_N_BYTES_U16; + else + return HISI_SPI_N_BYTES_U32; +} + +static void hisi_spi_reader(struct hisi_spi *hs) +{ + u32 max = min_t(u32, hs->rx_len, hs->fifo_len); + u32 rxw; + + while (hisi_spi_rx_not_empty(hs) && max--) { + rxw = readl(hs->regs + HISI_SPI_DOUT); + /* Check the transfer's original "rx" is not null */ + if (hs->rx) { + switch (hs->n_bytes) { + case HISI_SPI_N_BYTES_U8: + *(u8 *)(hs->rx) = rxw; + break; + case HISI_SPI_N_BYTES_U16: + *(u16 *)(hs->rx) = rxw; + break; + case HISI_SPI_N_BYTES_U32: + *(u32 *)(hs->rx) = rxw; + break; + } + hs->rx += hs->n_bytes; + } + --hs->rx_len; + } +} + +static void hisi_spi_writer(struct hisi_spi *hs) +{ + u32 max = min_t(u32, hs->tx_len, hs->fifo_len); + u32 txw = 0; + + while (hisi_spi_tx_not_full(hs) && max--) { + /* Check the transfer's original "tx" is not null */ + if (hs->tx) { + switch (hs->n_bytes) { + case HISI_SPI_N_BYTES_U8: + txw = *(u8 *)(hs->tx); + break; + case HISI_SPI_N_BYTES_U16: + txw = *(u16 *)(hs->tx); + break; + case HISI_SPI_N_BYTES_U32: + txw = *(u32 *)(hs->tx); + break; + } + hs->tx += hs->n_bytes; + } + writel(txw, hs->regs + HISI_SPI_DIN); + --hs->tx_len; + } +} + +static void __hisi_calc_div_reg(struct hisi_chip_data *chip) +{ + chip->div_pre = DIV_PRE_MAX; + while (chip->div_pre >= DIV_PRE_MIN) { + if (chip->clk_div % chip->div_pre == 0) + break; + + chip->div_pre -= 2; + } + + if (chip->div_pre > chip->clk_div) + chip->div_pre = chip->clk_div; + + chip->div_post = (chip->clk_div / chip->div_pre) - 1; +} + +static u32 hisi_calc_effective_speed(struct spi_controller *master, + struct hisi_chip_data *chip, u32 speed_hz) +{ + u32 effective_speed; + + /* Note clock divider doesn't support odd numbers */ + chip->clk_div = DIV_ROUND_UP(master->max_speed_hz, speed_hz) + 1; + chip->clk_div &= 0xfffe; + if (chip->clk_div > CLK_DIV_MAX) + chip->clk_div = CLK_DIV_MAX; + + effective_speed = master->max_speed_hz / chip->clk_div; + if (chip->speed_hz != effective_speed) { + __hisi_calc_div_reg(chip); + chip->speed_hz = effective_speed; + } + + return effective_speed; +} + +static u32 hisi_spi_prepare_cr(struct spi_device *spi) +{ + u32 cr = FIELD_PREP(CR_SPD_MODE_MASK, 1); + + cr |= FIELD_PREP(CR_CPHA_MASK, (spi->mode & SPI_CPHA) ? 1 : 0); + cr |= FIELD_PREP(CR_CPOL_MASK, (spi->mode & SPI_CPOL) ? 1 : 0); + cr |= FIELD_PREP(CR_LOOP_MASK, (spi->mode & SPI_LOOP) ? 1 : 0); + + return cr; +} + +static void hisi_spi_hw_init(struct hisi_spi *hs) +{ + hisi_spi_disable(hs); + + /* FIFO default config */ + writel(FIELD_PREP(FIFOC_TX_MASK, HISI_SPI_TX_64_OR_LESS) | + FIELD_PREP(FIFOC_RX_MASK, HISI_SPI_RX_16), + hs->regs + HISI_SPI_FIFOC); + + hs->fifo_len = 256; +} + +static irqreturn_t hisi_spi_irq(int irq, void *dev_id) +{ + struct spi_controller *master = dev_id; + struct hisi_spi *hs = spi_controller_get_devdata(master); + u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK; + + if (!irq_status) + return IRQ_NONE; + + if (!master->cur_msg) + return IRQ_HANDLED; + + /* Error handling */ + if (irq_status & ISR_RXOF) { + dev_err(hs->dev, "interrupt_transfer: fifo overflow\n"); + master->cur_msg->status = -EIO; + goto finalize_transfer; + } + + /* + * Read data from the Rx FIFO every time. If there is + * nothing left to receive, finalize the transfer. + */ + hisi_spi_reader(hs); + if (!hs->rx_len) + goto finalize_transfer; + + /* Send data out when Tx FIFO IRQ triggered */ + if (irq_status & ISR_TX) + hisi_spi_writer(hs); + + return IRQ_HANDLED; + +finalize_transfer: + hisi_spi_disable(hs); + spi_finalize_current_transfer(master); + return IRQ_HANDLED; +} + +static int hisi_spi_transfer_one(struct spi_controller *master, + struct spi_device *spi, struct spi_transfer *transfer) +{ + struct hisi_spi *hs = spi_controller_get_devdata(master); + struct hisi_chip_data *chip = spi_get_ctldata(spi); + u32 cr = chip->cr; + + /* Update per transfer options for speed and bpw */ + transfer->effective_speed_hz = + hisi_calc_effective_speed(master, chip, transfer->speed_hz); + cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre); + cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post); + cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1); + writel(cr, hs->regs + HISI_SPI_CR); + + hisi_spi_flush_fifo(hs); + + hs->n_bytes = hisi_spi_n_bytes(transfer); + hs->tx = transfer->tx_buf; + hs->tx_len = transfer->len / hs->n_bytes; + hs->rx = transfer->rx_buf; + hs->rx_len = hs->tx_len; + + /* + * Ensure that the transfer data above has been updated + * before the interrupt to start. + */ + smp_mb(); + + /* Enable all interrupts and the controller */ + writel(~IMR_MASK, hs->regs + HISI_SPI_IMR); + writel(1, hs->regs + HISI_SPI_ENR); + + return 1; +} + +static void hisi_spi_handle_err(struct spi_controller *master, + struct spi_message *msg) +{ + struct hisi_spi *hs = spi_controller_get_devdata(master); + + hisi_spi_disable(hs); + + /* + * Wait for interrupt handler that is + * already in timeout to complete. + */ + msleep(HISI_SPI_WAIT_TIMEOUT_MS); +} + +static int hisi_spi_setup(struct spi_device *spi) +{ + struct hisi_chip_data *chip; + + /* Only alloc on first setup */ + chip = spi_get_ctldata(spi); + if (!chip) { + chip = kzalloc(sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + spi_set_ctldata(spi, chip); + } + + chip->cr = hisi_spi_prepare_cr(spi); + + return 0; +} + +static void hisi_spi_cleanup(struct spi_device *spi) +{ + struct hisi_chip_data *chip = spi_get_ctldata(spi); + + kfree(chip); + spi_set_ctldata(spi, NULL); +} + +static int hisi_spi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spi_controller *master; + struct hisi_spi *hs; + int ret, irq; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + master = devm_spi_alloc_master(dev, sizeof(*hs)); + if (!master) + return -ENOMEM; + + platform_set_drvdata(pdev, master); + + hs = spi_controller_get_devdata(master); + hs->dev = dev; + hs->irq = irq; + + hs->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hs->regs)) + return PTR_ERR(hs->regs); + + /* Specify maximum SPI clocking speed (master only) by firmware */ + ret = device_property_read_u32(dev, "spi-max-frequency", + &master->max_speed_hz); + if (ret) { + dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n", + ret); + return -EINVAL; + } + + ret = device_property_read_u16(dev, "num-cs", + &master->num_chipselect); + if (ret) + master->num_chipselect = DEFAULT_NUM_CS; + + master->use_gpio_descriptors = true; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); + master->bus_num = pdev->id; + master->setup = hisi_spi_setup; + master->cleanup = hisi_spi_cleanup; + master->transfer_one = hisi_spi_transfer_one; + master->handle_err = hisi_spi_handle_err; + master->dev.fwnode = dev->fwnode; + + hisi_spi_hw_init(hs); + + ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev), + master); + if (ret < 0) { + dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret); + return ret; + } + + ret = spi_register_controller(master); + if (ret) { + dev_err(dev, "failed to register spi master, ret=%d\n", ret); + return ret; + } + + dev_info(dev, "hw version:0x%x max-freq:%u kHz\n", + readl(hs->regs + HISI_SPI_VERSION), + master->max_speed_hz / 1000); + + return 0; +} + +static int hisi_spi_remove(struct platform_device *pdev) +{ + struct spi_controller *master = platform_get_drvdata(pdev); + + spi_unregister_controller(master); + + return 0; +} + +static const struct acpi_device_id hisi_spi_acpi_match[] = { + {"HISI03E1", 0}, + {} +}; +MODULE_DEVICE_TABLE(acpi, hisi_spi_acpi_match); + +static struct platform_driver hisi_spi_driver = { + .probe = hisi_spi_probe, + .remove = hisi_spi_remove, + .driver = { + .name = "hisi-kunpeng-spi", + .acpi_match_table = hisi_spi_acpi_match, + }, +}; +module_platform_driver(hisi_spi_driver); + +MODULE_AUTHOR("Jay Fang <f.fangjian(a)huawei.com>"); +MODULE_DESCRIPTION("HiSilicon SPI Controller Driver for Kunpeng SoCs"); +MODULE_LICENSE("GPL v2"); -- 2.20.1

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[PATCH openEuler-1.0-LTS] mm/vmscan: setup drop_caches_loop_limit in cmdline
by Yang Yingliang 06 Aug '21

06 Aug '21

From: Liu Shixin <liushixin2(a)huawei.com> hulk inclusion category: bugfix bugzilla: 175105 CVE: NA ------------------------------------------------- When !CONFIG_SYSCTL, drop_caches_loop_limit is invisible. Add cmdline "drop_caches_loop_limit=" to set it. This parameter can limit the number of loops per node. Fixes: 90394d30702e ("mm/vmscan: add drop_caches_loop_limit to break loop in drop_slab_node") Signed-off-by: Liu Shixin <liushixin2(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- fs/drop_caches.c | 1 - include/linux/mm.h | 2 +- kernel/sysctl.c | 2 +- mm/vmscan.c | 19 +++++++++++++------ 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/fs/drop_caches.c b/fs/drop_caches.c index 1f866b32cd150..dc1a1d5d825b4 100644 --- a/fs/drop_caches.c +++ b/fs/drop_caches.c @@ -13,7 +13,6 @@ /* A global variable is a bit ugly, but it keeps the code simple */ int sysctl_drop_caches; -unsigned int sysctl_drop_caches_loop_limit __read_mostly; static void drop_pagecache_sb(struct super_block *sb, void *unused) { diff --git a/include/linux/mm.h b/include/linux/mm.h index db53f49e13b91..d3d62cd3ee07c 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -2769,7 +2769,7 @@ extern bool process_shares_mm(struct task_struct *p, struct mm_struct *mm); #ifdef CONFIG_SYSCTL extern int sysctl_drop_caches; -extern unsigned int sysctl_drop_caches_loop_limit; +extern unsigned int drop_caches_loop_limit; int drop_caches_sysctl_handler(struct ctl_table *, int, void __user *, size_t *, loff_t *); #endif diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 1733b8c71b117..91d4fe5b2770f 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -1479,7 +1479,7 @@ static struct ctl_table vm_table[] = { }, { .procname = "drop_caches_loop_limit", - .data = &sysctl_drop_caches_loop_limit, + .data = &drop_caches_loop_limit, .maxlen = sizeof(unsigned int), .mode = 0644, .proc_handler = proc_douintvec, diff --git a/mm/vmscan.c b/mm/vmscan.c index 3d7716e2e2c66..b5f5a366d155f 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -723,12 +723,21 @@ static unsigned long shrink_slab(gfp_t gfp_mask, int nid, return freed; } +unsigned int drop_caches_loop_limit __read_mostly; +static int __init drop_caches_loop_limit_setup(char *s) +{ + int ret = kstrtouint(s, 10, &drop_caches_loop_limit); + + if (ret) + pr_info("Parse drop_caches_loop_limit failed: ret: %d\n", ret); + return 1; +} +__setup("drop_caches_loop_limit=", drop_caches_loop_limit_setup); + void drop_slab_node(int nid) { unsigned long freed; -#ifdef CONFIG_SYSCTL unsigned int counts = 0; -#endif do { struct mem_cgroup *memcg = NULL; @@ -742,17 +751,15 @@ void drop_slab_node(int nid) freed += shrink_slab(GFP_KERNEL, nid, memcg, 0); } while ((memcg = mem_cgroup_iter(NULL, memcg, NULL)) != NULL); -#ifdef CONFIG_SYSCTL - if (unlikely(sysctl_drop_caches_loop_limit)) { + if (unlikely(drop_caches_loop_limit)) { counts++; - if (counts >= sysctl_drop_caches_loop_limit) { + if (counts >= drop_caches_loop_limit) { pr_info("%s (%d): drop_caches early break: %u loops\n", current->comm, task_pid_nr(current), counts); return; } } -#endif } while (freed > 10); } -- 2.25.1

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Kernel August 2021