tree: https://gitee.com/openeuler/kernel.git OLK-6.6
head: 7c547c6bbe6b6a9cedf63d7cdadb2529404df633
commit: 6449ff7a5a2b148bc0a60efb3f0d723aaeceaae6 [1474/1474] ipmi: Errata workaround to prevent SMS message processing timeout
config: arm64-randconfig-003-20241117 (https://download.01.org/0day-ci/archive/20241118/202411180216.cVGR9zgK-lkp@…)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241118/202411180216.cVGR9zgK-lkp@…)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp(a)intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411180216.cVGR9zgK-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/char/ipmi/ipmi_bt_sm.c:194:11: error: call to undeclared function 'acpi_evaluate_integer'; ISO C99 and later do not support implicit function declarations [-Werror,-Wimplicit-function-declaration]
status = acpi_evaluate_integer(handle, "SATN", NULL, &tmp);
^
drivers/char/ipmi/ipmi_bt_sm.c:194:11: note: did you mean 'acpi_evaluate_object'?
include/acpi/acpixf.h:550:8: note: 'acpi_evaluate_object' declared here
acpi_evaluate_object(acpi_handle object,
^
include/acpi/platform/aclinux.h:93:21: note: expanded from macro 'ACPI_EXTERNAL_RETURN_STATUS'
static ACPI_INLINE prototype {return(AE_NOT_CONFIGURED);}
^
1 error generated.
vim +/acpi_evaluate_integer +194 drivers/char/ipmi/ipmi_bt_sm.c
177
178 #ifdef CONFIG_HISILICON_ERRATUM_162102203
179 /*
180 * To confirm whether the SMS_ATN flag needs to be stored and get
181 * quirk through the method reported by the BIOS. Because in special
182 * cases SMS_ATN flag bits may be lost before being processed.
183 */
184 static bool get_sms_atn_quirk(struct si_sm_io *io)
185 {
186 acpi_handle handle;
187 acpi_status status;
188 unsigned long long tmp;
189
190 handle = ACPI_HANDLE(io->dev);
191 if (!handle)
192 return false;
193
> 194 status = acpi_evaluate_integer(handle, "SATN", NULL, &tmp);
195 if (ACPI_FAILURE(status))
196 return false;
197 else if (tmp != 1)
198 return false;
199
200 return true;
201 }
202 #endif
203
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Wang,
FYI, the error/warning still remains.
tree: https://gitee.com/openeuler/kernel.git OLK-6.6
head: 7c547c6bbe6b6a9cedf63d7cdadb2529404df633
commit: 549b1f40b56511536196f7522ffa4d7b3da42337 [1474/1474] mm/sharepool: Implement mg_sp_make_share_u2k()
config: arm64-randconfig-003-20241117 (https://download.01.org/0day-ci/archive/20241117/202411172041.LAsMkbYc-lkp@…)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241117/202411172041.LAsMkbYc-lkp@…)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp(a)intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411172041.LAsMkbYc-lkp@intel.com/
All errors (new ones prefixed by >>):
>> mm/share_pool.c:1226:14: error: call to undeclared function 'huge_ptep_get'; ISO C99 and later do not support implicit function declarations [-Werror,-Wimplicit-function-declaration]
pte_t pte = huge_ptep_get(ptep);
^
mm/share_pool.c:1226:8: error: initializing 'pte_t' with an expression of incompatible type 'int'
pte_t pte = huge_ptep_get(ptep);
^ ~~~~~~~~~~~~~~~~~~~
2 errors generated.
vim +/huge_ptep_get +1226 mm/share_pool.c
1221
1222 static int sp_hugetlb_entry(pte_t *ptep, unsigned long hmask,
1223 unsigned long addr, unsigned long next,
1224 struct mm_walk *walk)
1225 {
> 1226 pte_t pte = huge_ptep_get(ptep);
1227 struct page *page = pte_page(pte);
1228 struct sp_walk_data *sp_walk_data;
1229
1230 if (unlikely(!pte_present(pte))) {
1231 pr_debug("the page of addr %lx unexpectedly not in RAM\n", (unsigned long)addr);
1232 return -EFAULT;
1233 }
1234
1235 sp_walk_data = walk->private;
1236 get_page(page);
1237 sp_walk_data->pages[sp_walk_data->page_count++] = page;
1238 return 0;
1239 }
1240
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
From: Jason Gunthorpe <jgg(a)nvidia.com>
mainline inclusion
from mainline-v6.9-rc1
commit 7da51af9125c624318c8099de13c5ddefd47e9e8
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IB4WDJ
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?…
--------------------------------
As the comment in arm_smmu_write_strtab_ent() explains, this routine has
been limited to only work correctly in certain scenarios that the caller
must ensure. Generally the caller must put the STE into ABORT or BYPASS
before attempting to program it to something else.
The iommu core APIs would ideally expect the driver to do a hitless change
of iommu_domain in a number of cases:
- RESV_DIRECT support wants IDENTITY -> DMA -> IDENTITY to be hitless
for the RESV ranges
- PASID upgrade has IDENTIY on the RID with no PASID then a PASID paging
domain installed. The RID should not be impacted
- PASID downgrade has IDENTIY on the RID and all PASID's removed.
The RID should not be impacted
- RID does PAGING -> BLOCKING with active PASID, PASID's should not be
impacted
- NESTING -> NESTING for carrying all the above hitless cases in a VM
into the hypervisor. To comprehensively emulate the HW in a VM we
should assume the VM OS is running logic like this and expecting
hitless updates to be relayed to real HW.
For CD updates arm_smmu_write_ctx_desc() has a similar comment explaining
how limited it is, and the driver does have a need for hitless CD updates:
- SMMUv3 BTM S1 ASID re-label
- SVA mm release should change the CD to answert not-present to all
requests without allowing logging (EPD0)
The next patches/series are going to start removing some of this logic
from the callers, and add more complex state combinations than currently.
At the end everything that can be hitless will be hitless, including all
of the above.
Introduce arm_smmu_write_ste() which will run through the multi-qword
programming sequence to avoid creating an incoherent 'torn' STE in the HW
caches. It automatically detects which of two algorithms to use:
1) The disruptive V=0 update described in the spec which disrupts the
entry and does three syncs to make the change:
- Write V=0 to QWORD 0
- Write the entire STE except QWORD 0
- Write QWORD 0
2) A hitless update algorithm that follows the same rational that the driver
already uses. It is safe to change IGNORED bits that HW doesn't use:
- Write the target value into all currently unused bits
- Write a single QWORD, this makes the new STE live atomically
- Ensure now unused bits are 0
The detection of which path to use and the implementation of the hitless
update rely on a "used bitmask" describing what bits the HW is actually
using based on the V/CFG/etc bits. This flows from the spec language,
typically indicated as IGNORED.
Knowing which bits the HW is using we can update the bits it does not use
and then compute how many QWORDS need to be changed. If only one qword
needs to be updated the hitless algorithm is possible.
Later patches will include CD updates in this mechanism so make the
implementation generic using a struct arm_smmu_entry_writer and struct
arm_smmu_entry_writer_ops to abstract the differences between STE and CD
to be plugged in.
At this point it generates the same sequence of updates as the current
code, except that zeroing the VMID on entry to BYPASS/ABORT will do an
extra sync (this seems to be an existing bug).
Going forward this will use a V=0 transition instead of cycling through
ABORT if a hitfull change is required. This seems more appropriate as ABORT
will fail DMAs without any logging, but dropping a DMA due to transient
V=0 is probably signaling a bug, so the C_BAD_STE is valuable.
Add STRTAB_STE_1_SHCFG_INCOMING to s2_cfg, this was editing the STE in
place and subtly inherited the value of data[1] from abort/bypass.
Signed-off-by: Michael Shavit <mshavit(a)google.com>
Signed-off-by: Jason Gunthorpe <jgg(a)nvidia.com>
Link: https://lore.kernel.org/r/1-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia…
Signed-off-by: Will Deacon <will(a)kernel.org>
Signed-off-by: Kunkun Jiang <jiangkunkun(a)huawei.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 275 +++++++++++++++-----
1 file changed, 211 insertions(+), 64 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 230368d05892..21cb2e47f96e 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -110,6 +110,9 @@ enum arm_smmu_msi_index {
ARM_SMMU_MAX_MSIS,
};
+static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu,
+ ioasid_t sid);
+
static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
[EVTQ_MSI_INDEX] = {
ARM_SMMU_EVTQ_IRQ_CFG0,
@@ -1190,6 +1193,199 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid)
arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
}
+/*
+ * Based on the value of ent report which bits of the STE the HW will access. It
+ * would be nice if this was complete according to the spec, but minimally it
+ * has to capture the bits this driver uses.
+ */
+static void arm_smmu_get_ste_used(const struct arm_smmu_ste *ent,
+ struct arm_smmu_ste *used_bits)
+{
+ unsigned int cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ent->data[0]));
+
+ used_bits->data[0] = cpu_to_le64(STRTAB_STE_0_V);
+ if (!(ent->data[0] & cpu_to_le64(STRTAB_STE_0_V)))
+ return;
+
+ used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_CFG);
+
+ /* S1 translates */
+ if (cfg & BIT(0)) {
+ used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_S1FMT |
+ STRTAB_STE_0_S1CTXPTR_MASK |
+ STRTAB_STE_0_S1CDMAX);
+ used_bits->data[1] |=
+ cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR |
+ STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH |
+ STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW |
+ STRTAB_STE_1_EATS);
+ used_bits->data[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID);
+ }
+
+ /* S2 translates */
+ if (cfg & BIT(1)) {
+ used_bits->data[1] |=
+ cpu_to_le64(STRTAB_STE_1_EATS | STRTAB_STE_1_SHCFG);
+ used_bits->data[2] |=
+ cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR |
+ STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI |
+ STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2R);
+ used_bits->data[3] |= cpu_to_le64(STRTAB_STE_3_S2TTB_MASK);
+ }
+
+ if (cfg == STRTAB_STE_0_CFG_BYPASS)
+ used_bits->data[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG);
+}
+
+/*
+ * Figure out if we can do a hitless update of entry to become target. Returns a
+ * bit mask where 1 indicates that qword needs to be set disruptively.
+ * unused_update is an intermediate value of entry that has unused bits set to
+ * their new values.
+ */
+static u8 arm_smmu_entry_qword_diff(const struct arm_smmu_ste *entry,
+ const struct arm_smmu_ste *target,
+ struct arm_smmu_ste *unused_update)
+{
+ struct arm_smmu_ste target_used = {};
+ struct arm_smmu_ste cur_used = {};
+ u8 used_qword_diff = 0;
+ unsigned int i;
+
+ arm_smmu_get_ste_used(entry, &cur_used);
+ arm_smmu_get_ste_used(target, &target_used);
+
+ for (i = 0; i != ARRAY_SIZE(target_used.data); i++) {
+ /*
+ * Check that masks are up to date, the make functions are not
+ * allowed to set a bit to 1 if the used function doesn't say it
+ * is used.
+ */
+ WARN_ON_ONCE(target->data[i] & ~target_used.data[i]);
+
+ /* Bits can change because they are not currently being used */
+ unused_update->data[i] = (entry->data[i] & cur_used.data[i]) |
+ (target->data[i] & ~cur_used.data[i]);
+ /*
+ * Each bit indicates that a used bit in a qword needs to be
+ * changed after unused_update is applied.
+ */
+ if ((unused_update->data[i] & target_used.data[i]) !=
+ target->data[i])
+ used_qword_diff |= 1 << i;
+ }
+ return used_qword_diff;
+}
+
+static bool entry_set(struct arm_smmu_device *smmu, ioasid_t sid,
+ struct arm_smmu_ste *entry,
+ const struct arm_smmu_ste *target, unsigned int start,
+ unsigned int len)
+{
+ bool changed = false;
+ unsigned int i;
+
+ for (i = start; len != 0; len--, i++) {
+ if (entry->data[i] != target->data[i]) {
+ WRITE_ONCE(entry->data[i], target->data[i]);
+ changed = true;
+ }
+ }
+
+ if (changed)
+ arm_smmu_sync_ste_for_sid(smmu, sid);
+ return changed;
+}
+
+/*
+ * Update the STE/CD to the target configuration. The transition from the
+ * current entry to the target entry takes place over multiple steps that
+ * attempts to make the transition hitless if possible. This function takes care
+ * not to create a situation where the HW can perceive a corrupted entry. HW is
+ * only required to have a 64 bit atomicity with stores from the CPU, while
+ * entries are many 64 bit values big.
+ *
+ * The difference between the current value and the target value is analyzed to
+ * determine which of three updates are required - disruptive, hitless or no
+ * change.
+ *
+ * In the most general disruptive case we can make any update in three steps:
+ * - Disrupting the entry (V=0)
+ * - Fill now unused qwords, execpt qword 0 which contains V
+ * - Make qword 0 have the final value and valid (V=1) with a single 64
+ * bit store
+ *
+ * However this disrupts the HW while it is happening. There are several
+ * interesting cases where a STE/CD can be updated without disturbing the HW
+ * because only a small number of bits are changing (S1DSS, CONFIG, etc) or
+ * because the used bits don't intersect. We can detect this by calculating how
+ * many 64 bit values need update after adjusting the unused bits and skip the
+ * V=0 process. This relies on the IGNORED behavior described in the
+ * specification.
+ */
+static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid,
+ struct arm_smmu_ste *entry,
+ const struct arm_smmu_ste *target)
+{
+ unsigned int num_entry_qwords = ARRAY_SIZE(target->data);
+ struct arm_smmu_device *smmu = master->smmu;
+ struct arm_smmu_ste unused_update;
+ u8 used_qword_diff;
+
+ used_qword_diff =
+ arm_smmu_entry_qword_diff(entry, target, &unused_update);
+ if (hweight8(used_qword_diff) == 1) {
+ /*
+ * Only one qword needs its used bits to be changed. This is a
+ * hitless update, update all bits the current STE is ignoring
+ * to their new values, then update a single "critical qword" to
+ * change the STE and finally 0 out any bits that are now unused
+ * in the target configuration.
+ */
+ unsigned int critical_qword_index = ffs(used_qword_diff) - 1;
+
+ /*
+ * Skip writing unused bits in the critical qword since we'll be
+ * writing it in the next step anyways. This can save a sync
+ * when the only change is in that qword.
+ */
+ unused_update.data[critical_qword_index] =
+ entry->data[critical_qword_index];
+ entry_set(smmu, sid, entry, &unused_update, 0, num_entry_qwords);
+ entry_set(smmu, sid, entry, target, critical_qword_index, 1);
+ entry_set(smmu, sid, entry, target, 0, num_entry_qwords);
+ } else if (used_qword_diff) {
+ /*
+ * At least two qwords need their inuse bits to be changed. This
+ * requires a breaking update, zero the V bit, write all qwords
+ * but 0, then set qword 0
+ */
+ unused_update.data[0] = entry->data[0] & (~STRTAB_STE_0_V);
+ entry_set(smmu, sid, entry, &unused_update, 0, 1);
+ entry_set(smmu, sid, entry, target, 1, num_entry_qwords - 1);
+ entry_set(smmu, sid, entry, target, 0, 1);
+ } else {
+ /*
+ * No inuse bit changed. Sanity check that all unused bits are 0
+ * in the entry. The target was already sanity checked by
+ * compute_qword_diff().
+ */
+ WARN_ON_ONCE(
+ entry_set(smmu, sid, entry, target, 0, num_entry_qwords));
+ }
+
+ /* It's likely that we'll want to use the new STE soon */
+ if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) {
+ struct arm_smmu_cmdq_ent
+ prefetch_cmd = { .opcode = CMDQ_OP_PREFETCH_CFG,
+ .prefetch = {
+ .sid = sid,
+ } };
+
+ arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
+ }
+}
+
static void arm_smmu_sync_cd(struct arm_smmu_master *master,
int ssid, bool leaf)
{
@@ -1483,34 +1679,12 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
struct arm_smmu_ste *dst)
{
- /*
- * This is hideously complicated, but we only really care about
- * three cases at the moment:
- *
- * 1. Invalid (all zero) -> bypass/fault (init)
- * 2. Bypass/fault -> translation/bypass (attach)
- * 3. Translation/bypass -> bypass/fault (detach)
- *
- * Given that we can't update the STE atomically and the SMMU
- * doesn't read the thing in a defined order, that leaves us
- * with the following maintenance requirements:
- *
- * 1. Update Config, return (init time STEs aren't live)
- * 2. Write everything apart from dword 0, sync, write dword 0, sync
- * 3. Update Config, sync
- */
- u64 val = le64_to_cpu(dst->data[0]);
- bool ste_live = false;
+ u64 val;
struct arm_smmu_device *smmu = master->smmu;
struct arm_smmu_ctx_desc_cfg *cd_table = NULL;
struct arm_smmu_s2_cfg *s2_cfg = NULL;
struct arm_smmu_domain *smmu_domain = master->domain;
- struct arm_smmu_cmdq_ent prefetch_cmd = {
- .opcode = CMDQ_OP_PREFETCH_CFG,
- .prefetch = {
- .sid = sid,
- },
- };
+ struct arm_smmu_ste target = {};
if (smmu_domain) {
switch (smmu_domain->stage) {
@@ -1525,22 +1699,6 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
}
}
- if (val & STRTAB_STE_0_V) {
- switch (FIELD_GET(STRTAB_STE_0_CFG, val)) {
- case STRTAB_STE_0_CFG_BYPASS:
- break;
- case STRTAB_STE_0_CFG_S1_TRANS:
- case STRTAB_STE_0_CFG_S2_TRANS:
- ste_live = true;
- break;
- case STRTAB_STE_0_CFG_ABORT:
- BUG_ON(!disable_bypass);
- break;
- default:
- BUG(); /* STE corruption */
- }
- }
-
/* Nuke the existing STE_0 value, as we're going to rewrite it */
val = STRTAB_STE_0_V;
@@ -1551,16 +1709,11 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
else
val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
- dst->data[0] = cpu_to_le64(val);
- dst->data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
+ target.data[0] = cpu_to_le64(val);
+ target.data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
STRTAB_STE_1_SHCFG_INCOMING));
- dst->data[2] = 0; /* Nuke the VMID */
- /*
- * The SMMU can perform negative caching, so we must sync
- * the STE regardless of whether the old value was live.
- */
- if (smmu)
- arm_smmu_sync_ste_for_sid(smmu, sid);
+ target.data[2] = 0; /* Nuke the VMID */
+ arm_smmu_write_ste(master, sid, dst, &target);
return;
}
@@ -1568,8 +1721,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ?
STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1;
- BUG_ON(ste_live);
- dst->data[1] = cpu_to_le64(
+ target.data[1] = cpu_to_le64(
FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) |
FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
@@ -1578,7 +1730,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
if (smmu->features & ARM_SMMU_FEAT_STALLS &&
!master->stall_enabled)
- dst->data[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
+ target.data[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
val |= (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) |
@@ -1587,8 +1739,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
}
if (s2_cfg) {
- BUG_ON(ste_live);
- dst->data[2] = cpu_to_le64(
+ target.data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
+ STRTAB_STE_1_SHCFG_INCOMING));
+ target.data[2] = cpu_to_le64(
FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) |
FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) |
#ifdef __BIG_ENDIAN
@@ -1597,23 +1750,17 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
STRTAB_STE_2_S2R);
- dst->data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
+ target.data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
}
if (master->ats_enabled)
- dst->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS,
+ target.data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS,
STRTAB_STE_1_EATS_TRANS));
- arm_smmu_sync_ste_for_sid(smmu, sid);
- /* See comment in arm_smmu_write_ctx_desc() */
- WRITE_ONCE(dst->data[0], cpu_to_le64(val));
- arm_smmu_sync_ste_for_sid(smmu, sid);
-
- /* It's likely that we'll want to use the new STE soon */
- if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH))
- arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
+ target.data[0] = cpu_to_le64(val);
+ arm_smmu_write_ste(master, sid, dst, &target);
}
static void arm_smmu_init_bypass_stes(struct arm_smmu_ste *strtab,
--
2.33.0
Hi Ze,
FYI, the error/warning still remains.
tree: https://gitee.com/openeuler/kernel.git OLK-5.10
head: 4cbb736395eb31ff181c4488182276601992fa0b
commit: 0695e18bbaebbfbe22b049104bbb9a4300a9f30c [2439/2439] mm: Add PMU based memory sampling abstract layer
config: arm64-randconfig-004-20241117 (https://download.01.org/0day-ci/archive/20241117/202411171805.sOdLtjgt-lkp@…)
compiler: aarch64-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241117/202411171805.sOdLtjgt-lkp@…)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp(a)intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411171805.sOdLtjgt-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/compiler_types.h:65,
from <command-line>:
drivers/arm/spe/spe.c: In function '__arm_spe_dev_probe':
>> include/linux/compiler_attributes.h:221:41: warning: attribute 'fallthrough' not preceding a case label or default label
221 | # define fallthrough __attribute__((__fallthrough__))
| ^~~~~~~~~~~~~
drivers/arm/spe/spe.c:492:17: note: in expansion of macro 'fallthrough'
492 | fallthrough;
| ^~~~~~~~~~~
>> include/linux/compiler_attributes.h:221:41: warning: attribute 'fallthrough' not preceding a case label or default label
221 | # define fallthrough __attribute__((__fallthrough__))
| ^~~~~~~~~~~~~
drivers/arm/spe/spe.c:514:17: note: in expansion of macro 'fallthrough'
514 | fallthrough;
| ^~~~~~~~~~~
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for ARM_SPE_MEM_SAMPLING
Depends on [n]: ARM64 [=y] && !ARM_SPE_PMU [=y]
Selected by [y]:
- MEM_SAMPLING [=y] && ARM64 [=y]
vim +/fallthrough +221 include/linux/compiler_attributes.h
294f69e662d157 Joe Perches 2019-10-05 209
294f69e662d157 Joe Perches 2019-10-05 210 /*
294f69e662d157 Joe Perches 2019-10-05 211 * Add the pseudo keyword 'fallthrough' so case statement blocks
294f69e662d157 Joe Perches 2019-10-05 212 * must end with any of these keywords:
294f69e662d157 Joe Perches 2019-10-05 213 * break;
294f69e662d157 Joe Perches 2019-10-05 214 * fallthrough;
294f69e662d157 Joe Perches 2019-10-05 215 * goto <label>;
294f69e662d157 Joe Perches 2019-10-05 216 * return [expression];
294f69e662d157 Joe Perches 2019-10-05 217 *
294f69e662d157 Joe Perches 2019-10-05 218 * gcc: https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html#Statement-Attr…
294f69e662d157 Joe Perches 2019-10-05 219 */
294f69e662d157 Joe Perches 2019-10-05 220 #if __has_attribute(__fallthrough__)
294f69e662d157 Joe Perches 2019-10-05 @221 # define fallthrough __attribute__((__fallthrough__))
294f69e662d157 Joe Perches 2019-10-05 222 #else
294f69e662d157 Joe Perches 2019-10-05 223 # define fallthrough do {} while (0) /* fallthrough */
a3f8a30f3f0079 Miguel Ojeda 2018-08-30 224 #endif
a3f8a30f3f0079 Miguel Ojeda 2018-08-30 225
:::::: The code at line 221 was first introduced by commit
:::::: 294f69e662d1570703e9b56e95be37a9fd3afba5 compiler_attributes.h: Add 'fallthrough' pseudo keyword for switch/case use
:::::: TO: Joe Perches <joe(a)perches.com>
:::::: CC: Linus Torvalds <torvalds(a)linux-foundation.org>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
tree: https://gitee.com/openeuler/kernel.git OLK-6.6
head: 7c547c6bbe6b6a9cedf63d7cdadb2529404df633
commit: b89997c5e3ffa58c43c4cb3547eb0c11b75d0634 [1474/1474] IMA support script execution check
config: x86_64-buildonly-randconfig-001-20241117 (https://download.01.org/0day-ci/archive/20241117/202411171510.9dZc68aH-lkp@…)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241117/202411171510.9dZc68aH-lkp@…)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp(a)intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411171510.9dZc68aH-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from security/security.c:14:
In file included from include/linux/bpf.h:21:
In file included from include/linux/kallsyms.h:13:
In file included from include/linux/mm.h:2247:
include/linux/vmstat.h:522:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
522 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
| ~~~~~~~~~~~ ^ ~~~
>> security/security.c:1071:9: error: call to undeclared function 'ima_bprm_creds_for_exec'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
1071 | return ima_bprm_creds_for_exec(bprm);
| ^
security/security.c:1071:9: note: did you mean 'security_bprm_creds_for_exec'?
security/security.c:1064:5: note: 'security_bprm_creds_for_exec' declared here
1064 | int security_bprm_creds_for_exec(struct linux_binprm *bprm)
| ^
1065 | {
1066 | int ret;
1067 |
1068 | ret = call_int_hook(bprm_creds_for_exec, 0, bprm);
1069 | if (ret)
1070 | return ret;
1071 | return ima_bprm_creds_for_exec(bprm);
| ~~~~~~~~~~~~~~~~~~~~~~~
| security_bprm_creds_for_exec
1 warning and 1 error generated.
vim +/ima_bprm_creds_for_exec +1071 security/security.c
1043
1044 /**
1045 * security_bprm_creds_for_exec() - Prepare the credentials for exec()
1046 * @bprm: binary program information
1047 *
1048 * If the setup in prepare_exec_creds did not setup @bprm->cred->security
1049 * properly for executing @bprm->file, update the LSM's portion of
1050 * @bprm->cred->security to be what commit_creds needs to install for the new
1051 * program. This hook may also optionally check permissions (e.g. for
1052 * transitions between security domains). The hook must set @bprm->secureexec
1053 * to 1 if AT_SECURE should be set to request libc enable secure mode. @bprm
1054 * contains the linux_binprm structure.
1055 *
1056 * If execveat(2) is called with the AT_CHECK flag, bprm->is_check is set. The
1057 * result must be the same as without this flag even if the execution will
1058 * never really happen and @bprm will always be dropped.
1059 *
1060 * This hook must not change current->cred, only @bprm->cred.
1061 *
1062 * Return: Returns 0 if the hook is successful and permission is granted.
1063 */
1064 int security_bprm_creds_for_exec(struct linux_binprm *bprm)
1065 {
1066 int ret;
1067
1068 ret = call_int_hook(bprm_creds_for_exec, 0, bprm);
1069 if (ret)
1070 return ret;
> 1071 return ima_bprm_creds_for_exec(bprm);
1072 }
1073
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi laokz,
FYI, the error/warning still remains.
tree: https://gitee.com/openeuler/kernel.git OLK-6.6
head: 7c547c6bbe6b6a9cedf63d7cdadb2529404df633
commit: b8f3220637be1736c165c289c634f27841ac4e01 [1474/1474] livepatch: add arch hook before doing klp_resolve_symbols
config: arm64-randconfig-003-20241117 (https://download.01.org/0day-ci/archive/20241117/202411171312.1qX29CJl-lkp@…)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241117/202411171312.1qX29CJl-lkp@…)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp(a)intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411171312.1qX29CJl-lkp@intel.com/
All warnings (new ones prefixed by >>):
kernel/livepatch/core.c:97:12: warning: no previous prototype for function 'arch_klp_init_func' [-Wmissing-prototypes]
int __weak arch_klp_init_func(struct klp_object *obj, struct klp_func *func)
^
kernel/livepatch/core.c:97:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int __weak arch_klp_init_func(struct klp_object *obj, struct klp_func *func)
^
static
>> kernel/livepatch/core.c:216:13: warning: no previous prototype for function 'arch_klp_skip_resolve' [-Wmissing-prototypes]
bool __weak arch_klp_skip_resolve(unsigned int type)
^
kernel/livepatch/core.c:216:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
bool __weak arch_klp_skip_resolve(unsigned int type)
^
static
kernel/livepatch/core.c:1767:12: warning: no previous prototype for function 'arch_klp_check_activeness_func' [-Wmissing-prototypes]
int __weak arch_klp_check_activeness_func(struct klp_func *func, int enable,
^
kernel/livepatch/core.c:1767:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int __weak arch_klp_check_activeness_func(struct klp_func *func, int enable,
^
static
kernel/livepatch/core.c:2022:14: warning: no previous prototype for function 'arch_klp_mem_alloc' [-Wmissing-prototypes]
void __weak *arch_klp_mem_alloc(size_t size)
^
kernel/livepatch/core.c:2022:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak *arch_klp_mem_alloc(size_t size)
^
static
kernel/livepatch/core.c:2027:13: warning: no previous prototype for function 'arch_klp_mem_free' [-Wmissing-prototypes]
void __weak arch_klp_mem_free(void *mem)
^
kernel/livepatch/core.c:2027:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_mem_free(void *mem)
^
static
kernel/livepatch/core.c:2032:13: warning: no previous prototype for function 'arch_klp_code_modify_prepare' [-Wmissing-prototypes]
void __weak arch_klp_code_modify_prepare(void)
^
kernel/livepatch/core.c:2032:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_code_modify_prepare(void)
^
static
kernel/livepatch/core.c:2036:13: warning: no previous prototype for function 'arch_klp_code_modify_post_process' [-Wmissing-prototypes]
void __weak arch_klp_code_modify_post_process(void)
^
kernel/livepatch/core.c:2036:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_code_modify_post_process(void)
^
static
kernel/livepatch/core.c:2049:12: warning: no previous prototype for function 'arch_klp_check_breakpoint' [-Wmissing-prototypes]
int __weak arch_klp_check_breakpoint(struct arch_klp_data *arch_data, void *old_func)
^
kernel/livepatch/core.c:2049:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int __weak arch_klp_check_breakpoint(struct arch_klp_data *arch_data, void *old_func)
^
static
kernel/livepatch/core.c:2063:13: warning: no previous prototype for function 'arch_klp_set_brk_func' [-Wmissing-prototypes]
void __weak arch_klp_set_brk_func(struct klp_func_node *func_node, void *new_func)
^
kernel/livepatch/core.c:2063:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_set_brk_func(struct klp_func_node *func_node, void *new_func)
^
static
9 warnings generated.
vim +/arch_klp_skip_resolve +216 kernel/livepatch/core.c
214
215 #ifdef CONFIG_LIVEPATCH_WO_FTRACE
> 216 bool __weak arch_klp_skip_resolve(unsigned int type)
217 {
218 return false;
219 }
220 #endif
221
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
tree: https://gitee.com/openeuler/kernel.git OLK-6.6
head: 7c547c6bbe6b6a9cedf63d7cdadb2529404df633
commit: eabc33c6f2c91168537f10e9275b0921c9f78c45 [1474/1474] livepatch/ppc64: Implement livepatch without ftrace for ppc64be
config: arm64-randconfig-003-20241117 (https://download.01.org/0day-ci/archive/20241117/202411171106.SNb1bUTk-lkp@…)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241117/202411171106.SNb1bUTk-lkp@…)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp(a)intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411171106.SNb1bUTk-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> kernel/livepatch/core.c:97:12: warning: no previous prototype for function 'arch_klp_init_func' [-Wmissing-prototypes]
int __weak arch_klp_init_func(struct klp_object *obj, struct klp_func *func)
^
kernel/livepatch/core.c:97:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int __weak arch_klp_init_func(struct klp_object *obj, struct klp_func *func)
^
static
kernel/livepatch/core.c:1756:12: warning: no previous prototype for function 'arch_klp_check_activeness_func' [-Wmissing-prototypes]
int __weak arch_klp_check_activeness_func(struct klp_func *func, int enable,
^
kernel/livepatch/core.c:1756:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int __weak arch_klp_check_activeness_func(struct klp_func *func, int enable,
^
static
kernel/livepatch/core.c:2011:14: warning: no previous prototype for function 'arch_klp_mem_alloc' [-Wmissing-prototypes]
void __weak *arch_klp_mem_alloc(size_t size)
^
kernel/livepatch/core.c:2011:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak *arch_klp_mem_alloc(size_t size)
^
static
kernel/livepatch/core.c:2016:13: warning: no previous prototype for function 'arch_klp_mem_free' [-Wmissing-prototypes]
void __weak arch_klp_mem_free(void *mem)
^
kernel/livepatch/core.c:2016:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_mem_free(void *mem)
^
static
kernel/livepatch/core.c:2021:13: warning: no previous prototype for function 'arch_klp_code_modify_prepare' [-Wmissing-prototypes]
void __weak arch_klp_code_modify_prepare(void)
^
kernel/livepatch/core.c:2021:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_code_modify_prepare(void)
^
static
kernel/livepatch/core.c:2025:13: warning: no previous prototype for function 'arch_klp_code_modify_post_process' [-Wmissing-prototypes]
void __weak arch_klp_code_modify_post_process(void)
^
kernel/livepatch/core.c:2025:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_code_modify_post_process(void)
^
static
kernel/livepatch/core.c:2038:12: warning: no previous prototype for function 'arch_klp_check_breakpoint' [-Wmissing-prototypes]
int __weak arch_klp_check_breakpoint(struct arch_klp_data *arch_data, void *old_func)
^
kernel/livepatch/core.c:2038:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int __weak arch_klp_check_breakpoint(struct arch_klp_data *arch_data, void *old_func)
^
static
kernel/livepatch/core.c:2052:13: warning: no previous prototype for function 'arch_klp_set_brk_func' [-Wmissing-prototypes]
void __weak arch_klp_set_brk_func(struct klp_func_node *func_node, void *new_func)
^
kernel/livepatch/core.c:2052:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void __weak arch_klp_set_brk_func(struct klp_func_node *func_node, void *new_func)
^
static
8 warnings generated.
vim +/arch_klp_init_func +97 kernel/livepatch/core.c
96
> 97 int __weak arch_klp_init_func(struct klp_object *obj, struct klp_func *func)
98 {
99 return 0;
100 }
101 #endif /* CONFIG_LIVEPATCH_FTRACE */
102
--
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