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[PATCH OLK-6.6] net: ipa: fix event ring index not programmed for IPA v5.0+
by Wupeng Ma 14 May '26

14 May '26

From: Alexander Koskovich <akoskovich(a)pm.me> stable inclusion from stable-v6.6.136 commit ae8343a19ccb051d519dbb3a9082ddea9f0551d3 category: bugfix bugzilla: https://atomgit.com/src-openeuler/kernel/issues/14903 CVE: CVE-2026-43345 Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id… -------------------------------- [ Upstream commit 56007972c0b1e783ca714d6f1f4d6e66e531d21f ] For IPA v5.0+, the event ring index field moved from CH_C_CNTXT_0 to CH_C_CNTXT_1. The v5.0 register definition intended to define this field in the CH_C_CNTXT_1 fmask array but used the old identifier of ERINDEX instead of CH_ERINDEX. Without a valid event ring, GSI channels could never signal transfer completions. This caused gsi_channel_trans_quiesce() to block forever in wait_for_completion(). At least for IPA v5.2 this resolves an issue seen where runtime suspend, system suspend, and remoteproc stop all hanged forever. It also meant the IPA data path was completely non functional. Fixes: faf0678ec8a0 ("net: ipa: add IPA v5.0 GSI register definitions") Signed-off-by: Alexander Koskovich <akoskovich(a)pm.me> Signed-off-by: Luca Weiss <luca.weiss(a)fairphone.com> Reviewed-by: Simon Horman <horms(a)kernel.org> Link: https://patch.msgid.link/20260403-milos-ipa-v1-2-01e9e4e03d3e@fairphone.com Signed-off-by: Paolo Abeni <pabeni(a)redhat.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> Signed-off-by: Wupeng Ma <mawupeng1(a)huawei.com> --- drivers/net/ipa/reg/gsi_reg-v5.0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ipa/reg/gsi_reg-v5.0.c b/drivers/net/ipa/reg/gsi_reg-v5.0.c index 145eb0bd096d..ff71a95557c7 100644 --- a/drivers/net/ipa/reg/gsi_reg-v5.0.c +++ b/drivers/net/ipa/reg/gsi_reg-v5.0.c @@ -28,7 +28,7 @@ REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, static const u32 reg_ch_c_cntxt_1_fmask[] = { [CH_R_LENGTH] = GENMASK(23, 0), - [ERINDEX] = GENMASK(31, 24), + [CH_ERINDEX] = GENMASK(31, 24), }; REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, -- 2.43.0

2 1

[PATCH OLK-6.6 v2 0/3] optimize copy_from_user
by Qi Xi 14 May '26

14 May '26

This patchset adds an optimized copy_from_user path for Hisilicon HIP11/HIP12/Linxicore9100, using ldp/stp instructions with PAN temporarily disabled during the copy. Patch 1 adds the HIP11 MIDR definition. Patch 2 implements the optimized path and the raw_copy_from_user routing. Patch 3 adds CONFIG_ARM64_COPY_FROM_USER_OPT compile-time gating. v2 changes: - add HISI_CPU_PART_HIP11 - merge the asm implementation and the uaccess.h routing into a single patch to avoid bisect breakage - fix compile error when CONFIG_ARM64_COPY_FROM_USER_OPT=n Qi Xi (3): arm64: cputype: Add CPU type for HISI_CPU_PART_HIP11 arm64: uaccess: add optimized copy_from_user for Hisilicon platforms arm64: uaccess: add CONFIG control for copy_from_user_opt .../admin-guide/kernel-parameters.txt | 6 + arch/arm64/Kconfig | 11 + arch/arm64/include/asm/asm-uaccess.h | 11 + arch/arm64/include/asm/cputype.h | 2 + arch/arm64/include/asm/uaccess.h | 30 ++- arch/arm64/kernel/cpufeature.c | 36 ++++ arch/arm64/lib/copy_from_user.S | 36 ++++ arch/arm64/lib/copy_template_opt.S | 189 ++++++++++++++++++ arch/arm64/tools/cpucaps | 2 +- tools/arch/arm64/include/asm/cputype.h | 2 + 10 files changed, 322 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/lib/copy_template_opt.S -- 2.33.0

2 4

[PATCH OLK-6.6 00/36] perf arm-spe: Extend branch operations
by Yushan Wang 14 May '26

14 May '26

From: Ying Jiang<jiangying44(a)h-partners.com> In Arm ARM (ARM DDI 0487, L.a), the section "D18.2.7 Operation Type packet", the branch subclass is extended for Call Return (CR), Guarded control stack data access (GCS). This commit adds support CR and GCS operations. The IND (indirect) operation is defined only in bit [1], its macro is updated accordingly. Move the COND (Conditional) macro into the same group with other operations for better maintenance. Anshuman Khandual (9): arm64: Handle BRBE booting requirements arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 arm64/sysreg: Add register fields for HDFGRTR2_EL2 arm64/sysreg: Add register fields for HDFGWTR2_EL2 arm64/sysreg: Add register fields for HFGITR2_EL2 arm64/sysreg: Add register fields for HFGRTR2_EL2 arm64/sysreg: Add register fields for HFGWTR2_EL2 arm64/sysreg: Update ID_DFR0_EL1 register fields arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 Dave Martin (1): arm64: el2_setup.h: Rename some labels to be more diff-friendly James Clark (12): perf: arm_spe: Add format option for discard mode arm64: sysreg: Add new PMSFCR_EL1 fields and PMSDSFR_EL1 register perf: arm_spe: Support FEAT_SPEv1p4 filters perf: arm_spe: Add support for FEAT_SPE_EFT extended filtering arm64/boot: Factor out a macro to check SPE version arm64/boot: Enable EL2 requirements for SPE_FEAT_FDS KVM: arm64: Add trap configs for PMSDSFR_EL1 perf: Add perf_event_attr::config4 perf: arm_spe: Add support for filtering on data source tools headers UAPI: Sync linux/perf_event.h with the kernel sources perf tools: Add support for perf_event_attr::config4 perf docs: arm-spe: Document new SPE filtering features Leo Yan (1): perf: arm_spe: Expose event filter Marc Zyngier (5): KVM: arm64: Shave a few bytes from the EL2 idmap code arm64/sysreg: Allow a 'Mapping' descriptor for system registers arm64: sysreg: Add registers trapped by HDFG{R,W}TR2_EL2 KVM: arm64: nv: Add include containing the VNCR_EL2 offsets arm64: sysreg: Update PMSIDR_EL1 description Rob Herring (Arm) (4): arm64: el2_setup.h: Make __init_el2_fgt labels consistent, again perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control perf: arm_pmu: Use of_property_present() perf: arm_pmu: Remove event index to counter remapping Yushan Wang (4): Revert "arm64/boot: Enable EL2 requirements for BRBE" perf: Fix hw_metric event idx config perf: Keep event consistency of hw_metric events arm_pmuv3: hw_metric: Remove unnecessary check of event type Documentation/arch/arm64/booting.rst | 75 +++- arch/arm64/include/asm/el2_setup.h | 130 +++--- arch/arm64/include/asm/kvm_asm.h | 1 + arch/arm64/include/asm/sysreg.h | 19 +- arch/arm64/include/asm/vncr_mapping.h | 105 +++++ arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kvm/emulate-nested.c | 1 + arch/arm64/kvm/hyp/nvhe/hyp-init.S | 52 ++- arch/arm64/kvm/pmu-emul.c | 6 +- arch/arm64/kvm/sys_regs.c | 1 + arch/arm64/tools/gen-sysreg.awk | 2 +- arch/arm64/tools/sysreg | 502 +++++++++++++++++++++- drivers/perf/apple_m1_cpu_pmu.c | 4 +- drivers/perf/arm_pmu.c | 11 +- drivers/perf/arm_pmu_platform.c | 2 +- drivers/perf/arm_pmuv3.c | 68 +-- drivers/perf/arm_spe_pmu.c | 170 +++++++- include/linux/perf/arm_pmu.h | 2 +- include/linux/perf/arm_pmuv3.h | 1 + include/uapi/linux/perf_event.h | 4 + tools/include/uapi/linux/perf_event.h | 2 + tools/perf/Documentation/perf-arm-spe.txt | 103 ++++- tools/perf/tests/parse-events.c | 14 +- tools/perf/util/parse-events.c | 11 + tools/perf/util/parse-events.h | 1 + tools/perf/util/parse-events.l | 1 + tools/perf/util/pmu.c | 3 + tools/perf/util/pmu.h | 1 + 28 files changed, 1098 insertions(+), 195 deletions(-) create mode 100644 arch/arm64/include/asm/vncr_mapping.h -- 2.33.0

2 37

[PATCH OLK-5.10 0/7] net/oenetcls: RPS enhancements and bug fixes
by Li Xiasong 13 May '26

13 May '26

This series introduces several RPS (Receive Packet Steering) enhancements for oenetcls, including NUMA-aware flow scheduling, IPv6 ntuple support, RXQ multiplexing, and phy NIC policy switch, along with bug fixes for hash collision and limiting rxqs against combined_channels. Yue Haibing (7): net/oenetcls: Fix possible hash collision issue net/oenetcls: Add local flow NUMA-aware rps net/oenetcls: Supports rxq multiplexing net/oenetcls: Support ipv6 for ntuple mode net/oenetcls: Make OENETCLS default as module net/oenetcls: Add rps policy switch for phy NIC net/oenetcls: Limit rxqs against combined_channels include/linux/oenetcls.h | 38 ++++- include/linux/skbuff.h | 4 + include/net/sock.h | 4 + net/core/dev.c | 8 + net/core/sock.c | 3 + net/ipv4/tcp.c | 5 +- net/oenetcls/Kconfig | 11 +- net/oenetcls/oenetcls.h | 28 +++- net/oenetcls/oenetcls_flow.c | 284 ++++++++++++++++++++++++--------- net/oenetcls/oenetcls_main.c | 154 +++++++++++++----- net/oenetcls/oenetcls_ntuple.c | 255 ++++++++++++++++++----------- 11 files changed, 567 insertions(+), 227 deletions(-) -- 2.34.1

2 8

[PATCH OLK-6.6 v7 0/4] optimize copy_from_user
by Qi Xi 13 May '26

13 May '26

v7 changes: - add HISI_CPU_PART_HIP11 v6 changes: - rename cmdline param "copy_opt=off" to "copy_opt_disable" v5 changes: - replace cpus_have_const_cap with alternative_has_cap_unlikely v4 changes: - handle copy_opt=off via has_copy_opt() to clear ARM64_HAS_COPY_OPT v3 changes: - Introduce CONFIG_ARM64_COPY_FROM_USER_OPT and a "copy_opt=off" cmdline parameter to disable it. v2 changes: - Merge patch 1 and 2 into a single feature patch that adds the optimized copy_from_user implementation. - Change cpufeature description and delete unnecessary pr_info. Qi Xi (4): arm64: cputype: Add CPU type for HISI_CPU_PART_HIP11 arm64: lib: add __arch_copy_from_user_opt with index-addressed ldp/stp arm64: uaccess: enable optimized copy_from_user for >= 4kb copies arm64: uaccess: add CONFIG control for copy_from_user_opt .../admin-guide/kernel-parameters.txt | 6 + arch/arm64/Kconfig | 11 + arch/arm64/include/asm/asm-uaccess.h | 7 + arch/arm64/include/asm/cputype.h | 2 + arch/arm64/include/asm/uaccess.h | 31 ++- arch/arm64/kernel/cpufeature.c | 35 ++++ arch/arm64/lib/copy_from_user.S | 36 ++++ arch/arm64/lib/copy_template_opt.S | 189 ++++++++++++++++++ arch/arm64/tools/cpucaps | 2 +- tools/arch/arm64/include/asm/cputype.h | 2 + 10 files changed, 318 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/lib/copy_template_opt.S -- 2.33.0

2 5

[PATCH OLK-6.6] Revert "!21796 [OLK-6.6] x86/mce/zhaoxin: Enable mcelog to decode PCIE, ZDI/ZPI, and DRAM errors"
by Tengda Wu 13 May '26

13 May '26

hulk inclusion category: bugfix bugzilla: https://atomgit.com/openeuler/kernel/issues/9160 -------------------------------- This reverts commit f9b4fa77d0c477fbaebfdebd1259e387b88824da, reversing changes made to 6bcb72eb0f8795e6d0f89c92d5797672c28ab641. The commit 6bcb72eb0f87 has introduced a kernel build error: In function ‘zx_apei_mce_report_mem_error’: arch/x86/kernel/cpu/mce/apei.c:79:9: error: implicit declaration of function ‘mce_setup’; did you mean ‘memset_p’? [-Werror=implicit-function-declaration] 79 | mce_setup(&m); | ^~~~~~~~~ | memset_p arch/x86/kernel/cpu/mce/apei.c:130:17: error: passing argument 1 of ‘mce_log’ from incompatible pointer type [-Werror=incompatible-pointer-types] 130 | mce_log(&m); | ^~ | | | struct mce * Temporarily revert to mitigate. Fixes: 6bcb72eb0f87 ("!21795 [OLK-6.6] efi/cper: Add Zhaoxin mem error decode for KH-50000") Signed-off-by: Tengda Wu <wutengda2(a)huawei.com> --- arch/x86/include/asm/mce.h | 6 -- arch/x86/kernel/acpi/apei.c | 28 +----- arch/x86/kernel/cpu/mce/apei.c | 167 --------------------------------- drivers/acpi/apei/apei-base.c | 11 --- drivers/acpi/apei/ghes.c | 34 +------ include/acpi/apei.h | 2 - 6 files changed, 5 insertions(+), 243 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index ce4ffe3d844c..a795f963da1f 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -336,12 +336,6 @@ struct cper_sec_mem_err; extern void apei_mce_report_mem_error(int corrected, struct cper_sec_mem_err *mem_err); -extern void zx_apei_mce_report_mem_error(struct cper_sec_mem_err *mem_err); -struct cper_sec_pcie; -extern void zx_apei_mce_report_pcie_error(int corrected, struct cper_sec_pcie *pcie_err); -struct cper_sec_proc_generic; -extern void zx_apei_mce_report_zdi_error(struct cper_sec_proc_generic *zdi_err); - /* * Enumerate new IP types and HWID values in AMD processors which support * Scalable MCA. diff --git a/arch/x86/kernel/acpi/apei.c b/arch/x86/kernel/acpi/apei.c index 7cb88cd5b9d3..e21419e686eb 100644 --- a/arch/x86/kernel/acpi/apei.c +++ b/arch/x86/kernel/acpi/apei.c @@ -42,36 +42,10 @@ int arch_apei_enable_cmcff(struct acpi_hest_header *hest_hdr, void *data) void arch_apei_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) { #ifdef CONFIG_X86_MCE - if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || - boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) - zx_apei_mce_report_mem_error(mem_err); - else - apei_mce_report_mem_error(sev, mem_err); + apei_mce_report_mem_error(sev, mem_err); #endif } -void arch_apei_report_pcie_error(int sev, struct cper_sec_pcie *pcie_err) -{ -#ifdef CONFIG_X86_MCE - if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || - boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) - zx_apei_mce_report_pcie_error(sev, pcie_err); -#endif -} - -bool arch_apei_report_zdi_error(guid_t *sec_type, struct cper_sec_proc_generic *zdi_err) -{ -#ifdef CONFIG_X86_MCE - if ((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR || - boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) && - (guid_equal(sec_type, &CPER_SEC_PROC_GENERIC))) { - zx_apei_mce_report_zdi_error(zdi_err); - return true; - } -#endif - return false; -} - int arch_apei_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { return apei_smca_report_x86_error(ctx_info, lapic_id); diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index bdf895a7c38e..7f582b4ca1ca 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -65,173 +65,6 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) } EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); -void zx_apei_mce_report_mem_error(struct cper_sec_mem_err *mem_err) -{ - struct mce m; - int apei_error = 0; - - if (boot_cpu_data.x86 != 7 || boot_cpu_data.x86_model != 91) - return; - - if (!(mem_err->validation_bits & CPER_MEM_VALID_PA)) - return; - - mce_setup(&m); - m.misc = 0; - m.misc = mem_err->module; - m.addr = mem_err->physical_addr; - if (mem_err->card == 0) - m.bank = 9; - else - m.bank = 10; - - switch (mem_err->error_type) { - case 2: - m.status = 0x9c20004000010080; - break; - case 3: - m.status = 0xbe40000000020090; - apei_error = apei_write_mce(&m); - break; - case 8: - if (mem_err->requestor_id == 2) { - m.status = 0x98200040000400b0; - } else if (mem_err->requestor_id == 3) { - m.status = 0xba400000000600a0; - apei_error = apei_write_mce(&m); - } else if (mem_err->requestor_id == 4) { - m.status = 0x98200100000300b0; - } else if (mem_err->requestor_id == 5) { - m.status = 0xba000000000500b0; - apei_error = apei_write_mce(&m); - } else { - pr_info("Undefined Parity error\n"); - } - break; - case 10: - if (mem_err->requestor_id == 6) { - m.status = 0xba400000000700a0; - apei_error = apei_write_mce(&m); - } else if (mem_err->requestor_id == 7) { - m.status = 0xba000000000800b0; - apei_error = apei_write_mce(&m); - } else { - pr_info("Undefined dvad error\n"); - } - break; - case 13: - m.status = 0x9c200040000100c0; - break; - case 14: - m.status = 0xbd000000000200c0; - apei_error = apei_write_mce(&m); - break; - } - mce_log(&m); -} -EXPORT_SYMBOL_GPL(zx_apei_mce_report_mem_error); - -void zx_apei_mce_report_pcie_error(int severity, struct cper_sec_pcie *pcie_err) -{ - struct mce m; - int apei_error = 0; - - if (boot_cpu_data.x86 != 7 || boot_cpu_data.x86_model != 91) - return; - - mce_setup(&m); - m.addr = 0; - m.misc = 0; - m.misc |= (u64)pcie_err->device_id.segment << 32; - m.misc |= pcie_err->device_id.bus << 24; - m.misc |= pcie_err->device_id.device << 19; - m.misc |= pcie_err->device_id.function << 16; - m.bank = 6; - - switch (severity) { - case 1: - m.status = 0x9820004000020e0b; - break; - case 2: - m.status = 0xba20000000010e0b; - break; - case 3: - m.status = 0xbd20000000000e0b; - apei_error = apei_write_mce(&m); - break; - default: - pr_info("Undefine pcie error\n"); - break; - } - mce_log(&m); -} -EXPORT_SYMBOL_GPL(zx_apei_mce_report_pcie_error); - -void zx_apei_mce_report_zdi_error(struct cper_sec_proc_generic *zdi_err) -{ - struct mce m; - int apei_error = 0; - - if (boot_cpu_data.x86 != 7 || boot_cpu_data.x86_model != 91) - return; - - mce_setup(&m); - m.misc = 0; - m.misc |= (zdi_err->requestor_id & 0xff) << 19; - m.misc |= ((zdi_err->requestor_id & 0xff00) >> 8) >> 24; - m.bank = 5; - switch (zdi_err->responder_id) { - case 2: - m.status = 0xba00000000040e0f; - apei_error = apei_write_mce(&m); - break; - case 3: - m.status = 0xba00000000030e0f; - apei_error = apei_write_mce(&m); - break; - case 4: - m.status = 0xba00000000020e0f; - apei_error = apei_write_mce(&m); - break; - case 5: - m.status = 0xba00000000010e0f; - apei_error = apei_write_mce(&m); - break; - case 6: - m.status = 0x9820004000090e0f; - break; - case 7: - m.status = 0x9820004000080e0f; - break; - case 8: - m.status = 0x9820004000070e0f; - break; - case 9: - m.status = 0x9820004000060e0f; - break; - case 10: - m.status = 0x9820004000050e0f; - break; - case 11: - case 12: - case 13: - case 14: - case 15: - m.status = 0x98200040000b0e0f; - break; - case 16: - case 17: - case 18: - m.status = 0x98200040000c0e0f; - break; - default: - pr_info("Undefined ZDI Error\n"); - break; - } - mce_log(&m); -} -EXPORT_SYMBOL_GPL(zx_apei_mce_report_zdi_error); - int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { const u64 *i_mce = ((const u64 *) (ctx_info + 1)); diff --git a/drivers/acpi/apei/apei-base.c b/drivers/acpi/apei/apei-base.c index ad8d5d5e97cc..c7c26872f4ce 100644 --- a/drivers/acpi/apei/apei-base.c +++ b/drivers/acpi/apei/apei-base.c @@ -773,17 +773,6 @@ void __weak arch_apei_report_mem_error(int sev, } EXPORT_SYMBOL_GPL(arch_apei_report_mem_error); -void __weak arch_apei_report_pcie_error(int sev, struct cper_sec_pcie *pcie_err) -{ -} -EXPORT_SYMBOL_GPL(arch_apei_report_pcie_error); - -bool __weak arch_apei_report_zdi_error(guid_t *sec_type, struct cper_sec_proc_generic *zdi_err) -{ - return false; -} -EXPORT_SYMBOL_GPL(arch_apei_report_zdi_error); - int apei_osc_setup(void) { static u8 whea_uuid_str[] = "ed855e0c-6c90-47bf-a62a-26de0fc5ad5c"; diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index b5a382d7a3f2..88b78124a359 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -797,9 +797,6 @@ static void ghes_do_proc(struct ghes *ghes, queued = ghes_handle_memory_failure(gdata, sev, sync); } else if (guid_equal(sec_type, &CPER_SEC_PCIE)) { - struct cper_sec_pcie *pcie_err = acpi_hest_get_payload(gdata); - - arch_apei_report_pcie_error(sec_sev, pcie_err); ghes_handle_aer(gdata); } else if (guid_equal(sec_type, &CPER_SEC_UBUS)) { ghes_handle_ubus_err(gdata); @@ -807,16 +804,12 @@ static void ghes_do_proc(struct ghes *ghes, queued = ghes_handle_arm_hw_error(gdata, sev, sync); } else { void *err = acpi_hest_get_payload(gdata); - - if (!arch_apei_report_zdi_error(sec_type, - (struct cper_sec_proc_generic *)err)) { #ifndef CONFIG_ACPI_APEI_GHES_NOTIFY_ALL_RAS_ERR - ghes_defer_non_standard_event(gdata, sev); + ghes_defer_non_standard_event(gdata, sev); #endif - log_non_standard_event(sec_type, fru_id, fru_text, - sec_sev, err, - gdata->error_data_length); - } + log_non_standard_event(sec_type, fru_id, fru_text, + sec_sev, err, + gdata->error_data_length); } #ifdef CONFIG_ACPI_APEI_GHES_NOTIFY_ALL_RAS_ERR @@ -1199,8 +1192,6 @@ static int ghes_in_nmi_queue_one_entry(struct ghes *ghes, u32 len, node_len; u64 buf_paddr; int sev, rc; - struct acpi_hest_generic_data *gdata; - guid_t *sec_type; if (!IS_ENABLED(CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG)) return -EOPNOTSUPP; @@ -1235,23 +1226,6 @@ static int ghes_in_nmi_queue_one_entry(struct ghes *ghes, sev = ghes_severity(estatus->error_severity); if (sev >= GHES_SEV_PANIC) { - apei_estatus_for_each_section(estatus, gdata) { - sec_type = (guid_t *)gdata->section_type; - if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) { - struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata); - - arch_apei_report_mem_error(sev, mem_err); - } else if (guid_equal(sec_type, &CPER_SEC_PCIE)) { - struct cper_sec_pcie *pcie_err = acpi_hest_get_payload(gdata); - - arch_apei_report_pcie_error(sev, pcie_err); - } else if (guid_equal(sec_type, &CPER_SEC_PROC_GENERIC)) { - struct cper_sec_proc_generic *zdi_err = - acpi_hest_get_payload(gdata); - - arch_apei_report_zdi_error(sec_type, zdi_err); - } - } ghes_print_queued_estatus(); __ghes_panic(ghes, estatus, buf_paddr, fixmap_idx); } diff --git a/include/acpi/apei.h b/include/acpi/apei.h index 808cfa7d16b1..dc60f7db5524 100644 --- a/include/acpi/apei.h +++ b/include/acpi/apei.h @@ -52,8 +52,6 @@ int erst_clear(u64 record_id); int arch_apei_enable_cmcff(struct acpi_hest_header *hest_hdr, void *data); void arch_apei_report_mem_error(int sev, struct cper_sec_mem_err *mem_err); -void arch_apei_report_pcie_error(int sev, struct cper_sec_pcie *pcie_err); -bool arch_apei_report_zdi_error(guid_t *sec_type, struct cper_sec_proc_generic *zdi_err); #endif #endif -- 2.34.1

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[PATCH OLK-6.6 0/8] net/oenetcls: RPS enhancements and bug fixes
by Li Xiasong 13 May '26

13 May '26

This series introduces several RPS (Receive Packet Steering) enhancements for oenetcls, including NUMA-aware flow scheduling, IPv6 ntuple support, RXQ multiplexing, and phy NIC policy switch, along with bug fixes for hash collision. Yue Haibing (8): net/oenetcls: Add mode 2 for rps numa affinity net/oenetcls: Prioritize oenetcls hooks over rps net/oenetcls: Fix possible hash collision issue net/oenetcls: Add local flow NUMA-aware rps net/oenetcls: Supports rxq multiplexing net/oenetcls: Support ipv6 for ntuple mode net/oenetcls: Make OENETCLS default as module net/oenetcls: Add rps policy switch for phy NIC include/linux/oenetcls.h | 38 ++++- include/linux/skbuff.h | 4 + include/net/sock.h | 4 + net/core/dev.c | 37 ++-- net/core/sock.c | 3 + net/ipv4/tcp.c | 5 +- net/oenetcls/Kconfig | 10 +- net/oenetcls/oenetcls.h | 30 +++- net/oenetcls/oenetcls_flow.c | 300 +++++++++++++++++++++++++-------- net/oenetcls/oenetcls_main.c | 188 ++++++++++++++++----- net/oenetcls/oenetcls_ntuple.c | 257 +++++++++++++++++----------- 11 files changed, 632 insertions(+), 244 deletions(-) -- 2.34.1

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[PATCH OLK-6.6 0/3] optimize copy_from_user
by Qi Xi 13 May '26

13 May '26

Qi Xi (3): arm64: lib: add __arch_copy_from_user_opt with index-addressed ldp/stp arm64: uaccess: enable optimized copy_from_user for >= 4kb copies arm64: uaccess: add CONFIG and cmdline control for copy_from_user_opt .../admin-guide/kernel-parameters.txt | 6 + arch/arm64/Kconfig | 11 + arch/arm64/include/asm/asm-uaccess.h | 7 + arch/arm64/include/asm/uaccess.h | 31 ++- arch/arm64/kernel/cpufeature.c | 35 ++++ arch/arm64/lib/copy_from_user.S | 36 ++++ arch/arm64/lib/copy_template_opt.S | 189 ++++++++++++++++++ arch/arm64/tools/cpucaps | 2 +- 8 files changed, 314 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/lib/copy_template_opt.S -- 2.33.0

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[PATCH v4 OLK-6.6 0/4] arm64/ras: Firmware-first SEI error handling with ESB synchronization
by Wupeng Ma 13 May '26

13 May '26

This series introduces firmware-first RAS (Reliability, Availability, and Serviceability) error handling for ARM64 SEI (Synchronous External Interrupt) errors, with support for ESB (Error Synchronization Barrier) synchronization. The implementation includes: - Boot parameter to enable/disable ESB synchronization for SEI - Entry code patching to use ESB instruction for SEI handling - Vendor-specific SEI error handling via APEI/GHES - Sysctl interface for runtime control of vendor SEI handling Liao Chang (1): arm64/entry: Add support to synchronize SEI at the exception boundary Wupeng Ma (2): ACPI/APEI/arm64: add vendor SEI handling for firmware-first RAS arm64: openeuler_defconfig: enable CONFIG_ARM64_SYNC_SEI by default Zheng Chuan (1): arm64: Add runtime switch to control ESB for SEI synchronization Documentation/admin-guide/sysctl/kernel.rst | 27 ++++ arch/arm64/Kconfig | 14 ++ arch/arm64/configs/openeuler_defconfig | 1 + arch/arm64/include/asm/acpi.h | 2 + arch/arm64/include/asm/setup.h | 11 ++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/arm64_sync_sei.c | 124 +++++++++++++++ arch/arm64/kernel/entry.S | 64 ++++++++ arch/arm64/kernel/traps.c | 16 ++ arch/arm64/kernel/vmlinux.lds.S | 9 ++ arch/arm64/kernel/xcall/entry.S | 6 +- drivers/acpi/apei/apei-internal.h | 2 + drivers/acpi/apei/ghes-vendor-info.c | 162 +++++++++++++++++++- drivers/acpi/apei/ghes.c | 5 + 14 files changed, 441 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/kernel/arm64_sync_sei.c -- 2.43.0

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[PATCH OLK-6.6] sched: task_struct kabi test
by Hui Tang 13 May '26

13 May '26

hulk inclusion category: feature bugzilla: https://atomgit.com/openeuler/kernel/issues/8422 ---------------------------------------- Signed-off-by: Hui Tang <tanghui20(a)huawei.com> --- include/linux/sched.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/sched.h b/include/linux/sched.h index a4f1c5e6e013..388cabe57c8b 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1663,6 +1663,7 @@ struct task_struct { * * Do not put anything below here! */ + int sched_ext_test; }; static inline struct pid *task_pid(struct task_struct *task) -- 2.34.1

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