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[PATCH openEuler-1.0-LTS 19/28] RDMA/hns: add eq and cq time cfg compatibility support.
by Cheng Jian 22 Apr '21

22 Apr '21

From: wanglin <wanglin137(a)huawei.com> driver inclusion category: bugfix bugzilla: NA CVE: NA This patch add eq and cq time cfg compatibility support for new Hardware. Reviewed-by: Hu Chunzhi <huchunzhi(a)huawei.com> Reviewed-by: Zhao Weibo <zhaoweibo3(a)huawei.com> Signed-off-by: wanglin <wanglin137(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> Signed-off-by: Cheng Jian <cj.chengjian(a)huawei.com> --- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 69 +++++++++++++++++----- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 5 ++ 2 files changed, 58 insertions(+), 16 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index e1ba9877985b..4e81d1bf2441 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1483,15 +1483,23 @@ static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) { struct hns_roce_cfg_global_param *req; struct hns_roce_cmq_desc desc; + u32 clock_cycles_of_1us; hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, false); req = (struct hns_roce_cfg_global_param *)desc.data; memset(req, 0, sizeof(*req)); + + if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_B) + clock_cycles_of_1us = HNS_ROCE_1NS_CFG; + else + clock_cycles_of_1us = HNS_ROCE_1US_CFG; + roce_set_field(req->time_cfg_udp_port, CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, - CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0); + CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, + clock_cycles_of_1us); roce_set_field(req->time_cfg_udp_port, CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); @@ -4943,6 +4951,29 @@ static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, return ret; } +static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) +{ +#define QP_TIMEOUT_MAX_HIP08 20 +#define QP_TIMEOUT_MAX 31 + + if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_B) { + if (*timeout > QP_TIMEOUT_MAX_HIP08) { + dev_warn(hr_dev->dev, + "Local ACK timeout shall be 0 to 20.\n"); + return false; + } + *timeout += HNS_ROCE_QP_TIMEOUT_OFFSET; + } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08_B) { + if (*timeout > QP_TIMEOUT_MAX) { + dev_warn(hr_dev->dev, + "Local ACK timeout shall be 0 to 31.\n"); + return false; + } + } + + return true; +} + static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, @@ -4951,8 +4982,8 @@ static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, { struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); - struct device *dev = hr_dev->dev; int ret = 0; + u8 timeout; /* The AV component shall be modified for RoCEv2 */ if (attr_mask & IB_QP_AV) { @@ -4963,15 +4994,15 @@ static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, } if (attr_mask & IB_QP_TIMEOUT) { - if (attr->timeout < 21) { + timeout = attr->timeout; + if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, - attr->timeout + 10); + timeout); roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 0); - } else - dev_warn(dev, "Local ACK timeout shall be 0 to 20.\n"); + } } if (attr_mask & IB_QP_RETRY_CNT) { @@ -5598,14 +5629,17 @@ static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 0); - if (cq_period * HNS_ROCE_CLOCK_ADJUST > 0xFFFF) { - dev_info(hr_dev->dev, "Config cq_period param(0x%x) out of range for modify_cq, adjusted to 65.\n", - cq_period); - cq_period = HNS_ROCE_MAX_CQ_PERIOD; + if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_B) { + if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { + dev_info(hr_dev->dev, "cq_period(%d) reached the upper limit, adjusted to 65.\n", + cq_period); + cq_period = HNS_ROCE_MAX_CQ_PERIOD; + } + cq_period *= HNS_ROCE_CLOCK_ADJUST; } roce_set_field(cq_context->byte_56_cqe_period_maxcnt, V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, - cq_period * HNS_ROCE_CLOCK_ADJUST); + cq_period); roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 0); @@ -6166,10 +6200,14 @@ static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev, eqc = mb_buf; memset(eqc, 0, sizeof(struct hns_roce_eq_context)); - if (eq_period * HNS_ROCE_CLOCK_ADJUST > 0xFFFF) { - dev_info(hr_dev->dev, "Config eq_period param(0x%x) out of range for config_eqc, adjusted to 65.\n", - eq_period); - eq_period = HNS_ROCE_MAX_CQ_PERIOD; + eq->eq_period = eq_period; + if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_B) { + if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { + dev_info(hr_dev->dev, "eq_period(%d) reached the upper limit, adjusted to 65.\n", + eq->eq_period); + eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; + } + eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; } /* init eqc */ @@ -6182,7 +6220,6 @@ static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev, eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz; eq->shift = ilog2((unsigned int)eq->entries); eq->eq_max_cnt = eq_max_cnt; - eq->eq_period = eq_period * HNS_ROCE_CLOCK_ADJUST; eq->arm_st = eq_arm_st; if (!eq->hop_num) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index ba81aa607e1d..dad3ac0b4731 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -37,6 +37,11 @@ #define HNS_ROCE_CLOCK_ADJUST 1000 #define HNS_ROCE_MAX_CQ_PERIOD 65 +#define HNS_ROCE_MAX_EQ_PERIOD 65 +#define HNS_ROCE_QP_TIMEOUT_OFFSET 10 + +#define HNS_ROCE_1US_CFG 999 +#define HNS_ROCE_1NS_CFG 0 #define HNS_ROCE_VF_QPC_BT_NUM 256 #define HNS_ROCE_VF_SCCC_BT_NUM 64 -- 2.25.1

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[PATCH openEuler-1.0-LTS 18/28] nvme: fix incorrect behavior when BLKROSET is called by the user
by Cheng Jian 22 Apr '21

22 Apr '21

From: Sagi Grimberg <sagi(a)grimberg.me> mainline inclusion from mainline-5.10 commit 65c5a055b0d567b7e7639d942c0605da9cc54c5e category: bugfix bugzilla: NA CVE: NA ------------------------------------------------- The offending commit breaks BLKROSET ioctl because a device revalidation will blindly override BLKROSET setting. Hence, we remove the disk rw setting in case NVME_NS_ATTR_RO is cleared from by the controller. Fixes: 1293477f4f32 ("nvme: set gendisk read only based on nsattr") Signed-off-by: Sagi Grimberg <sagi(a)grimberg.me> Signed-off-by: Christoph Hellwig <hch(a)lst.de> Signed-off-by: Wenchao Hao <haowenchao(a)huawei.com> Reviewed-by: Miaohe Lin <linmiaohe(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> Signed-off-by: Cheng Jian <cj.chengjian(a)huawei.com> --- drivers/nvme/host/core.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index 8404d3275ce0..cf838c4d032b 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -1625,8 +1625,6 @@ static void nvme_update_disk_info(struct gendisk *disk, if (id->nsattr & (1 << 0)) set_disk_ro(disk, true); - else - set_disk_ro(disk, false); blk_mq_unfreeze_queue(disk->queue); } -- 2.25.1

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[PATCH kernel-4.19 00/13] backport linux-4.19.188
by Yang Yingliang 20 Apr '21

20 Apr '21

Arnaldo Carvalho de Melo (1): perf map: Tighten snprintf() string precision to pass gcc check on some 32-bit arches Arnd Bergmann (1): drm/imx: imx-ldb: fix out of bounds array access warning Bob Peterson (1): gfs2: report "already frozen/thawed" errors Dmitry Osipenko (1): drm/tegra: dc: Don't set PLL clock to 0Hz Florian Fainelli (1): net: phy: broadcom: Only advertise EEE for supported modes Florian Westphal (1): netfilter: x_tables: fix compat match/target pad out-of-bound write Greg Kroah-Hartman (2): staging: m57621-mmc: delete driver from the tree. Linux 4.19.188 Juergen Gross (1): xen/events: fix setting irq affinity Saravana Kannan (1): driver core: Fix locking bug in deferred_probe_timeout_work_func() Suzuki K Poulose (2): KVM: arm64: Hide system instruction access to Trace registers KVM: arm64: Disable guest access to trace filter controls Zihao Yu (1): riscv,entry: fix misaligned base for excp_vect_table Makefile | 2 +- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/kernel/cpufeature.c | 1 - arch/arm64/kvm/debug.c | 2 + arch/riscv/kernel/entry.S | 1 + drivers/base/dd.c | 8 +- drivers/gpu/drm/imx/imx-ldb.c | 10 + drivers/gpu/drm/tegra/dc.c | 10 +- drivers/net/phy/bcm-phy-lib.c | 11 +- drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/mt7621-mmc/Kconfig | 16 - drivers/staging/mt7621-mmc/Makefile | 42 - drivers/staging/mt7621-mmc/TODO | 8 - drivers/staging/mt7621-mmc/board.h | 63 - drivers/staging/mt7621-mmc/dbg.c | 307 --- drivers/staging/mt7621-mmc/dbg.h | 149 -- drivers/staging/mt7621-mmc/mt6575_sd.h | 488 ----- drivers/staging/mt7621-mmc/sd.c | 2392 ------------------------ drivers/xen/events/events_base.c | 4 +- fs/gfs2/super.c | 10 +- net/ipv4/netfilter/arp_tables.c | 2 + net/ipv4/netfilter/ip_tables.c | 2 + net/ipv6/netfilter/ip6_tables.c | 2 + net/netfilter/x_tables.c | 10 +- tools/perf/util/map.c | 7 +- 26 files changed, 52 insertions(+), 3499 deletions(-) delete mode 100644 drivers/staging/mt7621-mmc/Kconfig delete mode 100644 drivers/staging/mt7621-mmc/Makefile delete mode 100644 drivers/staging/mt7621-mmc/TODO delete mode 100644 drivers/staging/mt7621-mmc/board.h delete mode 100644 drivers/staging/mt7621-mmc/dbg.c delete mode 100644 drivers/staging/mt7621-mmc/dbg.h delete mode 100644 drivers/staging/mt7621-mmc/mt6575_sd.h delete mode 100644 drivers/staging/mt7621-mmc/sd.c -- 2.25.1

1 2

[PATCH kernel-4.19 01/36] iommu: Change tlb_range_add to iotlb_range_add and tlb_sync to iotlb_sync
by Yang Yingliang 20 Apr '21

20 Apr '21

From: tom <murphyt7(a)tcd.ie> mainline inclusion from mainline-v5.0-rc1 commit 51eb78098ab79bba8b1df24da2304e61deb74629 category: bugfix bugzilla: 21306 CVE: NA ------------------------------------------------------------------------- Someone forgot to update this comment. Signed-off-by: Tom Murphy <murphyt7(a)tcd.ie> Signed-off-by: Joerg Roedel <jroedel(a)suse.de> Signed-off-by: Zhen Lei <thunder.leizhen(a)huawei.com> Reviewed-by: Hanjun Guo <guohanjun(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- include/linux/iommu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 4907aae83b847..bc8847c878228 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -269,8 +269,8 @@ struct iommu_sva_param { * @map: map a physically contiguous memory region to an iommu domain * @unmap: unmap a physically contiguous memory region from an iommu domain * @flush_tlb_all: Synchronously flush all hardware TLBs for this domain - * @tlb_range_add: Add a given iova range to the flush queue for this domain - * @tlb_sync: Flush all queued ranges from the hardware TLBs and empty flush + * @iotlb_range_add: Add a given iova range to the flush queue for this domain + * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush * queue * @iova_to_phys: translate iova to physical address * @add_device: add device to iommu grouping -- 2.25.1

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[PATCH 42/48] locking/rwsem: Make handoff writer optimistically spin on owner
by Yang Yingliang 20 Apr '21

20 Apr '21

From: Waiman Long <longman(a)redhat.com> When the handoff bit is set by a writer, no other tasks other than the setting writer itself is allowed to acquire the lock. If the to-be-handoff'ed writer goes to sleep, there will be a wakeup latency period where the lock is free, but no one can acquire it. That is less than ideal. To reduce that latency, the handoff writer will now optimistically spin on the owner if it happens to be a on-cpu writer. It will spin until it releases the lock and the to-be-handoff'ed writer can then acquire the lock immediately without any delay. Of course, if the owner is not a on-cpu writer, the to-be-handoff'ed writer will have to sleep anyway. The optimistic spinning code is also modified to not stop spinning when the handoff bit is set. This will prevent an occasional setting of handoff bit from causing a bunch of optimistic spinners from entering into the wait queue causing significant reduction in throughput. On a 1-socket 22-core 44-thread Skylake system, the AIM7 shared_memory workload was run with 7000 users. The throughput (jobs/min) of the following kernels were as follows: 1) 5.2-rc6 - 8,092,486 2) 5.2-rc6 + tip's rwsem patches - 7,567,568 3) 5.2-rc6 + tip's rwsem patches + this patch - 7,954,545 Using perf-record(1), the %cpu time used by rwsem_down_write_slowpath(), rwsem_down_write_failed() and their callees for the 3 kernels were 1.70%, 5.46% and 2.08% respectively. Signed-off-by: Waiman Long <longman(a)redhat.com> Signed-off-by: Peter Zijlstra (Intel) <peterz(a)infradead.org> Cc: x86(a)kernel.org Cc: Ingo Molnar <mingo(a)redhat.com> Cc: Will Deacon <will.deacon(a)arm.com> Cc: huang ying <huang.ying.caritas(a)gmail.com> Cc: Tim Chen <tim.c.chen(a)linux.intel.com> Cc: Linus Torvalds <torvalds(a)linux-foundation.org> Cc: Borislav Petkov <bp(a)alien8.de> Cc: Thomas Gleixner <tglx(a)linutronix.de> Cc: Davidlohr Bueso <dave(a)stgolabs.net> Cc: "H. Peter Anvin" <hpa(a)zytor.com> Link: https://lkml.kernel.org/r/20190625143913.24154-1-longman@redhat.com --- kernel/locking/rwsem.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/kernel/locking/rwsem.c b/kernel/locking/rwsem.c index bd0f0d05724c..354238a08b7a 100644 --- a/kernel/locking/rwsem.c +++ b/kernel/locking/rwsem.c @@ -724,11 +724,12 @@ rwsem_spin_on_owner(struct rw_semaphore *sem, unsigned long nonspinnable) rcu_read_lock(); for (;;) { - if (atomic_long_read(&sem->count) & RWSEM_FLAG_HANDOFF) { - state = OWNER_NONSPINNABLE; - break; - } - + /* + * When a waiting writer set the handoff flag, it may spin + * on the owner as well. Once that writer acquires the lock, + * we can spin on it. So we don't need to quit even when the + * handoff bit is set. + */ new = rwsem_owner_flags(sem, &new_flags); if ((new != owner) || (new_flags != flags)) { state = rwsem_owner_state(new, new_flags, nonspinnable); @@ -974,6 +975,13 @@ static inline bool rwsem_reader_phase_trylock(struct rw_semaphore *sem, { return false; } + +static inline int +rwsem_spin_on_owner(struct rw_semaphore *sem, unsigned long nonspinnable) +{ + return 0; +} +#define OWNER_NULL 1 #endif /* @@ -1206,6 +1214,18 @@ rwsem_down_write_slowpath(struct rw_semaphore *sem, int state) raw_spin_unlock_irq(&sem->wait_lock); + /* + * After setting the handoff bit and failing to acquire + * the lock, attempt to spin on owner to accelerate lock + * transfer. If the previous owner is a on-cpu writer and it + * has just released the lock, OWNER_NULL will be returned. + * In this case, we attempt to acquire the lock again + * without sleeping. + */ + if ((wstate == WRITER_HANDOFF) && + (rwsem_spin_on_owner(sem, 0) == OWNER_NULL)) + goto trylock_again; + /* Block until there are no active lockers. */ for (;;) { if (signal_pending_state(state, current)) @@ -1240,7 +1260,7 @@ rwsem_down_write_slowpath(struct rw_semaphore *sem, int state) break; } } - +trylock_again: raw_spin_lock_irq(&sem->wait_lock); } __set_current_state(TASK_RUNNING); -- 2.29.2.366.gb291b0a628.dirty

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openEuler kernel Meetup 4月9号北京站圆满结束
by Xie XiuQi 17 Apr '21

17 Apr '21

openEuler kernel Meetup 4月9号北京站圆满结束 openEuler kernel SIG组于2021年4月9日在北京成功举办了kernel meetup。本次活动云集了来自华为、麒麟、PingCAP、申威、飞腾、万里红、armChina、兆芯、美团、复旦的行业领袖、业界资深专家、高校教授、社区maintainer、开发者，吸引了现场30人+，线上约300人参与。会上就内核技术、SIG组后续运作规划进行了充分研讨，收集了各厂商的诉求并进行答疑，对SIG组后续的工作开展和技术合作有着重大意义。来自麒麟软件的孙立明老师，对ARM64 KVM 虚拟化架构做了介绍，增进了大家对ARM64 架构虚拟化的理解。麒麟软件的郭皓老师提出了openEuler kernel 支持PREEMPT_RT 的想法和思路。期待openEuler 具备更高的实时性，促进其在嵌入式领域的应用。孙立明老师郭皓老师来自兆芯的张伟老师，对兆芯CPU的演进、特性，以及兆芯补丁合入openEuler kernel 的过程做了介绍。目前兆芯的补丁已经合入openEuler 4.19 内核，预计6 月底发布的 openEuler 20.03 LTS SP2 将支持兆芯CPU。兆芯与openEuler社区的紧密合作促成了 openEuler 对兆芯CPU的快速支持，张伟老师对此表示了称赞。张伟老师来自申威的崔巍老师就处理器接口、虚拟化支持、安全增强等话题与飞腾、兆芯专家进行了现场交流，并表达了积极参与openEuler 的愿望，期待openEuler 尽快支持申威全自主指令集架构，促进openEuler社区和申威生态的共同繁荣。崔巍老师来自华为的缪勰介绍了华为针对SCM介质研发的文件系统。该文件系统的原理基于华为OS内核实验室主任陈海波老师的论文Soft Updates Made Simple and Fast on Non-volatile Memory <https://www.usenix.org/system/files/conference/atc17/atc17-dong.pdf> 采用软更新（soft-update) 提供一致性保证，采用哈希表目录结构，消除循环依赖，提供的字节级读写能力显著降低了SoupFS的复杂性等技术。性能相比业界其他SCM 文件系统有显著的提升。来自华为的杨基鸿，介绍了性能调优的常用方法、工具和思路，并通过实际案例讲解工具的应用及性能分析的思路。线上与会同学表达了对TOP-down性能分析工具的强烈兴趣，我们后续会通过专题分享介绍更多技术细节。杨基鸿来自复旦大学计算机学院的张亮教授，针对如何推动高校参与openEuler提出了建设性意见，我们后续也会持续开展面向高校的交流合作活动。张亮教授 openEuler kernel SIG 的Maintainer 谢秀奇介绍了kernel SIG一年多以来的进展以及后续的运作、规划等。与会专家老师进行了充分的研讨，提出了在kernel SIG 建立committer 机制的想法，以Committer 为核心对openEuler 内核进行规划、开发和治理。谢秀奇本次meetup的成功举办，对kernel SIG的后续工作和发展有重大意义。期待各厂商、各单位、各开发者在openEuler 开源社区这个大平台下，共建、共享、共治，让 openEuler kernel走进千行百业，成为信息产业的基石。 openEuler kernel SIG openEuler kernel 源代码仓库： https://gitee.com/openeuler/kernel 欢迎大家多多star、fork，多多参与社区开发，多多贡献补丁。关于贡献补丁请参考：如何参与 openEuler 内核开发 <https://mp.weixin.qq.com/s/a42a5VfayFeJgWitqbI8Qw> openEuler kernel SIG 微信技术交流群请扫描下方二维码添加小助手微信，备注“交流群”或“技术交流”，加入 openEuler kernel SIG 技术交流群。

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【Meeting Notice】openEuler kernel 技术分享第三期 & 双周例会 Time: 2021-04-16 14:00-18:00
by Meeting Book 16 Apr '21

16 Apr '21

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[PATCH openEuler-1.0-LTS] config/arm64: fix kabi by disable CONFIG_NVME_MULTIPATH
by Cheng Jian 15 Apr '21

15 Apr '21

hulk inclusion category: bugfix bugzilla: https://bugzilla.openeuler.org/show_bug.cgi?id=20 CVE: NA ------------------------------------------------- The config CONFIG_NVME_MULTIPATH causes Kabi broken, so turn this feature off. This reverts commit 3aa30a87da112ec78cbd2a3cc543bbafc72be76c. Signed-off-by: Cheng Jian <cj.chengjian(a)huawei.com> --- arch/arm64/configs/openeuler_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index fc7065339051..89dec8e1954f 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -1960,7 +1960,7 @@ CONFIG_BLK_DEV_RBD=m # CONFIG_NVME_CORE=m CONFIG_BLK_DEV_NVME=m -CONFIG_NVME_MULTIPATH=y +# CONFIG_NVME_MULTIPATH is not set CONFIG_NVME_FABRICS=m CONFIG_NVME_RDMA=m CONFIG_NVME_FC=m -- 2.25.1

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[PATCH openEuler-1.0-LTS 0/5] errata and bugfix for openEuler 20.03
by Cheng Jian 15 Apr '21

15 Apr '21

errata and bugfix for openEuler 20.03 *** BLURB HERE *** Cheng Jian (1): config/x86: enable SHRINK_PAGECACHE Kai Shen (1): arm64: errata: add option to disable cache readunique prefetch on 1620 Xie XiuQi (2): arm64: errata: fix kabi changed for cpu_errata arm64: errata: enable HISILICON_ERRATUM_HIP08_RU_PREFETCH Zheng Zengkai (1): arm64: Add config switch and kernel parameter for CPU0 hotplug .../admin-guide/kernel-parameters.txt | 8 +++ arch/arm64/Kconfig | 46 +++++++++++++ arch/arm64/configs/openeuler_defconfig | 2 + arch/arm64/kernel/cpu_errata.c | 67 +++++++++++++++++++ arch/arm64/kernel/setup.c | 18 ++++- arch/x86/configs/hulk_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 2 +- 7 files changed, 142 insertions(+), 2 deletions(-) -- 2.25.1

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[PATCH openEuler-1.0-LTS 00/12] iommu/arm-smmu-v3: Reduce
by Cheng Jian 15 Apr '21

15 Apr '21

v2 --> v3: 1. Discard the patches(support gather) that affects the kabi. These patches are not critical to performance optimization. ---> openeuler_defconfig, 11 SSD non-strict 1313.4 (discard gather patches) 1314.7 1326.6 (all, contain gather patches) 1363.6 strict (after: all) 1357.3 1355.8 1311.1 strict (after: discard) 1248.7 1188.7 1218.5 strict (before) 716.7 728.9 721.6 v1 --> v2: 1. Fix compile error: drivers/uacce/dummy_drv/dummy_wd_v2.c:202:11: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types] .unmap = dummy_wd2_iommu_unmap, 2. Add a new fix: 862c3715de8f ("iommu: Switch gather->end to the inclusive end") 3. Leave member iotlb_range_add in "struct iommu_ops" as a placeholder v1: For more information, please refer: http://openeuler.huawei.com/bugzilla/show_bug.cgi?id=21306 Rob Herring (1): iommu: Allow io-pgtable to be used outside of drivers/iommu/ Tom Murphy (1): iommu: Fix flush_tlb_all typo Will Deacon (9): iommu/io-pgtable: Replace IO_PGTABLE_QUIRK_NO_DMA with specific flag iommu/arm-smmu-v3: Increase maximum size of queues iommu/io-pgtable-arm: Remove redundant call to io_pgtable_tlb_sync() iommu/io-pgtable: Rename iommu_gather_ops to iommu_flush_ops iommu/arm-smmu-v3: Separate s/w and h/w views of prod and cons indexes iommu/arm-smmu-v3: Drop unused 'q' argument from Q_OVF macro iommu/arm-smmu-v3: Move low-level queue fields out of arm_smmu_queue iommu/arm-smmu-v3: Operate directly on low-level queue where possible iommu/arm-smmu-v3: Reduce contention during command-queue insertion tom (1): iommu: Change tlb_range_add to iotlb_range_add and tlb_sync to iotlb_sync drivers/iommu/arm-smmu-v3.c | 853 +++++++++++++----- drivers/iommu/arm-smmu.c | 14 +- drivers/iommu/io-pgtable-arm-v7s.c | 16 +- drivers/iommu/io-pgtable-arm.c | 24 +- drivers/iommu/io-pgtable.c | 5 +- drivers/iommu/iommu-pasid-table.h | 2 +- drivers/iommu/ipmmu-vmsa.c | 8 +- drivers/iommu/msm_iommu.c | 6 +- drivers/iommu/mtk_iommu.c | 4 +- drivers/iommu/mtk_iommu.h | 3 +- drivers/iommu/qcom_iommu.c | 6 +- {drivers/iommu => include/linux}/io-pgtable.h | 17 +- include/linux/iommu.h | 6 +- 13 files changed, 685 insertions(+), 279 deletions(-) rename {drivers/iommu => include/linux}/io-pgtable.h (93%) -- 2.25.1

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