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[PATCH OLK-6.6] drivers/perf: hisi: Add cacheable option for L3C PMU
by Yushan Wang 16 Jun '25

16 Jun '25

From: Yicong Yang <yangyicong(a)hisilicon.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICFKE2 ---------------------------------------------------------------------- L3C PMU v3 implement additional control for tracetag which may influence the filter of certain events. Add below options: - cacheable: whether to filter the cacheable or noncacheable operation Fixes: 89711c8962cc ("drivers/perf: hisi: Add support for L3C PMU v3") Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> Signed-off-by: Yushan Wang <wangyushan12(a)huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c index 6950ccfa0a33..00ed571a3030 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -46,6 +46,7 @@ #define L3C_TRACETAG_MARK_EN BIT(0) #define L3C_TRACETAG_REQ_EN (L3C_TRACETAG_MARK_EN | BIT(2)) #define L3C_TRACETAG_CORE_EN (L3C_TRACETAG_MARK_EN | BIT(3)) +#define L3C_TRACETAG_CACHEABLE_EN BIT(12) #define L3C_CORE_EN BIT(20) #define L3C_COER_NONE 0x0 #define L3C_DATSRC_MASK 0xFF @@ -59,6 +60,7 @@ HISI_PMU_EVENT_ATTR_EXTRACTOR(ext, config, 16, 16); HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_req, config1, 10, 8); HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_cfg, config1, 15, 11); HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 16, 16); +HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_cacheable, config1, 17, 17); HISI_PMU_EVENT_ATTR_EXTRACTOR(tt_core, config2, 15, 0); struct hisi_l3c_pmu { @@ -157,6 +159,10 @@ static void hisi_l3c_pmu_config_req_tracetag(struct perf_event *event) val = hisi_l3c_pmu_event_readl(hwc, L3C_TRACETAG_CTRL); val |= tt_req << L3C_TRACETAG_REQ_SHIFT; val |= L3C_TRACETAG_REQ_EN; + + if (hisi_get_tt_cacheable(event)) + val |= L3C_TRACETAG_CACHEABLE_EN; + hisi_l3c_pmu_event_writel(hwc, L3C_TRACETAG_CTRL, val); /* Enable request-tracetag statistics */ @@ -178,6 +184,10 @@ static void hisi_l3c_pmu_clear_req_tracetag(struct perf_event *event) val = hisi_l3c_pmu_event_readl(hwc, L3C_TRACETAG_CTRL); val &= ~(tt_req << L3C_TRACETAG_REQ_SHIFT); val &= ~L3C_TRACETAG_REQ_EN; + + if (hisi_get_tt_cacheable(event)) + val &= ~L3C_TRACETAG_CACHEABLE_EN; + hisi_l3c_pmu_event_writel(hwc, L3C_TRACETAG_CTRL, val); /* Disable request-tracetag statistics */ @@ -564,6 +574,7 @@ static struct attribute *hisi_l3c_pmu_v3_format_attr[] = { HISI_PMU_FORMAT_ATTR(event, "config:0-7"), HISI_PMU_FORMAT_ATTR(ext, "config:16"), HISI_PMU_FORMAT_ATTR(tt_req, "config1:8-10"), + HISI_PMU_FORMAT_ATTR(tt_cacheable, "config1:17"), HISI_PMU_FORMAT_ATTR(tt_core, "config2:0-15"), NULL }; -- 2.33.0

2 1

[PATCH OLK-6.6] perf: Remove unstable events for uncore L3C PMU
by Yushan Wang 16 Jun '25

16 Jun '25

driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICFG4K ---------------------------------------------------------------------- Currently when taking event 0x80, 0x83, the value of PMU counters will be unstable if the value overflows and cause IRQs. Remove these events in sysfs then. Fixes: 89711c8962cc ("drivers/perf: hisi: Add support for L3C PMU v3") Signed-off-by: Yushan Wang <wangyushan12(a)huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c index f4afd8c7bf37..6950ccfa0a33 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -651,8 +651,6 @@ HISI_L3C_PMU_EVENT_ATTR(io_rd_hit_spipe, 0x1d, false); HISI_L3C_PMU_EVENT_ATTR(io_wr_spipe, 0x1e, false); HISI_L3C_PMU_EVENT_ATTR(io_wr_hit_spipe, 0x1f, false); HISI_L3C_PMU_EVENT_ATTR(cycles, 0x7f, false); -HISI_L3C_PMU_EVENT_ATTR(l3t_comp_sum, 0x80, false); -HISI_L3C_PMU_EVENT_ATTR(l3t_rdnotram, 0x83, true); HISI_L3C_PMU_EVENT_ATTR(l3c_ref, 0xbc, false); HISI_L3C_PMU_EVENT_ATTR(l3c2ring, 0xbd, true); @@ -675,8 +673,6 @@ static struct attribute *hisi_l3c_pmu_v3_events_attr[] = { &hisi_l3c_io_wr_spipe_attr.attr.attr, &hisi_l3c_io_wr_hit_spipe_attr.attr.attr, &hisi_l3c_cycles_attr.attr.attr, - &hisi_l3c_l3t_comp_sum_attr.attr.attr, - &hisi_l3c_l3t_rdnotram_attr.attr.attr, &hisi_l3c_l3c_ref_attr.attr.attr, &hisi_l3c_l3c2ring_attr.attr.attr, NULL -- 2.33.0

2 1

[PATCH OLK-6.6] arm64: perf: Add support for HIP12 hw metric
by Yushan Wang 16 Jun '25

16 Jun '25

From: Yicong Yang <yangyicong(a)hisilicon.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICFKG8 ---------------------------------------------------------------------- HIP12 provides hardware metric sampling with adjacent counters counter_2n and counter_2n+1. Overflow of counter_2n+1 will result in an interrupt while overflow of counter_2n will load initial value, which are stored in dedicated registers reload_counter_2n and reload_counter_2n+1, to both counters. With the ability above, software could only perform sampling during handling interrupt of counter_2n and configure different values of reload_counter_2n and reload_counter_2n+1, which realizes hardware metric sampling. For example, perf record -e '\ {armv8_pmuv3_0/cpu_cycles,period=1000000,hw_metric=1/, \ armv8_pmuv3_0/inst_retired,period=800000,hw_metric=1/}:u' \ -- <workload> Above command will only perform sampling when IPC < 800000 / 1000000, since the interrupt will only appear when cpu_cycles reaches 1000000 and inst_retired is less than 800000. Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> Signed-off-by: Yushan Wang <wangyushan(a)hisilicon.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- drivers/perf/arm_pmu.c | 6 ++ drivers/perf/arm_pmuv3.c | 177 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 181 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 57cd2d1a9a18..5621bbc828af 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -422,6 +422,12 @@ validate_group(struct perf_event *event) */ memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask)); + /* + * Make percpu_pmu null so that PMU might get a chance to know if + * get_event_idx is called for validation. + */ + fake_pmu.percpu_pmu = NULL; + if (!validate_event(event->pmu, &fake_pmu, leader)) return -EINVAL; diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index baa700ab5e03..d3ea5f2fdfda 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -319,6 +319,9 @@ static const struct attribute_group armv8_pmuv3_events_attr_group = { #define ATTR_CFG_FLD_threshold_CFG config1 /* PMEVTYPER.TH */ #define ATTR_CFG_FLD_threshold_LO 5 #define ATTR_CFG_FLD_threshold_HI 16 +#define ATTR_CFG_FLD_hw_metric_CFG config2 +#define ATTR_CFG_FLD_hw_metric_LO 0 +#define ATTR_CFG_FLD_hw_metric_HI 0 GEN_PMU_FORMAT_ATTR(event); GEN_PMU_FORMAT_ATTR(long); @@ -326,6 +329,7 @@ GEN_PMU_FORMAT_ATTR(rdpmc); GEN_PMU_FORMAT_ATTR(threshold_count); GEN_PMU_FORMAT_ATTR(threshold_compare); GEN_PMU_FORMAT_ATTR(threshold); +GEN_PMU_FORMAT_ATTR(hw_metric); static int sysctl_perf_user_access __read_mostly; @@ -358,6 +362,27 @@ static u8 armv8pmu_event_threshold_control(struct perf_event_attr *attr) return (th_compare << 1) | th_count; } +static inline bool armv8pmu_event_is_hw_metric(struct perf_event *event) +{ + return ATTR_CFG_GET_FLD(&event->attr, hw_metric); +} + +static bool armpmu_support_hisi_hw_metric(void) +{ + static const struct midr_range hip12_cpus[] = { + MIDR_ALL_VERSIONS(MIDR_HISI_HIP12), + { } + }; + + /* + * Feature of hw metric requires access to EL1 registers to accomplish, + * which will cause kernel panic in virtual machine because of lack of + * authority. Thus, this feature is banned for virtual machines. + */ + return is_midr_in_range_list(hip12_cpus) && + is_kernel_in_hyp_mode(); +} + static struct attribute *armv8_pmuv3_format_attrs[] = { &format_attr_event.attr, &format_attr_long.attr, @@ -365,11 +390,23 @@ static struct attribute *armv8_pmuv3_format_attrs[] = { &format_attr_threshold.attr, &format_attr_threshold_compare.attr, &format_attr_threshold_count.attr, + &format_attr_hw_metric.attr, NULL, }; +static umode_t +armv8pmu_format_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int unused) +{ + if (attr == &format_attr_hw_metric.attr && !armpmu_support_hisi_hw_metric()) + return 0; + + return attr->mode; +} + static const struct attribute_group armv8_pmuv3_format_attr_group = { .name = "format", + .is_visible = armv8pmu_format_attr_is_visible, .attrs = armv8_pmuv3_format_attrs, }; @@ -603,6 +640,39 @@ static void armv8pmu_write_evcntr(int idx, u64 value) write_pmevcntrn(counter, value); } +static inline void armv8pmu_write_reload_counter(struct perf_event *event, + u64 value) +{ + /* Need to be event->hw.idx - 1 since counter 0 is PMCCNTR_EL0 */ + int idx = event->hw.idx - 1; + +#define HW_METRIC_RELOAD_CNTR(n) sys_reg(3, 3, 15, 3, (2 + n)) +#define write_hw_metric_reload_cntr(_value, _n) \ + do { \ + switch (_n) { \ + case 0: \ + write_sysreg_s(_value, HW_METRIC_RELOAD_CNTR(0)); break; \ + case 1: \ + write_sysreg_s(_value, HW_METRIC_RELOAD_CNTR(1)); break; \ + case 2: \ + write_sysreg_s(_value, HW_METRIC_RELOAD_CNTR(2)); break; \ + case 3: \ + write_sysreg_s(_value, HW_METRIC_RELOAD_CNTR(3)); break; \ + case 4: \ + write_sysreg_s(_value, HW_METRIC_RELOAD_CNTR(4)); break; \ + case 5: \ + write_sysreg_s(_value, HW_METRIC_RELOAD_CNTR(5)); break; \ + default: \ + WARN(1, "Invalid hw_metric reload counter index\n"); \ + dev_err(event->pmu->dev, "event is 0x%lx index is %x\n",\ + event->hw.config_base, event->hw.idx); \ + } \ + } while (0) + write_hw_metric_reload_cntr(value, idx); +#undef write_hw_metric_reload_cntr +#undef HW_METRIC_RELOAD_CNTR +} + static void armv8pmu_write_hw_counter(struct perf_event *event, u64 value) { @@ -614,6 +684,9 @@ static void armv8pmu_write_hw_counter(struct perf_event *event, } else { armv8pmu_write_evcntr(idx, value); } + + if (armv8pmu_event_is_hw_metric(event)) + armv8pmu_write_reload_counter(event, value); } static void armv8pmu_write_counter(struct perf_event *event, u64 value) @@ -688,6 +761,36 @@ static void armv8pmu_enable_counter(u32 mask) write_pmcntenset(mask); } +#define HISI_DTU_CTLR_EL1 sys_reg(3, 0, 15, 8, 4) +#define HISI_DTU_CTLR_EL1_CHK_GROUP0 BIT(15) + +static inline void armv8pmu_enable_hw_metric(struct perf_event *event, bool enable) +{ + int idx = event->hw.idx; + u64 reg; + + /* + * Configure the chicken bit on leader event enabling. + */ + if (event != event->group_leader) + return; + + /* Convert the idx since we only use general counters, counter 0 is + * used for PMCCNTR_EL0. + */ + idx -= 1; + + reg = read_sysreg_s(HISI_DTU_CTLR_EL1); + if (enable) + reg |= HISI_DTU_CTLR_EL1_CHK_GROUP0 << (idx >> 1); + else + reg &= ~(HISI_DTU_CTLR_EL1_CHK_GROUP0 << (idx >> 1)); + + write_sysreg_s(reg, HISI_DTU_CTLR_EL1); + + reg = read_sysreg_s(HISI_DTU_CTLR_EL1); +} + static void armv8pmu_enable_event_counter(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; @@ -696,8 +799,12 @@ static void armv8pmu_enable_event_counter(struct perf_event *event) kvm_set_pmu_events(mask, attr); /* We rely on the hypervisor switch code to enable guest counters */ - if (!kvm_pmu_counter_deferred(attr)) + if (!kvm_pmu_counter_deferred(attr)) { armv8pmu_enable_counter(mask); + + if (armv8pmu_event_is_hw_metric(event)) + armv8pmu_enable_hw_metric(event, true); + } } static void armv8pmu_disable_counter(u32 mask) @@ -718,8 +825,12 @@ static void armv8pmu_disable_event_counter(struct perf_event *event) kvm_clr_pmu_events(mask); /* We rely on the hypervisor switch code to disable guest counters */ - if (!kvm_pmu_counter_deferred(attr)) + if (!kvm_pmu_counter_deferred(attr)) { armv8pmu_disable_counter(mask); + + if (armv8pmu_event_is_hw_metric(event)) + armv8pmu_enable_hw_metric(event, false); + } } static void armv8pmu_enable_intens(u32 mask) @@ -1005,6 +1116,59 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, return -EAGAIN; } +static int armv8pmu_check_hw_metric_event(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + struct perf_event *sibling, *leader = event->group_leader; + int hw_metric_cnt = 0; + + if (cpuc->percpu_pmu) { + for_each_sibling_event(sibling, leader) { + if (armv8pmu_event_is_hw_metric(sibling)) + hw_metric_cnt++; + } + + if (hw_metric_cnt != 1) + return -EINVAL; + } else { + if (event == leader) + return 0; + + if (!armv8pmu_event_is_hw_metric(leader)) + return -EINVAL; + + for_each_sibling_event(sibling, leader) { + if (armv8pmu_event_is_hw_metric(sibling)) + hw_metric_cnt++; + } + + if (hw_metric_cnt > 0) + return -EINVAL; + } + + return 0; +} + +static int armv8pmu_get_hw_metric_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); + struct perf_event *leader = event->group_leader; + int leader_idx; + + if (armv8pmu_check_hw_metric_event(cpuc, event)) + return -EINVAL; + + if (event == leader || leader->hw.idx < 1) + return armv8pmu_get_chain_idx(cpuc, cpu_pmu); + + leader_idx = leader->hw.idx; + if (cpuc->events[leader_idx - 1]) + return -EAGAIN; + + return leader_idx - 1; +} + static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1012,6 +1176,12 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, struct hw_perf_event *hwc = &event->hw; unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; + if (armv8pmu_event_is_hw_metric(event)) + return armv8pmu_get_hw_metric_event_idx(cpuc, event); + else if (event != event->group_leader && + armv8pmu_event_is_hw_metric(event->group_leader)) + return -EINVAL; + /* Always prefer to place a cycle counter into the cycle counter. */ if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && !armv8pmu_event_get_threshold(&event->attr)) { @@ -1235,6 +1405,9 @@ static int __armv8_pmuv3_map_event(struct perf_event *event, if (armv8pmu_event_is_64bit(event)) event->hw.flags |= ARMPMU_EVT_64BIT; + if (armv8pmu_event_is_hw_metric(event) && !armpmu_support_hisi_hw_metric()) + return -EOPNOTSUPP; + /* * User events must be allocated into a single counter, and so * must not be chained. -- 2.33.0

2 1

[PATCH OLK-6.6 1/2] drivers/perf: hisi: Clarifying event names and fix event ID for pa_pmu
by Yushan Wang 16 Jun '25

16 Jun '25

From: Junhao He <hejunhao3(a)huawei.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICFG22 ---------------------------------------------------------------------- The rx_req and tx_req events were only counting the number of flit package requests for link0. Hisilicon PA supports 4 links (0-3), and the original event names could be misinterpreted as counting the total flit packages across all links. Additionally, the tx_req event ID was incorrect. Fixes this by: 1) Adding the "link0" suffix and "pa" prefix to the event names to clearly indicate that they are specific to link0 and belong to the PA PMU. 2) Updating the tx_req event ID to 0x60 to reflect the correct identifier. These changes ensure accurate event naming and counting for link0 and flit packages. Fixes: a0ab25cd82ee ("drivers/perf: hisi: Add support for HiSilicon PA PMU driver") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> Signed-off-by: Yushan Wang <wangyushan12(a)huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c index bf79ef288564..e09822d67920 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c @@ -316,8 +316,8 @@ static const struct attribute_group hisi_pa_pmu_v2_format_group = { }; static struct attribute *hisi_pa_pmu_v2_events_attr[] = { - HISI_PMU_EVENT_ATTR(rx_req, 0x40), - HISI_PMU_EVENT_ATTR(tx_req, 0x5c), + HISI_PMU_EVENT_ATTR(pa_rx_req_link0, 0x40), + HISI_PMU_EVENT_ATTR(pa_tx_req_link0, 0x60), HISI_PMU_EVENT_ATTR(cycle, 0x78), NULL }; -- 2.33.0

2 2

[PATCH OLK-6.6] drivers/perf: hisi: Fixes the incorrect bitmask limit for the CPA event sysfs interface
by Yushan Wang 16 Jun '25

16 Jun '25

From: Junhao He <hejunhao3(a)huawei.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICFG6F ---------------------------------------------------------------------- However, when users input events in the range of 0x1ff to 0xffff, the driver does not return an error. Therefore, the bitmask limit should be adjusted to bitmask(0-7) to ensure proper functionality. before the patch: [root@localhost ~]# perf stat -e hisi_sicl0_cpa0/event=0x1FF/ sleep 1 Performance counter stats for 'system wide': <not supported> hisi_sicl0_cpa0/event=0x1FF/ after the patch: [root@localhost ~]# perf stat -e hisi_sicl0_cpa0/event=0x1FF/ sleep 1 event syntax error: '..cpa0/event=0x1FF/' \___ value too big for format, maximum is 255 Fixes: 6b79738b6ed91 ("drivers/perf: hisi: Add Support for CPA PMU") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> Signed-off-by: Yushan Wang <wangyushan12(a)huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c b/drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c index 006afb4d1208..cfc3ed2a79af 100644 --- a/drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c @@ -202,7 +202,7 @@ static int hisi_cpa_pmu_init_data(struct platform_device *pdev, } static struct attribute *hisi_cpa_pmu_format_attr[] = { - HISI_PMU_FORMAT_ATTR(event, "config:0-15"), + HISI_PMU_FORMAT_ATTR(event, "config:0-7"), NULL }; -- 2.33.0

2 1

[PATCH OLK-6.6] drivers/perf: hisi: Add events and rename event "cycle" for pa_pmu
by Yushan Wang 16 Jun '25

16 Jun '25

From: Junhao He <hejunhao3(a)huawei.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IC0GTV ---------------------------------------------------------------------- 1) Add events to count the number of request flit packages for links 1-3 and data flit packages for all links (0-3). 2) rename event "cycle" to pa_cycles to clearly indicate that it belongs to the PA PMU Fixes: a0ab25cd82ee ("drivers/perf: hisi: Add support for HiSilicon PA PMU driver") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> Signed-off-by: Yushan Wang <wangyushan12(a)huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c index e09822d67920..294746e11e39 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c @@ -317,8 +317,22 @@ static const struct attribute_group hisi_pa_pmu_v2_format_group = { static struct attribute *hisi_pa_pmu_v2_events_attr[] = { HISI_PMU_EVENT_ATTR(pa_rx_req_link0, 0x40), + HISI_PMU_EVENT_ATTR(pa_rx_req_link1, 0x41), + HISI_PMU_EVENT_ATTR(pa_rx_req_link2, 0x42), + HISI_PMU_EVENT_ATTR(pa_rx_req_link3, 0x43), + HISI_PMU_EVENT_ATTR(pa_rx_data_link0, 0x44), + HISI_PMU_EVENT_ATTR(pa_rx_data_link1, 0x45), + HISI_PMU_EVENT_ATTR(pa_rx_data_link2, 0x46), + HISI_PMU_EVENT_ATTR(pa_rx_data_link3, 0x47), HISI_PMU_EVENT_ATTR(pa_tx_req_link0, 0x60), - HISI_PMU_EVENT_ATTR(cycle, 0x78), + HISI_PMU_EVENT_ATTR(pa_tx_req_link1, 0x61), + HISI_PMU_EVENT_ATTR(pa_tx_req_link2, 0x62), + HISI_PMU_EVENT_ATTR(pa_tx_req_link3, 0x63), + HISI_PMU_EVENT_ATTR(pa_tx_data_link0, 0x64), + HISI_PMU_EVENT_ATTR(pa_tx_data_link1, 0x65), + HISI_PMU_EVENT_ATTR(pa_tx_data_link2, 0x66), + HISI_PMU_EVENT_ATTR(pa_tx_data_link3, 0x67), + HISI_PMU_EVENT_ATTR(pa_cycles, 0x78), NULL }; -- 2.33.0

2 1

[PATCH OLK-6.6] drivers/perf: hisi: Clarifying event names and fix event ID for pa_pmu
by Yushan Wang 16 Jun '25

16 Jun '25

From: Junhao He <hejunhao3(a)huawei.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICFG22 ---------------------------------------------------------------------- The rx_req and tx_req events were only counting the number of flit package requests for link0. Hisilicon PA supports 4 links (0-3), and the original event names could be misinterpreted as counting the total flit packages across all links. Additionally, the tx_req event ID was incorrect. Fixes this by: 1) Adding the "link0" suffix and "pa" prefix to the event names to clearly indicate that they are specific to link0 and belong to the PA PMU. 2) Updating the tx_req event ID to 0x60 to reflect the correct identifier. These changes ensure accurate event naming and counting for link0 and flit packages. Fixes: a0ab25cd82ee ("drivers/perf: hisi: Add support for HiSilicon PA PMU driver") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> Signed-off-by: Yushan Wang <wangyushan12(a)huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c index bf79ef288564..e09822d67920 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c @@ -316,8 +316,8 @@ static const struct attribute_group hisi_pa_pmu_v2_format_group = { }; static struct attribute *hisi_pa_pmu_v2_events_attr[] = { - HISI_PMU_EVENT_ATTR(rx_req, 0x40), - HISI_PMU_EVENT_ATTR(tx_req, 0x5c), + HISI_PMU_EVENT_ATTR(pa_rx_req_link0, 0x40), + HISI_PMU_EVENT_ATTR(pa_tx_req_link0, 0x60), HISI_PMU_EVENT_ATTR(cycle, 0x78), NULL }; -- 2.33.0

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[PATCH OLK-6.6] perf iostat: hisi: Fix port range retrival
by Yushan Wang 16 Jun '25

16 Jun '25

From: Yicong Yang <yangyicong(a)hisilicon.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICFG5B ---------------------------------------------------------------------- Root ports monitored by different the PCIe PMUs may locates on the same root bus. It's not correct to match all the Root Ports on the same bus for one PCIe PMU. Fix this. Fixes: 26b19f9990c0 ("perf stat: Enable iostat mode for HiSilicon PCIe PMU") Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> Signed-off-by: Yushan Wang <wangyushan12(a)huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3(a)h-partners.com> --- tools/perf/arch/arm64/util/hisi-iostat.c | 32 +++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/tools/perf/arch/arm64/util/hisi-iostat.c b/tools/perf/arch/arm64/util/hisi-iostat.c index 96684cc00464..fc794ee7d8d4 100644 --- a/tools/perf/arch/arm64/util/hisi-iostat.c +++ b/tools/perf/arch/arm64/util/hisi-iostat.c @@ -22,6 +22,10 @@ #include "util/iostat.h" #include "util/pmu.h" +/* From include/uapi/linux/pci.h */ +#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) + #define PCI_DEFAULT_DOMAIN 0 #define PCI_DEVICE_NAME_PATTERN "%04x:%02hhx:%02hhx.%hhu" #define PCI_ROOT_BUS_DEVICES_PATH "bus/pci/devices" @@ -69,9 +73,9 @@ struct hisi_pcie_root_port { LIST_HEAD(hisi_pcie_root_ports_list); static int hisi_pcie_root_ports_num; -static void hisi_pcie_init_root_port_mask(struct hisi_pcie_root_port *rp) +static void hisi_pcie_init_root_port_mask(struct hisi_pcie_root_port *rp, u16 devbase) { - rp->mask = BIT(rp->dev << 1); + rp->mask = BIT((rp->dev - devbase) << 1); } /* @@ -100,7 +104,8 @@ static void hisi_pcie_root_ports_select_all(void) rp->selected = true; } -static void hisi_pcie_root_ports_add(u16 sicl_id, u16 core_id, u8 target_bus) +static void hisi_pcie_root_ports_add(u16 sicl_id, u16 core_id, u8 target_bus, + u16 bdf_min, u16 bdf_max) { const char *sysfs = sysfs__mountpoint(); struct hisi_pcie_root_port *rp; @@ -109,6 +114,7 @@ static void hisi_pcie_root_ports_add(u16 sicl_id, u16 core_id, u8 target_bus) u8 bus, dev, fn; u32 domain; DIR *dir; + u16 bdf; int ret; snprintf(path, PATH_MAX, "%s/%s", sysfs, PCI_ROOT_BUS_DEVICES_PATH); @@ -123,6 +129,10 @@ static void hisi_pcie_root_ports_add(u16 sicl_id, u16 core_id, u8 target_bus) if (ret != 4 || bus != target_bus) continue; + bdf = (bus << 8) | PCI_DEVFN(dev, fn); + if (bdf < bdf_min || bdf > bdf_max) + continue; + rp = zalloc(sizeof(*rp)); if (!rp) continue; @@ -135,7 +145,7 @@ static void hisi_pcie_root_ports_add(u16 sicl_id, u16 core_id, u8 target_bus) rp->dev = dev; rp->fn = fn; - hisi_pcie_init_root_port_mask(rp); + hisi_pcie_init_root_port_mask(rp, PCI_SLOT(bdf_min)); list_add(&rp->list, &hisi_pcie_root_ports_list); hisi_pcie_root_ports_num++; @@ -150,7 +160,7 @@ static void hisi_pcie_root_ports_add(u16 sicl_id, u16 core_id, u8 target_bus) static int hisi_pcie_root_ports_init(void) { char event_source[PATH_MAX], bus_path[PATH_MAX]; - unsigned long long bus; + unsigned long long bus, bdf_max, bdf_min; u16 sicl_id, core_id; struct dirent *dent; DIR *dir; @@ -182,9 +192,19 @@ static int hisi_pcie_root_ports_init(void) if (filename__read_ull(bus_path, &bus)) continue; + scnprintf(bus_path, sizeof(bus_path), "%s/hisi_pcie%hu_core%hu/bdf_max", + event_source, sicl_id, core_id); + if (filename__read_xll(bus_path, &bdf_max)) + bdf_max = -1; + + scnprintf(bus_path, sizeof(bus_path), "%s/hisi_pcie%hu_core%hu/bdf_min", + event_source, sicl_id, core_id); + if (filename__read_xll(bus_path, &bdf_min)) + bdf_min = 0; + pr_debug3("Found pmu %s bus 0x%llx\n", dent->d_name, bus); - hisi_pcie_root_ports_add(sicl_id, core_id, (u8)bus); + hisi_pcie_root_ports_add(sicl_id, core_id, (u8)bus, (u16)bdf_min, (u16)bdf_max); } closedir(dir); -- 2.33.0

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[openeuler:OLK-5.10 2968/2968] ld.lld: error: version script assignment of 'LINUX_2.6' to symbol '__vdso_sgx_enter_enclave' failed: symbol not defined
by kernel test robot 16 Jun '25

16 Jun '25

Hi Sean, FYI, the error/warning still remains. tree: https://gitee.com/openeuler/kernel.git OLK-5.10 head: 49ad0aeea0747f589e03fb0959d5582f166c8fdf commit: 5476cb89ef2297bd36f8b38e27b54617b6f63236 [2968/2968] x86/vdso: Implement a vDSO for Intel SGX enclave call config: x86_64-allnoconfig (https://download.01.org/0day-ci/archive/20250616/202506161236.gXbjokCw-lkp@…) compiler: clang version 20.1.2 (https://github.com/llvm/llvm-project 58df0ef89dd64126512e4ee27b4ac3fd8ddf6247) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250616/202506161236.gXbjokCw-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202506161236.gXbjokCw-lkp@intel.com/ All errors (new ones prefixed by >>): >> ld.lld: error: version script assignment of 'LINUX_2.6' to symbol '__vdso_sgx_enter_enclave' failed: symbol not defined llvm-objdump: error: 'arch/x86/entry/vdso/vdso64.so.dbg': No such file or directory -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

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[openeuler:OLK-6.6 2392/2392] drivers/net/ethernet/linkdata/sxe/sxepf/sxe_main.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
by kernel test robot 16 Jun '25

16 Jun '25

tree: https://gitee.com/openeuler/kernel.git OLK-6.6 head: 93509d36bc89182689dc1bc16b348878b867f166 commit: a29c130b6607ab7a2d7e6df8625494cdafc6d736 [2392/2392] Linkdata：net：fix sxe compile errors 'sxe_resume' defined but not used config: arm64-randconfig-004-20250616 (https://download.01.org/0day-ci/archive/20250616/202506161212.8FdTH8ys-lkp@…) compiler: aarch64-linux-gcc (GCC) 7.5.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250616/202506161212.8FdTH8ys-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202506161212.8FdTH8ys-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/net/ethernet/linkdata/sxe/sxepf/sxe_main.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Copyright (C), 2020, Linkdata Technologies Co., Ltd. Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for PTP_1588_CLOCK Depends on [n]: NET [=y] && POSIX_TIMERS [=n] Selected by [m]: - SXE [=m] && NETDEVICES [=y] && ETHERNET [=y] && NET_VENDOR_LINKDATA [=y] && (X86 || ARM64 [=y]) && PCI [=y] - SXE_VF [=m] && NETDEVICES [=y] && ETHERNET [=y] && NET_VENDOR_LINKDATA [=y] && (X86 || ARM64 [=y]) && PCI [=y] WARNING: unmet direct dependencies detected for HALTPOLL_CPUIDLE Depends on [n]: CPU_IDLE [=n] && ARCH_CPUIDLE_HALTPOLL [=y] && ARCH_HAS_OPTIMIZED_POLL [=y] Selected by [y]: - ARM64 [=y] vim +3 drivers/net/ethernet/linkdata/sxe/sxepf/sxe_main.c dd013ad487534c liujie_answer 2025-04-15 @3 * Copyright (C), 2020, Linkdata Technologies Co., Ltd. dd013ad487534c liujie_answer 2025-04-15 4 * dd013ad487534c liujie_answer 2025-04-15 5 * @file: sxe_main.c dd013ad487534c liujie_answer 2025-04-15 6 * @author: Linkdata dd013ad487534c liujie_answer 2025-04-15 7 * @date: 2025.02.16 dd013ad487534c liujie_answer 2025-04-15 8 * @brief: dd013ad487534c liujie_answer 2025-04-15 9 * @note: dd013ad487534c liujie_answer 2025-04-15 10 */ dd013ad487534c liujie_answer 2025-04-15 11 #include <linux/kernel.h> dd013ad487534c liujie_answer 2025-04-15 12 #include <linux/pci.h> dd013ad487534c liujie_answer 2025-04-15 13 #include <linux/moduleparam.h> dd013ad487534c liujie_answer 2025-04-15 14 #include <linux/module.h> dd013ad487534c liujie_answer 2025-04-15 15 #include <linux/netdevice.h> dd013ad487534c liujie_answer 2025-04-15 16 #include <linux/etherdevice.h> dd013ad487534c liujie_answer 2025-04-15 17 #include <net/rtnetlink.h> dd013ad487534c liujie_answer 2025-04-15 18 #include <linux/moduleparam.h> dd013ad487534c liujie_answer 2025-04-15 19 #include <linux/aer.h> dd013ad487534c liujie_answer 2025-04-15 20 :::::: The code at line 3 was first introduced by commit :::::: dd013ad487534c1838afc2f55efdb5daec15aace Ethernet: Linkdata: Supports Linkdata ethernet Controllers :::::: TO: liujie_answer <liujie5(a)linkdatatechnology.com> :::::: CC: liujie_answer <liujie5(a)linkdatatechnology.com> -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

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