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[PATCH openEuler-5.10 1/9] crypto: Add PMULL judgment during initialization to prevent oops
by Zheng Zengkai 26 Jan '22

26 Jan '22

From: wangshouping <wangshouping(a)huawei.com> openEuler inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4OKIE?from=project-issue CVE: NA ---------------------------------------- For servers that do not support PMULL on the cpu, execute "modprobe crct10dif-ce", and accur oops. Signed-off-by: wangshouping <wangshouping(a)huawei.com> Reviewed-by: Yue Haibing <yuehaibing(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- arch/arm64/crypto/crct10dif-neon_glue.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/crypto/crct10dif-neon_glue.c b/arch/arm64/crypto/crct10dif-neon_glue.c index e0c4a9acee27..af731b3ec30e 100644 --- a/arch/arm64/crypto/crct10dif-neon_glue.c +++ b/arch/arm64/crypto/crct10dif-neon_glue.c @@ -97,7 +97,11 @@ static struct shash_alg alg = { static int __init crct10dif_arm64_mod_init(void) { - return crypto_register_shash(&alg); + if (cpu_have_named_feature(PMULL)) { + return crypto_register_shash(&alg); + } else { + return -ENODEV; + } } static void __exit crct10dif_arm64_mod_fini(void) -- 2.20.1

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Re: [PATCH openEuler-1.0-LTS V3 34/92] KVM: mmu: Fix SPTE encoding of MMIO generation upper half
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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Re: [PATCH openEuler-1.0-LTS V3 32/92] KVM: x86: fix overlap between SPTE_MMIO_MASK and generation
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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[PATCH openEuler-1.0-LTS] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Yang Yingliang 26 Jan '22

26 Jan '22

From: Laibin Qiu <qiulaibin(a)huawei.com> phytium inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4RK58 CVE: NA -------------------------------- The system would hang up when the Phytium S2500 communicates with some BMCs after several rounds of transactions, unless we reset the controller timeout counter manually by calling firmware through SMC. Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> #openEuler_contributor Signed-off-by: Laibin Qiu <qiulaibin(a)huawei.com> Reviewed-by: Xie XiuQi <xiexiuqi(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- drivers/char/ipmi/ipmi_si_mem_io.c | 72 ++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c index 75583612ab105..9403e35a19934 100644 --- a/drivers/char/ipmi/ipmi_si_mem_io.c +++ b/drivers/char/ipmi/ipmi_si_mem_io.c @@ -3,9 +3,75 @@ #include <linux/io.h> #include "ipmi_si.h" +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 +#include <linux/arm-smccc.h> + +#define CTL_RST_FUNC_ID 0xC2000011 + +static bool apply_phytium2500_workaround; + +struct ipmi_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +}; + +static struct ipmi_workaround_oem_info wa_info[] = { + { + .oem_id = "KPSVVJ", + } +}; + +static void ipmi_check_phytium_workaround(void) +{ +#ifdef CONFIG_ACPI + struct acpi_table_header tbl; + int i; + + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) + return; + + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) + continue; + + apply_phytium2500_workaround = true; + break; + } +#endif +} + +static void ctl_smc(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3) +{ + struct arm_smccc_res res; + + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); + if (res.a0 != 0) + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", + (int)res.a0, arg2); +} + +static void ctl_timeout_reset(void) +{ + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); +} + +static inline void ipmi_phytium_workaround(void) +{ + if (apply_phytium2500_workaround) + ctl_timeout_reset(); +} + +#else +static inline void ipmi_check_phytium_workaround(void) {} +static inline void ipmi_phytium_workaround(void) {} +#endif + static unsigned char intf_mem_inb(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return readb((io->addr)+(offset * io->regspacing)); } @@ -31,6 +97,8 @@ static void intf_mem_outw(const struct si_sm_io *io, unsigned int offset, static unsigned char intf_mem_inl(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } @@ -44,6 +112,8 @@ static void intf_mem_outl(const struct si_sm_io *io, unsigned int offset, #ifdef readq static unsigned char mem_inq(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } @@ -81,6 +151,8 @@ int ipmi_si_mem_setup(struct si_sm_io *io) if (!addr) return -ENODEV; + ipmi_check_phytium_workaround(); + /* * Figure out the actual readb/readw/readl/etc routine to use based * upon the register size. -- 2.25.1

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Re: [PATCH openEuler-1.0-LTS V3 31/92] KVM: x86: assign two bits to track SPTE kinds
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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Re: [PATCH openEuler-1.0-LTS V3 30/92] KVM: Move the memslot update in-progress flag to bit 63
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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Re: [PATCH openEuler-1.0-LTS V3 29/92] KVM: Remove the hack to trigger memslot generation wraparound
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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Re: [PATCH openEuler-1.0-LTS V3 13/92] KVM: x86: Refactor the MMIO SPTE generation handling
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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Re: [PATCH openEuler-1.0-LTS V3 11/92] KVM: x86: Use a u64 when passing the MMIO gen around
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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Re: [PATCH openEuler-1.0-LTS V3 12/92] KVM: Explicitly define the "memslot update in-progress" bit
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

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