In "u32 otg_inst = pipe_ctx->stream_res.tg->inst;"
pipe_ctx->stream_res.tg could be NULL, it is relying on the caller to
ensure the tg is not NULL.
Dan Carpenter (1):
drm/amd/display: Fix && vs || typos
Srinivasan Shanmugam (1):
drm/amd/display: Add NULL test for 'timing generator' in
'dcn21_set_pipe()'
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
--
2.34.1