- Kernel - mailweb.openeuler.org

Re: [PATCH openEuler-1.0-LTS V3 29/92] KVM: Remove the hack to trigger memslot generation wraparound
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 13/92] KVM: x86: Refactor the MMIO SPTE generation handling
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 11/92] KVM: x86: Use a u64 when passing the MMIO gen around
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 12/92] KVM: Explicitly define the "memslot update in-progress" bit
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 27/92] KVM: SVM: Clear the CR4 register on reset
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 28/92] KVM: x86: clflushopt should be treated as a no-op by emulation
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 26/92] KVM: SVM: Replace hard-coded value with #define
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 25/92] KVM: x86/mmu: Set mmio_value to '0' if reserved #PF can't be generated
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 24/92] KVM: x86/mmu: Apply max PA check for MMIO sptes to 32-bit KVM
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 23/92] KVM: x86: only do L1TF workaround on affected processors
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 22/92] kvm: x86: Fix L1TF mitigation for shadow MMU
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 20/92] KVM: SVM: Override default MMIO mask if memory encryption is enabled
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 21/92] KVM: x86/mmu: Consolidate "is MMIO SPTE" code
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 19/92] KVM: x86/mmu: Add explicit access mask for MMIO SPTEs
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 17/92] KVM: x86: Rename access permissions cache member in struct kvm_vcpu_arch
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

[PATCH openEuler-5.10 00/68] Backport 5.10.89 LTS
by Zheng Zengkai 26 Jan '22

26 Jan '22

Backport 5.10.89 LTS patches from upstream. Andrea Righi (1): Input: elantech - fix stack out of bound access in elantech_change_report_id() Andrew Cooper (1): x86/pkey: Fix undefined behaviour with PKRU_WD_BIT Andrey Ryabinin (1): mm: mempolicy: fix THP allocations escaping mempolicy restrictions Ard Biesheuvel (1): ARM: 9169/1: entry: fix Thumb2 bug in iWMMXt exception handling Benjamin Tissoires (1): HID: holtek: fix mouse probing Bradley Scott (2): ALSA: hda/realtek: Amp init fixup for HP ZBook 15 G6 ALSA: hda/realtek: Add new alc285-hp-amp-init model Christian Brauner (1): ceph: fix up non-directory creation in SGID directories Colin Ian King (1): ALSA: drivers: opl3: Fix incorrect use of vp->state Derek Fang (1): ASoC: rt5682: fix the wrong jack type detected Dongliang Mu (1): spi: change clk_disable_unprepare to clk_unprepare Fabien Dessenne (1): pinctrl: stm32: consider the GPIO offset to expose all the GPIO lines Fernando Fernandez Mancera (1): bonding: fix ad_actor_system option setting to default Greg Jesionowski (1): net: usb: lan78xx: add Allied Telesis AT29M2-AF Guenter Roeck (6): hwmon: (lm90) Fix usage of CONFIG2 register in detect function hwmon: (lm90) Introduce flag indicating extended temperature support hwmon: (lm90) Add basic support for TI TMP461 hwmon: (lm90) Drop critical attribute support for MAX6654 hwmom: (lm90) Fix citical alarm status for MAX6680/MAX6681 hwmon: (lm90) Do not report 'busy' status bit as alarm Guodong Liu (1): pinctrl: mediatek: fix global-out-of-bounds issue Hans de Goede (1): Input: goodix - add id->model mapping for the "9111" model Heiner Kallweit (1): igb: fix deadlock caused by taking RTNL in RPM resume path Jiacheng Shi (1): RDMA/hns: Replace kfree() with kvfree() Jiasheng Jiang (7): HID: potential dereference of null pointer qlcnic: potential dereference null pointer of rx_queue->page_ring fjes: Check for error irq drivers: net: smc911x: Check for error irq net: ks8851: Check for error irq sfc: Check null pointer of rx_queue->page_ring sfc: falcon: Check null pointer of rx_queue->page_ring Johan Hovold (1): platform/x86: intel_pmc_core: fix memleak on registration failure Johannes Berg (1): mac80211: fix locking in ieee80211_start_ap error path John David Anglin (2): parisc: Correct completer in lws start parisc: Fix mask used to select futex spinlock Johnny Chuang (1): Input: elants_i2c - do not check Remark ID on eKTH3900/eKTH5312 José Expósito (2): IB/qib: Fix memory leak in qib_user_sdma_queue_pkts() Input: atmel_mxt_ts - fix double free in mxt_read_info_block Lin Ma (3): ax25: NPD bug when detaching AX25 device hamradio: defer ax25 kfree after unregister_netdev hamradio: improve the incomplete fix to avoid NPD Marian Postevca (1): usb: gadget: u_ether: fix race in setting MAC address in setup phase Martin Blumenstingl (3): ASoC: meson: aiu: fifo: Add missing dma_coerce_mask_and_coherent() ASoC: meson: aiu: Move AIU_I2S_MISC hold setting to aiu-fifo-i2s mmc: meson-mx-sdhc: Set MANUAL_STOP for multi-block SDIO commands Martin Haaß (1): ARM: dts: imx6qdl-wandboard: Fix Ethernet support Martin Povišer (1): ASoC: tas2770: Fix setting of high sample rates Mian Yousaf Kaukab (1): ipmi: ssif: initialize ssif_info->client early Nick Desaulniers (2): arm64: vdso32: drop -no-integrated-as flag arm64: vdso32: require CROSS_COMPILE_COMPAT for gcc+bfd Noralf Trønnes (1): gpio: dln2: Fix interrupts when replugging the device Phil Elwell (1): pinctrl: bcm2835: Change init order for gpio hogs Prathamesh Shete (1): mmc: sdhci-tegra: Fix switch to HS400ES mode Robert Marko (1): arm64: dts: allwinner: orangepi-zero-plus: fix PHY mode Rémi Denis-Courmont (1): phonet/pep: refuse to enable an unbound pipe Sean Christopherson (2): KVM: VMX: Wake vCPU when delivering posted IRQ even if vCPU == this vCPU KVM: VMX: Fix stale docs for kvm-intel.emulate_invalid_guest_state Sumit Garg (1): tee: optee: Fix incorrect page free bug Thadeu Lima de Souza Cascardo (2): ipmi: bail out if init_srcu_struct fails ipmi: fix initialization when workqueue allocation fails Ulf Hansson (1): mmc: core: Disable card detect during shutdown Werner Sembach (1): ALSA: hda/realtek: Fix quirk for Clevo NJ51CU Willem de Bruijn (2): net: accept UFOv6 packages in virtio_net_hdr_to_skb net: skip virtio_net_hdr_set_proto if protocol already set Wu Bo (1): ipmi: Fix UAF when uninstall ipmi_si and ipmi_msghandler module Xiaoke Wang (1): ALSA: jack: Check the return value of kstrdup() Yann Gautier (1): mmc: mmci: stm32: clear DLYB_CR after sending tuning command Yevhen Orlov (1): net: marvell: prestera: fix incorrect return of port_find .../admin-guide/kernel-parameters.txt | 8 +- Documentation/hwmon/lm90.rst | 10 + Documentation/networking/bonding.rst | 11 +- Documentation/sound/hd-audio/models.rst | 2 + arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 1 + arch/arm/kernel/entry-armv.S | 8 +- arch/arm64/Kconfig | 3 +- .../sun50i-h5-orangepi-zero-plus.dts | 2 +- arch/arm64/kernel/vdso32/Makefile | 25 +-- arch/parisc/include/asm/futex.h | 4 +- arch/parisc/kernel/syscall.S | 2 +- arch/x86/include/asm/pgtable.h | 4 +- arch/x86/kvm/vmx/vmx.c | 3 +- drivers/char/ipmi/ipmi_msghandler.c | 21 ++- drivers/char/ipmi/ipmi_ssif.c | 7 +- drivers/gpio/gpio-dln2.c | 19 +- drivers/hid/hid-holtek-mouse.c | 15 ++ drivers/hid/hid-vivaldi.c | 3 + drivers/hwmon/Kconfig | 2 +- drivers/hwmon/lm90.c | 171 +++++++++++------- drivers/infiniband/hw/hns/hns_roce_srq.c | 2 +- drivers/infiniband/hw/qib/qib_user_sdma.c | 2 +- drivers/input/mouse/elantech.c | 8 +- drivers/input/touchscreen/atmel_mxt_ts.c | 2 +- drivers/input/touchscreen/elants_i2c.c | 46 ++++- drivers/input/touchscreen/goodix.c | 1 + drivers/mmc/core/core.c | 7 +- drivers/mmc/core/core.h | 1 + drivers/mmc/core/host.c | 9 + drivers/mmc/host/meson-mx-sdhc-mmc.c | 16 ++ drivers/mmc/host/mmci_stm32_sdmmc.c | 2 + drivers/mmc/host/sdhci-tegra.c | 43 +++-- drivers/net/bonding/bond_options.c | 2 +- drivers/net/ethernet/intel/igb/igb_main.c | 19 +- .../ethernet/marvell/prestera/prestera_main.c | 16 +- drivers/net/ethernet/micrel/ks8851_par.c | 2 + .../net/ethernet/qlogic/qlcnic/qlcnic_sriov.h | 2 +- .../qlogic/qlcnic/qlcnic_sriov_common.c | 12 +- .../ethernet/qlogic/qlcnic/qlcnic_sriov_pf.c | 4 +- drivers/net/ethernet/sfc/falcon/rx.c | 5 +- drivers/net/ethernet/sfc/rx_common.c | 5 +- drivers/net/ethernet/smsc/smc911x.c | 5 + drivers/net/fjes/fjes_main.c | 5 + drivers/net/hamradio/mkiss.c | 5 +- drivers/net/usb/lan78xx.c | 6 + drivers/pinctrl/bcm/pinctrl-bcm2835.c | 29 +-- .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 8 +- drivers/pinctrl/stm32/pinctrl-stm32.c | 8 +- drivers/platform/x86/intel_pmc_core_pltdrv.c | 2 +- drivers/spi/spi-armada-3700.c | 2 +- drivers/tee/optee/shm_pool.c | 6 +- drivers/usb/gadget/function/u_ether.c | 15 +- fs/ceph/file.c | 18 +- include/linux/virtio_net.h | 25 ++- mm/mempolicy.c | 3 +- net/ax25/af_ax25.c | 4 +- net/mac80211/cfg.c | 3 + net/phonet/pep.c | 2 + sound/core/jack.c | 4 + sound/drivers/opl3/opl3_midi.c | 2 +- sound/pci/hda/patch_realtek.c | 28 ++- sound/soc/codecs/rt5682.c | 4 + sound/soc/codecs/tas2770.c | 4 +- sound/soc/meson/aiu-encoder-i2s.c | 33 ---- sound/soc/meson/aiu-fifo-i2s.c | 19 ++ sound/soc/meson/aiu-fifo.c | 6 + 66 files changed, 521 insertions(+), 252 deletions(-) -- 2.20.1

1 68

Re: [PATCH openEuler-1.0-LTS V3 18/92] kvm: x86: Fix reserved bits related calculation errors caused by MKTME
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 16/92] kvm: x86: Move kvm_set_mmio_spte_mask() from x86.c to mmu.c
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 15/92] kvm/svm: PKU not currently supported
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 14/92] kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 10/92] KVM: x86: expose MOVDIR64B CPU feature into VM.
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 09/92] KVM: x86: expose MOVDIRI CPU feature into VM.
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 08/92] KVM: x86: Add requisite includes to hyperv.h
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 07/92] KVM: x86: Add requisite includes to kvm_cache_regs.h
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 06/92] KVM: nVMX: Allocate and configure VM{READ,WRITE} bitmaps iff enable_shadow_vmcs
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

[PATCH OLK-5.10] eulerfs: remove redundant calculations
by Gou Hao 26 Jan '22

26 Jan '22

uniontech inclusion category: cleanup CVE: NA The 'left' always is 0. If it is not 0, it will 'goto out;' from the previous if judgment. --- Signed-off-by: Gou Hao <gouhao(a)uniontech.com> --- fs/eulerfs/dax.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/eulerfs/dax.c b/fs/eulerfs/dax.c index 9ec8ad7..131d08f 100644 --- a/fs/eulerfs/dax.c +++ b/fs/eulerfs/dax.c @@ -1172,8 +1172,8 @@ static ssize_t do_mapping_read(struct address_space *mapping, goto out; } - copied += (nr - left); - offset += (nr - left); + copied += nr; + offset += nr; index += offset >> PAGE_SHIFT; offset &= ~PAGE_MASK; } while (copied < len); -- 2.20.1

1 0

[PATCH] eulerfs: remove redundant calculations
by Gou Hao 26 Jan '22

26 Jan '22

uniontech inclusion category: cleanup CVE: NA The 'left' always is 0. If it is not 0, it will 'goto out;' from the previous if judgment. --- Signed-off-by: Gou Hao <gouhao(a)uniontech.com> --- fs/eulerfs/dax.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/eulerfs/dax.c b/fs/eulerfs/dax.c index 9ec8ad7..131d08f 100644 --- a/fs/eulerfs/dax.c +++ b/fs/eulerfs/dax.c @@ -1172,8 +1172,8 @@ static ssize_t do_mapping_read(struct address_space *mapping, goto out; } - copied += (nr - left); - offset += (nr - left); + copied += nr; + offset += nr; index += offset >> PAGE_SHIFT; offset &= ~PAGE_MASK; } while (copied < len); -- 2.20.1

1 0

[PATCH OLK-5.10 v6 0/2] change arm64 and x86 configs
by Chao Liu 26 Jan '22

26 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 265 +++++++----- arch/x86/configs/openeuler_defconfig | 549 +++++++++---------------- 2 files changed, 349 insertions(+), 465 deletions(-) -- 2.27.0

3 5

[PATCH openEuler-1.0-LTS 1/3] etmem: add original kernel swap enabled options
by Yang Yingliang 26 Jan '22

26 Jan '22

From: liubo <liubo254(a)huawei.com> euleros inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4QVXW CVE: NA ------------------------------------------------- etmem, the memory vertical expansion technology, uses DRAM and high-performance storage new media to form multi-level memory storage. By grading the stored data, etmem migrates the classified cold storage data from the storage medium to the high-performance storage medium, so as to achieve the purpose of memory capacity expansion and memory cost reduction. When the memory expansion function etmem is running, the native swap function of the kernel needs to be disabled in certain scenarios to avoid the impact of kernel swap. This feature provides the preceding functions. The /sys/kernel/mm/swap/ directory provides the kernel_swap_enable sys interface to enable or disable the native swap function of the kernel. The default value of /sys/kernel/mm/swap/kernel_swap_enable is true, that is, kernel swap is enabled by default. Turn on kernel swap: echo true > /sys/kernel/mm/swap/kernel_swap_enable Turn off kernel swap: echo false > /sys/kernel/mm/swap/kernel_swap_enable Signed-off-by: liubo <liubo254(a)huawei.com> Reviewed-by: Miaohe Lin <linmiaohe(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- include/linux/swap.h | 1 + mm/swap_state.c | 29 +++++++++++++++++++++++++++++ mm/vmscan.c | 18 ++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/include/linux/swap.h b/include/linux/swap.h index b7cfad35987a2..23549741336a4 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h @@ -476,6 +476,7 @@ extern struct page *swap_cluster_readahead(swp_entry_t entry, gfp_t flag, struct vm_fault *vmf); extern struct page *swapin_readahead(swp_entry_t entry, gfp_t flag, struct vm_fault *vmf); +extern bool kernel_swap_enabled(void); /* linux/mm/swapfile.c */ extern atomic_long_t nr_swap_pages; diff --git a/mm/swap_state.c b/mm/swap_state.c index 2137e2d571965..1527ac72928b6 100644 --- a/mm/swap_state.c +++ b/mm/swap_state.c @@ -40,6 +40,7 @@ static const struct address_space_operations swap_aops = { struct address_space *swapper_spaces[MAX_SWAPFILES] __read_mostly; static unsigned int nr_swapper_spaces[MAX_SWAPFILES] __read_mostly; static bool enable_vma_readahead __read_mostly = true; +static bool enable_kernel_swap __read_mostly = true; #define SWAP_RA_WIN_SHIFT (PAGE_SHIFT / 2) #define SWAP_RA_HITS_MASK ((1UL << SWAP_RA_WIN_SHIFT) - 1) @@ -326,6 +327,11 @@ static inline bool swap_use_vma_readahead(void) return READ_ONCE(enable_vma_readahead) && !atomic_read(&nr_rotate_swap); } +bool kernel_swap_enabled(void) +{ + return READ_ONCE(enable_kernel_swap); +} + /* * Lookup a swap entry in the swap cache. A found page will be returned * unlocked and with its refcount incremented - we rely on the kernel @@ -828,8 +834,31 @@ static struct kobj_attribute vma_ra_enabled_attr = __ATTR(vma_ra_enabled, 0644, vma_ra_enabled_show, vma_ra_enabled_store); +static ssize_t kernel_swap_enable_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", enable_kernel_swap ? "true" : "false"); +} +static ssize_t kernel_swap_enable_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + if (!strncmp(buf, "true", 4) || !strncmp(buf, "1", 1)) + WRITE_ONCE(enable_kernel_swap, true); + else if (!strncmp(buf, "false", 5) || !strncmp(buf, "0", 1)) + WRITE_ONCE(enable_kernel_swap, false); + else + return -EINVAL; + + return count; +} +static struct kobj_attribute kernel_swap_enable_attr = + __ATTR(kernel_swap_enable, 0644, kernel_swap_enable_show, + kernel_swap_enable_store); + static struct attribute *swap_attrs[] = { &vma_ra_enabled_attr.attr, + &kernel_swap_enable_attr.attr, NULL, }; diff --git a/mm/vmscan.c b/mm/vmscan.c index e8befe70d2800..2676d6cf2ccac 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -3248,6 +3248,16 @@ static bool throttle_direct_reclaim(gfp_t gfp_mask, struct zonelist *zonelist, return false; } +/* + * Check if original kernel swap is enabled + * turn off kernel swap,but leave page cache reclaim on + */ +static inline void kernel_swap_check(struct scan_control *sc) +{ + if (sc != NULL && !kernel_swap_enabled()) + sc->may_swap = 0; +} + unsigned long try_to_free_pages(struct zonelist *zonelist, int order, gfp_t gfp_mask, nodemask_t *nodemask) { @@ -3264,6 +3274,7 @@ unsigned long try_to_free_pages(struct zonelist *zonelist, int order, .may_swap = 1, }; + kernel_swap_check(&sc); /* * scan_control uses s8 fields for order, priority, and reclaim_idx. * Confirm they are large enough for max values. @@ -3548,6 +3559,8 @@ static int balance_pgdat(pg_data_t *pgdat, int order, int classzone_idx) count_vm_event(PAGEOUTRUN); + kernel_swap_check(&sc); + #ifdef CONFIG_SHRINK_PAGECACHE if (vm_cache_limit_mbytes && page_cache_over_limit()) shrink_page_cache(GFP_KERNEL); @@ -3963,6 +3976,8 @@ static unsigned long __shrink_page_cache(gfp_t mask) struct zonelist *zonelist = node_zonelist(numa_node_id(), mask); + kernel_swap_check(&sc); + return do_try_to_free_pages(zonelist, &sc); } @@ -4282,6 +4297,9 @@ static int __node_reclaim(struct pglist_data *pgdat, gfp_t gfp_mask, unsigned in cond_resched(); fs_reclaim_acquire(sc.gfp_mask); + + kernel_swap_check(&sc); + /* * We need to be able to allocate from the reserves for RECLAIM_UNMAP * and we also need to be able to write out pages for RECLAIM_WRITE -- 2.25.1

1 2

[PATCH OLK-5.10 v5 0/2] change arm64 and x86 configs
by Chao Liu 25 Jan '22

25 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 260 +++++++----- arch/x86/configs/openeuler_defconfig | 531 ++++++++----------------- 2 files changed, 337 insertions(+), 454 deletions(-) -- 2.27.0

5 9

[PATCH openEuler-1.0-LTS] net: bridge: clear bridge's private skb space on xmit
by Yang Yingliang 24 Jan '22

24 Jan '22

From: Nikolay Aleksandrov <nikolay(a)cumulusnetworks.com> mainline inclusion from mainline-v5.9-rc1 commit fd65e5a95d08389444e8591a20538b3edece0e15 category: bugfix bugzilla: 186114 CVE: NA -------------------------------- We need to clear all of the bridge private skb variables as they can be stale due to the packet being recirculated through the stack and then transmitted through the bridge device. Similar memset is already done on bridge's input. We've seen cases where proxyarp_replied was 1 on routed multicast packets transmitted through the bridge to ports with neigh suppress which were getting dropped. Same thing can in theory happen with the port isolation bit as well. Fixes: 821f1b21cabb ("bridge: add new BR_NEIGH_SUPPRESS port flag to suppress arp and nd flood") Signed-off-by: Nikolay Aleksandrov <nikolay(a)cumulusnetworks.com> Signed-off-by: David S. Miller <davem(a)davemloft.net> Signed-off-by: Huang Guobin <huangguobin4(a)huawei.com> Reviewed-by: Yue Haibing <yuehaibing(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- net/bridge/br_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/bridge/br_device.c b/net/bridge/br_device.c index 7b7784bb1cb99..9475e0443ff92 100644 --- a/net/bridge/br_device.c +++ b/net/bridge/br_device.c @@ -41,6 +41,8 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) const unsigned char *dest; u16 vid = 0; + memset(skb->cb, 0, sizeof(struct br_input_skb_cb)); + rcu_read_lock(); nf_ops = rcu_dereference(nf_br_ops); if (nf_ops && nf_ops->br_dev_xmit_hook(skb)) { -- 2.25.1

1 0

[PATCH openEuler-5.10 01/38] tcp_comp: implement sendmsg for tcp compression
by Zheng Zengkai 22 Jan '22

22 Jan '22

From: Wei Yongjun <weiyongjun1(a)huawei.com> hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4PNEK CVE: NA ------------------------------------------------- This patch implement software level compression for sending tcp messages. All of the TCP payload will be compressed before xmit. Signed-off-by: Wei Yongjun <weiyongjun1(a)huawei.com> Signed-off-by: Wang Yufen <wangyufen(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> Signed-off-by: Lu Wei <luwei32(a)huawei.com> Reviewed-by: Wang Yufen <wangyufen(a)huawei.com> Reviewed-by: Wei Yongjun <weiyongjun1(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- net/ipv4/Kconfig | 1 + net/ipv4/tcp_comp.c | 415 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 412 insertions(+), 4 deletions(-) diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig index 59ffbf80f7f2..22c554d3a9ab 100644 --- a/net/ipv4/Kconfig +++ b/net/ipv4/Kconfig @@ -745,6 +745,7 @@ config TCP_MD5SIG config TCP_COMP bool "TCP: Transport Layer Compression support" + depends on ZSTD_COMPRESS=y help Enable kernel payload compression support for TCP protocol. This allows payload compression handling of the TCP protocol to be done in-kernel. diff --git a/net/ipv4/tcp_comp.c b/net/ipv4/tcp_comp.c index fb90be4d9e9c..e85803da3924 100644 --- a/net/ipv4/tcp_comp.c +++ b/net/ipv4/tcp_comp.c @@ -5,7 +5,15 @@ * Copyright(c) 2021 Huawei Technologies Co., Ltd */ -#include <net/tcp.h> +#include <linux/skmsg.h> +#include <linux/zstd.h> + +#define TCP_COMP_MAX_PADDING 64 +#define TCP_COMP_SCRATCH_SIZE 65400 +#define TCP_COMP_MAX_CSIZE (TCP_COMP_SCRATCH_SIZE + TCP_COMP_MAX_PADDING) + +#define TCP_COMP_SEND_PENDING 1 +#define ZSTD_COMP_DEFAULT_LEVEL 1 static unsigned long tcp_compression_ports[65536 / 8]; @@ -14,11 +22,37 @@ int sysctl_tcp_compression_local __read_mostly; static struct proto tcp_prot_override; +struct tcp_comp_context_tx { + ZSTD_CStream *cstream; + void *cworkspace; + void *plaintext_data; + void *compressed_data; + struct sk_msg msg; + bool in_tcp_sendpages; +}; + struct tcp_comp_context { - struct proto *sk_proto; struct rcu_head rcu; + + struct proto *sk_proto; + void (*sk_write_space)(struct sock *sk); + + struct tcp_comp_context_tx tx; + + unsigned long flags; }; +static bool tcp_comp_is_write_pending(struct tcp_comp_context *ctx) +{ + return test_bit(TCP_COMP_SEND_PENDING, &ctx->flags); +} + +static void tcp_comp_err_abort(struct sock *sk, int err) +{ + sk->sk_err = err; + sk->sk_error_report(sk); +} + static bool tcp_comp_enabled(__be32 saddr, __be32 daddr, int port) { if (!sysctl_tcp_compression_local && @@ -55,11 +89,341 @@ static struct tcp_comp_context *comp_get_ctx(const struct sock *sk) return (__force void *)icsk->icsk_ulp_data; } -static int tcp_comp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) +static int tcp_comp_tx_context_init(struct tcp_comp_context *ctx) +{ + ZSTD_parameters params; + int csize; + + params = ZSTD_getParams(ZSTD_COMP_DEFAULT_LEVEL, PAGE_SIZE, 0); + csize = ZSTD_CStreamWorkspaceBound(params.cParams); + if (csize <= 0) + return -EINVAL; + + ctx->tx.cworkspace = kmalloc(csize, GFP_KERNEL); + if (!ctx->tx.cworkspace) + return -ENOMEM; + + ctx->tx.cstream = ZSTD_initCStream(params, 0, ctx->tx.cworkspace, + csize); + if (!ctx->tx.cstream) + goto err_cstream; + + ctx->tx.plaintext_data = kvmalloc(TCP_COMP_SCRATCH_SIZE, GFP_KERNEL); + if (!ctx->tx.plaintext_data) + goto err_cstream; + + ctx->tx.compressed_data = kvmalloc(TCP_COMP_MAX_CSIZE, GFP_KERNEL); + if (!ctx->tx.compressed_data) + goto err_compressed; + + return 0; + +err_compressed: + kvfree(ctx->tx.plaintext_data); + ctx->tx.plaintext_data = NULL; +err_cstream: + kfree(ctx->tx.cworkspace); + ctx->tx.cworkspace = NULL; + + return -ENOMEM; +} + +static void *tcp_comp_get_tx_stream(struct sock *sk) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + + if (!ctx->tx.plaintext_data) + tcp_comp_tx_context_init(ctx); + + return ctx->tx.plaintext_data; +} + +static int alloc_compressed_msg(struct sock *sk, int len) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct sk_msg *msg = &ctx->tx.msg; + + sk_msg_init(msg); + + return sk_msg_alloc(sk, msg, len, 0); +} + +static int memcopy_from_iter(struct sock *sk, struct iov_iter *from, int copy) +{ + void *dest; + int rc; + + dest = tcp_comp_get_tx_stream(sk); + if (!dest) + return -ENOSPC; + + if (sk->sk_route_caps & NETIF_F_NOCACHE_COPY) + rc = copy_from_iter_nocache(dest, copy, from); + else + rc = copy_from_iter(dest, copy, from); + + if (rc != copy) + rc = -EFAULT; + + return rc; +} + +static int memcopy_to_msg(struct sock *sk, int bytes) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct sk_msg *msg = &ctx->tx.msg; + int i = msg->sg.curr; + struct scatterlist *sge; + u32 copy, buf_size; + void *from, *to; + + from = ctx->tx.compressed_data; + do { + sge = sk_msg_elem(msg, i); + /* This is possible if a trim operation shrunk the buffer */ + if (msg->sg.copybreak >= sge->length) { + msg->sg.copybreak = 0; + sk_msg_iter_var_next(i); + if (i == msg->sg.end) + break; + sge = sk_msg_elem(msg, i); + } + buf_size = sge->length - msg->sg.copybreak; + copy = (buf_size > bytes) ? bytes : buf_size; + to = sg_virt(sge) + msg->sg.copybreak; + msg->sg.copybreak += copy; + memcpy(to, from, copy); + bytes -= copy; + from += copy; + if (!bytes) + break; + msg->sg.copybreak = 0; + sk_msg_iter_var_next(i); + } while (i != msg->sg.end); + + msg->sg.curr = i; + return bytes; +} + +static int tcp_comp_compress_to_msg(struct sock *sk, int bytes) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + ZSTD_outBuffer outbuf; + ZSTD_inBuffer inbuf; + size_t ret; + + inbuf.src = ctx->tx.plaintext_data; + outbuf.dst = ctx->tx.compressed_data; + inbuf.size = bytes; + outbuf.size = TCP_COMP_MAX_CSIZE; + inbuf.pos = 0; + outbuf.pos = 0; + + ret = ZSTD_compressStream(ctx->tx.cstream, &outbuf, &inbuf); + if (ZSTD_isError(ret)) + return -EIO; + + ret = ZSTD_flushStream(ctx->tx.cstream, &outbuf); + if (ZSTD_isError(ret)) + return -EIO; + + if (inbuf.pos != inbuf.size) + return -EIO; + + if (memcopy_to_msg(sk, outbuf.pos)) + return -EIO; + + sk_msg_trim(sk, &ctx->tx.msg, outbuf.pos); + + return 0; +} + +static int tcp_comp_push_msg(struct sock *sk, struct sk_msg *msg, int flags) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct scatterlist *sg; + int ret, offset; + struct page *p; + size_t size; + + ctx->tx.in_tcp_sendpages = true; + while (1) { + sg = sk_msg_elem(msg, msg->sg.start); + offset = sg->offset; + size = sg->length; + p = sg_page(sg); +retry: + ret = do_tcp_sendpages(sk, p, offset, size, flags); + if (ret != size) { + if (ret > 0) { + sk_mem_uncharge(sk, ret); + sg->offset += ret; + sg->length -= ret; + size -= ret; + offset += ret; + goto retry; + } + ctx->tx.in_tcp_sendpages = false; + return ret; + } + + sk_mem_uncharge(sk, ret); + msg->sg.size -= size; + put_page(p); + sk_msg_iter_next(msg, start); + if (msg->sg.start == msg->sg.end) + break; + } + + clear_bit(TCP_COMP_SEND_PENDING, &ctx->flags); + ctx->tx.in_tcp_sendpages = false; + + return 0; +} + +static int tcp_comp_push(struct sock *sk, int bytes, int flags) { struct tcp_comp_context *ctx = comp_get_ctx(sk); + int ret; - return ctx->sk_proto->sendmsg(sk, msg, size); + ret = tcp_comp_compress_to_msg(sk, bytes); + if (ret < 0) { + pr_debug("%s: failed to compress sg\n", __func__); + return ret; + } + + set_bit(TCP_COMP_SEND_PENDING, &ctx->flags); + + ret = tcp_comp_push_msg(sk, &ctx->tx.msg, flags); + if (ret) { + pr_debug("%s: failed to tcp_comp_push_sg\n", __func__); + return ret; + } + + return 0; +} + +static int wait_on_pending_writer(struct sock *sk, long *timeo) +{ + DEFINE_WAIT_FUNC(wait, woken_wake_function); + int ret = 0; + + add_wait_queue(sk_sleep(sk), &wait); + while (1) { + if (!*timeo) { + ret = -EAGAIN; + break; + } + + if (signal_pending(current)) { + ret = sock_intr_errno(*timeo); + break; + } + + if (sk_wait_event(sk, timeo, !sk->sk_write_pending, &wait)) + break; + } + remove_wait_queue(sk_sleep(sk), &wait); + + return ret; +} + +static int tcp_comp_push_pending_msg(struct sock *sk, int flags) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct sk_msg *msg = &ctx->tx.msg; + + if (msg->sg.start == msg->sg.end) + return 0; + + return tcp_comp_push_msg(sk, msg, flags); +} + +static int tcp_comp_complete_pending_work(struct sock *sk, int flags, + long *timeo) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + int ret = 0; + + if (unlikely(sk->sk_write_pending)) + ret = wait_on_pending_writer(sk, timeo); + + if (!ret && tcp_comp_is_write_pending(ctx)) + ret = tcp_comp_push_pending_msg(sk, flags); + + return ret; +} + +static int tcp_comp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + int copied = 0, err = 0; + size_t try_to_copy; + int required_size; + long timeo; + + lock_sock(sk); + + timeo = sock_sndtimeo(sk, msg->msg_flags & MSG_DONTWAIT); + + err = tcp_comp_complete_pending_work(sk, msg->msg_flags, &timeo); + if (err) + goto out_err; + + while (msg_data_left(msg)) { + if (sk->sk_err) { + err = -sk->sk_err; + goto out_err; + } + + try_to_copy = msg_data_left(msg); + if (try_to_copy > TCP_COMP_SCRATCH_SIZE) + try_to_copy = TCP_COMP_SCRATCH_SIZE; + required_size = try_to_copy + TCP_COMP_MAX_PADDING; + + if (!sk_stream_memory_free(sk)) + goto wait_for_sndbuf; + +alloc_compressed: + err = alloc_compressed_msg(sk, required_size); + if (err) { + if (err != -ENOSPC) + goto wait_for_memory; + goto out_err; + } + + err = memcopy_from_iter(sk, &msg->msg_iter, try_to_copy); + if (err < 0) + goto out_err; + + copied += try_to_copy; + + err = tcp_comp_push(sk, try_to_copy, msg->msg_flags); + if (err < 0) { + if (err == -ENOMEM) + goto wait_for_memory; + if (err != -EAGAIN) + tcp_comp_err_abort(sk, EBADMSG); + goto out_err; + } + + continue; +wait_for_sndbuf: + set_bit(SOCK_NOSPACE, &sk->sk_socket->flags); +wait_for_memory: + err = sk_stream_wait_memory(sk, &timeo); + if (err) + goto out_err; + if (ctx->tx.msg.sg.size < required_size) + goto alloc_compressed; + } + +out_err: + err = sk_stream_error(sk, msg->msg_flags, err); + + release_sock(sk); + + return copied ? copied : err; } static int tcp_comp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, @@ -70,10 +434,35 @@ static int tcp_comp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, return ctx->sk_proto->recvmsg(sk, msg, len, nonblock, flags, addr_len); } +static void tcp_comp_write_space(struct sock *sk) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + + if (ctx->tx.in_tcp_sendpages) { + ctx->sk_write_space(sk); + return; + } + + if (!sk->sk_write_pending && tcp_comp_is_write_pending(ctx)) { + gfp_t sk_allocation = sk->sk_allocation; + int rc; + + sk->sk_allocation = GFP_ATOMIC; + rc = tcp_comp_push_pending_msg(sk, MSG_DONTWAIT | MSG_NOSIGNAL); + sk->sk_allocation = sk_allocation; + + if (rc < 0) + return; + } + + ctx->sk_write_space(sk); +} + void tcp_init_compression(struct sock *sk) { struct inet_connection_sock *icsk = inet_csk(sk); struct tcp_comp_context *ctx = NULL; + struct sk_msg *msg = NULL; struct tcp_sock *tp = tcp_sk(sk); if (!tp->rx_opt.comp_ok) @@ -83,20 +472,38 @@ void tcp_init_compression(struct sock *sk) if (!ctx) return; + msg = &ctx->tx.msg; + sk_msg_init(msg); + + ctx->sk_write_space = sk->sk_write_space; ctx->sk_proto = sk->sk_prot; WRITE_ONCE(sk->sk_prot, &tcp_prot_override); + sk->sk_write_space = tcp_comp_write_space; rcu_assign_pointer(icsk->icsk_ulp_data, ctx); sock_set_flag(sk, SOCK_COMP); } +static void tcp_comp_context_tx_free(struct tcp_comp_context *ctx) +{ + kfree(ctx->tx.cworkspace); + ctx->tx.cworkspace = NULL; + + kvfree(ctx->tx.plaintext_data); + ctx->tx.plaintext_data = NULL; + + kvfree(ctx->tx.compressed_data); + ctx->tx.compressed_data = NULL; +} + static void tcp_comp_context_free(struct rcu_head *head) { struct tcp_comp_context *ctx; ctx = container_of(head, struct tcp_comp_context, rcu); + tcp_comp_context_tx_free(ctx); kfree(ctx); } -- 2.20.1

1 37

[PATCH OLK-5.10 v3 0/2] change arm64 and x86 configs
by Chao Liu 22 Jan '22

22 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 292 ++++++++----- arch/x86/configs/openeuler_defconfig | 548 +++++++++---------------- 2 files changed, 380 insertions(+), 460 deletions(-) -- 2.27.0

5 9

[PATCH OLK-5.10 v7 3/3] arm64: openeuler_defconfig: Enable ARM64_PMEM_LEGACY
by Zhuling 22 Jan '22

22 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Enable legacy pmem register feature for arm64. Signed-off-by: Zhuling <zhuling8(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> --- arch/arm64/configs/openeuler_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 771eb45..7745715 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -416,6 +416,8 @@ CONFIG_ARM64_CPU_PARK=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_ARM64_PMEM_RESERVE=y +CONFIG_ARM64_PMEM_LEGACY=m # CONFIG_ARM64_SW_TTBR0_PAN is not set CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_ILP32=y @@ -6027,6 +6029,8 @@ CONFIG_USB4=m # end of Android CONFIG_LIBNVDIMM=m +CONFIG_PMEM_LEGACY=m +CONFIG_PMEM_LEGACY_DEVICE=y CONFIG_BLK_DEV_PMEM=m CONFIG_ND_BLK=m CONFIG_ND_CLAIM=y -- 2.9.5

1 0

[PATCH OLK-5.10 v7 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by Zhuling 22 Jan '22

22 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of nd_e820.o, then the code could be reused by other architectures. Note，this patch fixs the nd_e820.c build introduced by commit 2499317e408e ("arm64: Revert feature: Add memmap parameter and register pmem"). Signed-off-by: Zhuling <zhuling8(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> --- arch/x86/Kconfig | 6 ++---- arch/x86/kernel/Makefile | 1 - drivers/nvdimm/Kconfig | 6 ++++++ drivers/nvdimm/Makefile | 2 ++ arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 tools/testing/nvdimm/Kbuild | 2 +- 6 files changed, 11 insertions(+), 6 deletions(-) rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c77ef59..1d3176a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE default 0 if X86_32 default 0xdead000000000000 if X86_64 -config X86_PMEM_LEGACY_DEVICE - bool - config X86_PMEM_LEGACY tristate "Support non-standard NVDIMMs and ADR protected memory" depends on PHYS_ADDR_T_64BIT depends on BLK_DEV - select X86_PMEM_LEGACY_DEVICE + select PMEM_LEGACY + select PMEM_LEGACY_DEVICE select NUMA_KEEP_MEMINFO if NUMA select LIBNVDIMM help diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f0606f8..1e12751 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index b7d1eb3..632b6ed 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM if LIBNVDIMM +config PMEM_LEGACY + tristate + +config PMEM_LEGACY_DEVICE + bool + config BLK_DEV_PMEM tristate "PMEM: Persistent memory block device support" default LIBNVDIMM diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 0407753..2098221 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_OF_PMEM) += of_pmem.o obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c similarity index 100% rename from arch/x86/kernel/pmem.c rename to drivers/nvdimm/pmem_legacy_device.c diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild index 47f9cc9..77aa117 100644 --- a/tools/testing/nvdimm/Kbuild +++ b/tools/testing/nvdimm/Kbuild @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_ACPI_NFIT) += nfit.o ifeq ($(CONFIG_DAX),m) obj-$(CONFIG_DAX) += dax.o -- 2.9.5

1 1

[PATCH OLK-5.10 v4 0/2] change arm64 and x86 configs
by Chao Liu 22 Jan '22

22 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 272 ++++++++----- arch/x86/configs/openeuler_defconfig | 540 +++++++++---------------- 2 files changed, 356 insertions(+), 456 deletions(-) -- 2.27.0

1 2

[PATCH openEuler-1.0-LTS V2] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Laibin Qiu 22 Jan '22

22 Jan '22

phytium inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4RK58 CVE: NA -------------------------------- The system would hang up when the Phytium S2500 communicates with some BMCs after several rounds of transactions, unless we reset the controller timeout counter manually by calling firmware through SMC. Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> #openEuler_contributor Signed-off-by: Laibin Qiu <qiulaibin(a)huawei.com> --- drivers/char/ipmi/ipmi_si_mem_io.c | 72 ++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c index 75583612ab10..9403e35a1993 100644 --- a/drivers/char/ipmi/ipmi_si_mem_io.c +++ b/drivers/char/ipmi/ipmi_si_mem_io.c @@ -3,9 +3,75 @@ #include <linux/io.h> #include "ipmi_si.h" +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 +#include <linux/arm-smccc.h> + +#define CTL_RST_FUNC_ID 0xC2000011 + +static bool apply_phytium2500_workaround; + +struct ipmi_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +}; + +static struct ipmi_workaround_oem_info wa_info[] = { + { + .oem_id = "KPSVVJ", + } +}; + +static void ipmi_check_phytium_workaround(void) +{ +#ifdef CONFIG_ACPI + struct acpi_table_header tbl; + int i; + + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) + return; + + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) + continue; + + apply_phytium2500_workaround = true; + break; + } +#endif +} + +static void ctl_smc(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3) +{ + struct arm_smccc_res res; + + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); + if (res.a0 != 0) + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", + (int)res.a0, arg2); +} + +static void ctl_timeout_reset(void) +{ + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); +} + +static inline void ipmi_phytium_workaround(void) +{ + if (apply_phytium2500_workaround) + ctl_timeout_reset(); +} + +#else +static inline void ipmi_check_phytium_workaround(void) {} +static inline void ipmi_phytium_workaround(void) {} +#endif + static unsigned char intf_mem_inb(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return readb((io->addr)+(offset * io->regspacing)); } @@ -31,6 +97,8 @@ static void intf_mem_outw(const struct si_sm_io *io, unsigned int offset, static unsigned char intf_mem_inl(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } @@ -44,6 +112,8 @@ static void intf_mem_outl(const struct si_sm_io *io, unsigned int offset, #ifdef readq static unsigned char mem_inq(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } @@ -81,6 +151,8 @@ int ipmi_si_mem_setup(struct si_sm_io *io) if (!addr) return -ENODEV; + ipmi_check_phytium_workaround(); + /* * Figure out the actual readb/readw/readl/etc routine to use based * upon the register size. -- 2.22.0

1 0

Re: [PATCH V2] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Xie XiuQi 21 Jan '22

21 Jan '22

On 2022/1/21 18:06, Chen Baozi wrote: > phytium inclusion > category: bugfix > bugzilla: https://gitee.com/openeuler/kernel/issues/I4RK58 > CVE: NA > > --------------------------------- > > The system would hang up when the Phytium S2500 communicates with > some BMCs after several rounds of transactions, unless we reset > the controller timeout counter manually by calling firmware through > SMC. > > Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> > Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> Looks good to me, Reviewed-by: Xie XiuQi <xiexiuqi(a)huawei.com> > --- > drivers/char/ipmi/ipmi_si_mem_io.c | 74 ++++++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c > index 75583612ab10..bb4ed90a1153 100644 > --- a/drivers/char/ipmi/ipmi_si_mem_io.c > +++ b/drivers/char/ipmi/ipmi_si_mem_io.c > @@ -3,9 +3,75 @@ > #include <linux/io.h> > #include "ipmi_si.h" > > +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 > +#include <linux/arm-smccc.h> > + > +#define CTL_RST_FUNC_ID 0xC2000011 > + > +static bool apply_phytium2500_workaround; > + > +struct ipmi_workaround_oem_info { > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > +}; > + > +static struct ipmi_workaround_oem_info wa_info[] = { > + { > + .oem_id = "KPSVVJ", > + } > +}; > + > +static void ipmi_check_phytium_workaround(void) > +{ > +#ifdef CONFIG_ACPI > + struct acpi_table_header tbl; > + int i; > + > + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) > + return; > + > + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { > + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) > + continue; > + > + apply_phytium2500_workaround = true; > + break; > + } > +#endif > +} > + > +static void ctl_smc(unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); > + if (res.a0 != 0) > + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", > + (int)res.a0, arg2); > +} > + > +static void ctl_timeout_reset(void) > +{ > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); > +} > + > +static inline void ipmi_phytium_workaround(void) > +{ > + if (apply_phytium2500_workaround) > + ctl_timeout_reset(); > +} > + > +#else > +static inline void ipmi_check_phytium_workaround(void) {} > +static inline void ipmi_phytium_workaround(void) {} > +#endif > + > static unsigned char intf_mem_inb(const struct si_sm_io *io, > unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return readb((io->addr)+(offset * io->regspacing)); > } > > @@ -18,6 +84,8 @@ static void intf_mem_outb(const struct si_sm_io *io, unsigned int offset, > static unsigned char intf_mem_inw(const struct si_sm_io *io, > unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) > & 0xff; > } > @@ -31,6 +99,8 @@ static void intf_mem_outw(const struct si_sm_io *io, unsigned int offset, > static unsigned char intf_mem_inl(const struct si_sm_io *io, > unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) > & 0xff; > } > @@ -44,6 +114,8 @@ static void intf_mem_outl(const struct si_sm_io *io, unsigned int offset, > #ifdef readq > static unsigned char mem_inq(const struct si_sm_io *io, unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) > & 0xff; > } > @@ -81,6 +153,8 @@ int ipmi_si_mem_setup(struct si_sm_io *io) > if (!addr) > return -ENODEV; > > + ipmi_check_phytium_workaround(); > + > /* > * Figure out the actual readb/readw/readl/etc routine to use based > * upon the register size. >

1 0

Re: [PATCH] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Xie XiuQi 21 Jan '22

21 Jan '22

Hi, Thanks for your patch. There're some comments bellow. On 2022/1/19 14:57, Chen Baozi wrote: > The system would hang up when the Phytium S2500 communicates with > some BMCs after several rounds of transactions, unless we reset > the controller timeout counter manually by calling firmware through > SMC. > > Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> > Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> > --- > drivers/char/ipmi/ipmi_si_mem_io.c | 117 ++++++++++++++++++++++++++++- > 1 file changed, 113 insertions(+), 4 deletions(-) > > diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c > index 75583612ab10..73a3d6979eaa 100644 > --- a/drivers/char/ipmi/ipmi_si_mem_io.c > +++ b/drivers/char/ipmi/ipmi_si_mem_io.c > @@ -3,6 +3,105 @@ > #include <linux/io.h> > #include "ipmi_si.h" > > +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 > +#include <linux/arm-smccc.h> > + > +#define CTL_RST_FUNC_ID 0xC2000011 > + > +static void ctl_smc(unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); > + if (res.a0 != 0) > + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", > + (int)res.a0, arg2); > +} > + > +static void ctl_timeout_reset(void) > +{ > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); > +} > + > +static unsigned char intf_mem_inb_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return readb((io->addr)+(offset * io->regspacing)); 与 intf_mem_inb（）代码重复，下同。 > +} > + > +static unsigned char intf_mem_inw_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char intf_mem_inl_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char mem_inq_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > +#else > +#define intf_mem_inb_2500 intf_mem_inb > +#define intf_mem_inw_2500 intf_mem_inw > +#define intf_mem_inl_2500 intf_mem_inl > +#define mem_inq_2500 mem_inq > +#endif > + > +static bool apply_phytium2500_workaround; 这个变量全局存在的，其实只在 phytium2500 平台上才有意义。 > + > +#ifdef CONFIG_ACPI > +struct ipmi_workaround_oem_info { > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > +}; > + > +static struct ipmi_workaround_oem_info wa_info[] = { > + { > + .oem_id = "KPSVVJ", > + } > +}; > + > +static void ipmi_check_phytium_workaround(void) > +{ > + struct acpi_table_header tbl; > + int i; > + > + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) > + return; > + > + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { > + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) > + continue; > + > + apply_phytium2500_workaround = true; > + break; > + } > +} 这个 CONFIG_ACPI 和 PHYTIUM 没有依赖，即便不是 PHYTIUM 平台，仍然会做这些没必要的检查。而且在非 ARM64 架构上，这个 apply_phytium2500_workaround 仍然会全局存在。是不是类似这样比较好： #ifdef CONFIG_ARM_GIC_PHYTIUM_2500 static bool apply_phytium2500_workaround; static void ipmi_check_phytium_workaround(void) { #ifdef CONFIG_ACPI ... #endif } ... static inline void ipmi_phytium2500_workaround（void） { if (apply_phytium2500_workaround) ctl_timeout_reset(); } static unsigned char intf_mem_inb(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium2500_workaround(); return readb((io->addr)+(offset * io->regspacing)); } static unsigned char intf_mem_inw(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium2500_workaround(); return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } ... #else static inline void ipmi_phytium2500_workaround（） {} static inline void ipmi_check_phytium_workaround(void) {} #endif > +#else > +static void ipmi_check_phytium_workaround(void) > +{ > + apply_phytium2500_workaround = false; > +} > +#endif > + > static unsigned char intf_mem_inb(const struct si_sm_io *io, > unsigned int offset) > { > @@ -81,26 +180,36 @@ int ipmi_si_mem_setup(struct si_sm_io *io) > if (!addr) > return -ENODEV; > > + ipmi_check_phytium_workaround(); > + > /* > * Figure out the actual readb/readw/readl/etc routine to use based > * upon the register size. > */ > switch (io->regsize) { > case 1: > - io->inputb = intf_mem_inb; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inb_2500 : > + intf_mem_inb; > io->outputb = intf_mem_outb; > break; > case 2: > - io->inputb = intf_mem_inw; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inw_2500 : > + intf_mem_inw; > io->outputb = intf_mem_outw; > break; > case 4: > - io->inputb = intf_mem_inl; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inl_2500 : > + intf_mem_inl; > io->outputb = intf_mem_outl; > break; > #ifdef readq > case 8: > - io->inputb = mem_inq; > + io->inputb = apply_phytium2500_workaround ? > + mem_inq_2500 : > + mem_inq; > io->outputb = mem_outq; > break; > #endif >

1 0

[PATCH OLK-5.10 v6 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by Zhuling 21 Jan '22

21 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of nd_e820.o, then the code could be reused by other architectures. Note��this patch fixs the nd_e820.c build introduced by commit 2499317e408e ("arm64: Revert feature: Add memmap parameter and register pmem"). Signed-off-by: Zhuling <zhuling8(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> --- arch/x86/Kconfig | 6 ++---- arch/x86/kernel/Makefile | 1 - drivers/nvdimm/Kconfig | 6 ++++++ drivers/nvdimm/Makefile | 2 ++ arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 tools/testing/nvdimm/Kbuild | 2 +- 6 files changed, 11 insertions(+), 6 deletions(-) rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c77ef59..1d3176a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE default 0 if X86_32 default 0xdead000000000000 if X86_64 -config X86_PMEM_LEGACY_DEVICE - bool - config X86_PMEM_LEGACY tristate "Support non-standard NVDIMMs and ADR protected memory" depends on PHYS_ADDR_T_64BIT depends on BLK_DEV - select X86_PMEM_LEGACY_DEVICE + select PMEM_LEGACY + select PMEM_LEGACY_DEVICE select NUMA_KEEP_MEMINFO if NUMA select LIBNVDIMM help diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f0606f8..1e12751 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index b7d1eb3..632b6ed 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM if LIBNVDIMM +config PMEM_LEGACY + tristate + +config PMEM_LEGACY_DEVICE + bool + config BLK_DEV_PMEM tristate "PMEM: Persistent memory block device support" default LIBNVDIMM diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 0407753..2098221 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_OF_PMEM) += of_pmem.o obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c similarity index 100% rename from arch/x86/kernel/pmem.c rename to drivers/nvdimm/pmem_legacy_device.c diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild index 47f9cc9..77aa117 100644 --- a/tools/testing/nvdimm/Kbuild +++ b/tools/testing/nvdimm/Kbuild @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_ACPI_NFIT) += nfit.o ifeq ($(CONFIG_DAX),m) obj-$(CONFIG_DAX) += dax.o -- 2.9.5

1 2

Re: [PATCH OLK-5.10 v5 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by zhuling 21 Jan '22

21 Jan '22

On 2022/1/21 14:25, Kefeng Wang wrote: > Move x86's pmem.c into nvdimm, and rename it pmem_legacy_device.c, > also rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE. > Meanwhile, add PMEM_LEGACY to control the built of nd_e820.o, then > the code could be reused by other architectures. > > Note，this patch fixs the nd_e820.c build introduced by commit 2499317e408e > ("arm64: Revert feature: Add memmap parameter and register pmem"). > > changelog改下；好的，我加下 > > On 2022/1/21 11:20, Zhuling wrote: >> hulk inclusion >> category: feature >> bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I >> >> Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to >> PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of >> nd_e820.o, then the code could be reused by other architectures. >> >> Signed-off-by: Zhuling <zhuling8(a)huawei.com> >> --- >> arch/x86/Kconfig | 6 ++---- >> arch/x86/kernel/Makefile | 1 - >> drivers/nvdimm/Kconfig | 6 ++++++ >> drivers/nvdimm/Makefile | 2 ++ >> arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 >> tools/testing/nvdimm/Kbuild | 2 +- >> 6 files changed, 11 insertions(+), 6 deletions(-) >> rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) >> >> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig >> index c77ef59..1d3176a 100644 >> --- a/arch/x86/Kconfig >> +++ b/arch/x86/Kconfig >> @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE >> default 0 if X86_32 >> default 0xdead000000000000 if X86_64 >> -config X86_PMEM_LEGACY_DEVICE >> - bool >> - >> config X86_PMEM_LEGACY >> tristate "Support non-standard NVDIMMs and ADR protected memory" >> depends on PHYS_ADDR_T_64BIT >> depends on BLK_DEV >> - select X86_PMEM_LEGACY_DEVICE >> + select PMEM_LEGACY >> + select PMEM_LEGACY_DEVICE >> select NUMA_KEEP_MEMINFO if NUMA >> select LIBNVDIMM >> help >> diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile >> index f0606f8..1e12751 100644 >> --- a/arch/x86/kernel/Makefile >> +++ b/arch/x86/kernel/Makefile >> @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o >> obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o >> obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o >> obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o >> -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o >> obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o >> diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig >> index b7d1eb3..632b6ed 100644 >> --- a/drivers/nvdimm/Kconfig >> +++ b/drivers/nvdimm/Kconfig >> @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM >> if LIBNVDIMM >> +config PMEM_LEGACY >> + tristate >> + >> +config PMEM_LEGACY_DEVICE >> + bool >> + >> config BLK_DEV_PMEM >> tristate "PMEM: Persistent memory block device support" >> default LIBNVDIMM >> diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile >> index 0407753..2098221 100644 >> --- a/drivers/nvdimm/Makefile >> +++ b/drivers/nvdimm/Makefile >> @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o >> obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o >> obj-$(CONFIG_ND_BTT) += nd_btt.o >> obj-$(CONFIG_ND_BLK) += nd_blk.o >> +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o >> +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o >> obj-$(CONFIG_OF_PMEM) += of_pmem.o >> obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o >> diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c >> similarity index 100% >> rename from arch/x86/kernel/pmem.c >> rename to drivers/nvdimm/pmem_legacy_device.c >> diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild >> index 47f9cc9..77aa117 100644 >> --- a/tools/testing/nvdimm/Kbuild >> +++ b/tools/testing/nvdimm/Kbuild >> @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o >> obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o >> obj-$(CONFIG_ND_BTT) += nd_btt.o >> obj-$(CONFIG_ND_BLK) += nd_blk.o >> -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o >> +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o >> obj-$(CONFIG_ACPI_NFIT) += nfit.o >> ifeq ($(CONFIG_DAX),m) >> obj-$(CONFIG_DAX) += dax.o > .

1 0

[PATCH OLK-5.10 v5 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by Zhuling 21 Jan '22

21 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of nd_e820.o, then the code could be reused by other architectures. Signed-off-by: Zhuling <zhuling8(a)huawei.com> --- arch/x86/Kconfig | 6 ++---- arch/x86/kernel/Makefile | 1 - drivers/nvdimm/Kconfig | 6 ++++++ drivers/nvdimm/Makefile | 2 ++ arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 tools/testing/nvdimm/Kbuild | 2 +- 6 files changed, 11 insertions(+), 6 deletions(-) rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c77ef59..1d3176a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE default 0 if X86_32 default 0xdead000000000000 if X86_64 -config X86_PMEM_LEGACY_DEVICE - bool - config X86_PMEM_LEGACY tristate "Support non-standard NVDIMMs and ADR protected memory" depends on PHYS_ADDR_T_64BIT depends on BLK_DEV - select X86_PMEM_LEGACY_DEVICE + select PMEM_LEGACY + select PMEM_LEGACY_DEVICE select NUMA_KEEP_MEMINFO if NUMA select LIBNVDIMM help diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f0606f8..1e12751 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index b7d1eb3..632b6ed 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM if LIBNVDIMM +config PMEM_LEGACY + tristate + +config PMEM_LEGACY_DEVICE + bool + config BLK_DEV_PMEM tristate "PMEM: Persistent memory block device support" default LIBNVDIMM diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 0407753..2098221 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_OF_PMEM) += of_pmem.o obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c similarity index 100% rename from arch/x86/kernel/pmem.c rename to drivers/nvdimm/pmem_legacy_device.c diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild index 47f9cc9..77aa117 100644 --- a/tools/testing/nvdimm/Kbuild +++ b/tools/testing/nvdimm/Kbuild @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_ACPI_NFIT) += nfit.o ifeq ($(CONFIG_DAX),m) obj-$(CONFIG_DAX) += dax.o -- 2.9.5

1 2

[PATCH openEuler-1.0-LTS] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Laibin Qiu 20 Jan '22

20 Jan '22

phytium inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4RK58 CVE: NA -------------------------------- The system would hang up when the Phytium S2500 communicates with some BMCs after several rounds of transactions, unless we reset the controller timeout counter manually by calling firmware through SMC. Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> #openEuler_contributor Signed-off-by: Laibin Qiu <qiulaibin(a)huawei.com> --- drivers/char/ipmi/ipmi_si_mem_io.c | 117 ++++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 4 deletions(-) diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c index 75583612ab10..73a3d6979eaa 100644 --- a/drivers/char/ipmi/ipmi_si_mem_io.c +++ b/drivers/char/ipmi/ipmi_si_mem_io.c @@ -3,6 +3,105 @@ #include <linux/io.h> #include "ipmi_si.h" +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 +#include <linux/arm-smccc.h> + +#define CTL_RST_FUNC_ID 0xC2000011 + +static void ctl_smc(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3) +{ + struct arm_smccc_res res; + + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); + if (res.a0 != 0) + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", + (int)res.a0, arg2); +} + +static void ctl_timeout_reset(void) +{ + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); +} + +static unsigned char intf_mem_inb_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return readb((io->addr)+(offset * io->regspacing)); +} + +static unsigned char intf_mem_inw_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) + & 0xff; +} + +static unsigned char intf_mem_inl_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) + & 0xff; +} + +static unsigned char mem_inq_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) + & 0xff; +} +#else +#define intf_mem_inb_2500 intf_mem_inb +#define intf_mem_inw_2500 intf_mem_inw +#define intf_mem_inl_2500 intf_mem_inl +#define mem_inq_2500 mem_inq +#endif + +static bool apply_phytium2500_workaround; + +#ifdef CONFIG_ACPI +struct ipmi_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +}; + +static struct ipmi_workaround_oem_info wa_info[] = { + { + .oem_id = "KPSVVJ", + } +}; + +static void ipmi_check_phytium_workaround(void) +{ + struct acpi_table_header tbl; + int i; + + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) + return; + + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) + continue; + + apply_phytium2500_workaround = true; + break; + } +} +#else +static void ipmi_check_phytium_workaround(void) +{ + apply_phytium2500_workaround = false; +} +#endif + static unsigned char intf_mem_inb(const struct si_sm_io *io, unsigned int offset) { @@ -81,26 +180,36 @@ int ipmi_si_mem_setup(struct si_sm_io *io) if (!addr) return -ENODEV; + ipmi_check_phytium_workaround(); + /* * Figure out the actual readb/readw/readl/etc routine to use based * upon the register size. */ switch (io->regsize) { case 1: - io->inputb = intf_mem_inb; + io->inputb = apply_phytium2500_workaround ? + intf_mem_inb_2500 : + intf_mem_inb; io->outputb = intf_mem_outb; break; case 2: - io->inputb = intf_mem_inw; + io->inputb = apply_phytium2500_workaround ? + intf_mem_inw_2500 : + intf_mem_inw; io->outputb = intf_mem_outw; break; case 4: - io->inputb = intf_mem_inl; + io->inputb = apply_phytium2500_workaround ? + intf_mem_inl_2500 : + intf_mem_inl; io->outputb = intf_mem_outl; break; #ifdef readq case 8: - io->inputb = mem_inq; + io->inputb = apply_phytium2500_workaround ? + mem_inq_2500 : + mem_inq; io->outputb = mem_outq; break; #endif -- 2.22.0

1 0

[PATCH openEuler-5.10 01/22] perf vendor events amd: Add Zen3 events
by Zheng Zengkai 20 Jan '22

20 Jan '22

From: Smita Koralahalli <Smita.KoralahalliChannabasappa(a)amd.com> mainline inclusion from mainline-v5.13-rc1 commit da66658638c947cab0fb157289f03698453ff8d5 category: feature feature: milan cpu bugzilla: https://gitee.com/openeuler/kernel/issues/I4OBEH?from=project-issue CVE: NA -------------------------------- Add PMU events for AMD Zen3 processors as documented in the AMD Processor Programming Reference for Family 19h and Model 01h [1]. Below are the events which are new on Zen3: PMCx041 ls_mab_alloc.{all_allocations|hardware_prefetcher_allocations|load_store_allocations} PMCx043 ls_dmnd_fills_from_sys.ext_cache_local PMCx044 ls_any_fills_from_sys.{mem_io_remote|ext_cache_remote|mem_io_local|ext_cache_local|int_cache|lcl_l2} PMCx047 ls_misal_loads.{ma4k|ma64} PMCx059 ls_sw_pf_dc_fills.ext_cache_local PMCx05a ls_hw_pf_dc_fills.ext_cache_local PMCx05f ls_alloc_mab_count PMCx085 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k PMCx0ab de_dis_cops_from_decoder.disp_op_type.{any_integer_dispatch|any_fp_dispatch} PMCx0cc ex_ret_ind_brch_instr PMCx18e ic_tag_hit_miss.{all_instruction_cache_accesses|instruction_cache_miss|instruction_cache_hit} PMCx1c7 ex_ret_msprd_brnch_instr_dir_msmtch PMCx28f op_cache_hit_miss.{all_op_cache_accesses|op_cache_miss|op_cache_hit} Section 2.1.17.2 "Performance Measurement" of "PPR for AMD Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, 2021." lists new metrics. Add them. Preserve the events for Zen3 if they are measurable and non-zero as taken from Zen2 directory even if the PPR of Zen3 [1] omits them. Those events are the following: PMCx000 fpu_pipe_assignment.{total|total0|total1|total2|total3} PMCx004 fp_num_mov_elim_scal_op.{optimized|opt_potential|sse_mov_ops_elim|sse_mov_ops} PMCx02D ls_rdtsc PMCx040 ls_dc_accesses PMCx046 ls_tablewalker.{iside|ic_type1|ic_type0|dside|dc_type1|dc_type0} PMCx061 l2_request_g2.{group1|ls_rd_sized|ls_rd_sized_nc|ic_rd_sized|ic_rd_sized_nc|smc_inval|bus_lock_originator|bus_locks_responses} PMCx062 l2_latency.l2_cycles_waiting_on_fills PMCx063 l2_wcb_req.{wcb_write|wcb_close|zero_byte_store|cl_zero} PMCx06d l2_fill_pending.l2_fill_busy PMCx080 ic_fw32 PMCx081 ic_fw32_miss PMCx086 bp_snp_re_sync PMCx087 ic_fetch_stall.{ic_stall_any|ic_stall_dq_empty|ic_stall_back_pressure} PMCx08a bp_l1_btb_correct PMCx08c ic_cache_inval.{l2_invalidating_probe|fill_invalidated} PMCx099 bp_tlb_rel PMCx0a9 de_dis_uop_queue_empty_di0 PMCx0c7 ex_ret_brn_resync PMCx28a ic_oc_mode_switch.{oc_ic_mode_switch|ic_oc_mode_switch} L3PMCx01 l3_request_g1.caching_l3_cache_accesses L3PMCx06 l3_comb_clstr_state.{other_l3_miss_typs|request_miss} [1] Processor Programming Reference (PPR) for AMD Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, 2021. [2] Processor Programming Reference (PPR) for AMD Family 17h Model 71h, Revision B0 Processors, 56176 Rev 3.06 - Jul 17, 2019. [3] Processor Programming Reference (PPR) for AMD Family 17h Models 01h,08h, Revision B2 Processors, 54945 Rev 3.03 - Jun 14, 2019. All of the PPRs can be found at: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Robert Richter <rrichter(a)amd.com> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa(a)amd.com> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Ian Rogers <irogers(a)google.com> Cc: Ingo Molnar <mingo(a)redhat.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Kim Phillips <kim.phillips(a)amd.com> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Martin Liška <mliska(a)suse.cz> Cc: Michael Petlan <mpetlan(a)redhat.com> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Vijay Thakkar <vijaythakkar(a)me.com> Cc: linux-perf-users(a)vger.kernel.org Link: https://lore.kernel.org/r/20210406215944.113332-5-Smita.KoralahalliChannaba… Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Reviewed-by: Yang Jihong <yangjihong1(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- .../pmu-events/arch/x86/amdzen3/branch.json | 53 +++ .../pmu-events/arch/x86/amdzen3/cache.json | 402 ++++++++++++++++ .../pmu-events/arch/x86/amdzen3/core.json | 137 ++++++ .../arch/x86/amdzen3/data-fabric.json | 98 ++++ .../arch/x86/amdzen3/floating-point.json | 139 ++++++ .../pmu-events/arch/x86/amdzen3/memory.json | 428 ++++++++++++++++++ .../pmu-events/arch/x86/amdzen3/other.json | 103 +++++ .../arch/x86/amdzen3/recommended.json | 214 +++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 9 files changed, 1575 insertions(+), 1 deletion(-) create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/branch.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/core.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/other.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/recommended.json diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/branch.json b/tools/perf/pmu-events/arch/x86/amdzen3/branch.json new file mode 100644 index 000000000000..018a7fe94fb9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/branch.json @@ -0,0 +1,53 @@ +[ + { + "EventName": "bp_l1_btb_correct", + "EventCode": "0x8a", + "BriefDescription": "L1 Branch Prediction Overrides Existing Prediction (speculative)." + }, + { + "EventName": "bp_l2_btb_correct", + "EventCode": "0x8b", + "BriefDescription": "L2 Branch Prediction Overrides Existing Prediction (speculative)." + }, + { + "EventName": "bp_dyn_ind_pred", + "EventCode": "0x8e", + "BriefDescription": "Dynamic Indirect Predictions.", + "PublicDescription": "The number of times a branch used the indirect predictor to make a prediction." + }, + { + "EventName": "bp_de_redirect", + "EventCode": "0x91", + "BriefDescription": "Decode Redirects", + "PublicDescription": "The number of times the instruction decoder overrides the predicted target." + }, + { + "EventName": "bp_l1_tlb_fetch_hit", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.", + "UMask": "0xff" + }, + { + "EventName": "bp_l1_tlb_fetch_hit.if1g", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size).", + "UMask": "0x04" + }, + { + "EventName": "bp_l1_tlb_fetch_hit.if2m", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size).", + "UMask": "0x02" + }, + { + "EventName": "bp_l1_tlb_fetch_hit.if4k", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size).", + "UMask": "0x01" + }, + { + "EventName": "bp_tlb_rel", + "EventCode": "0x99", + "BriefDescription": "The number of ITLB reload requests." + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/cache.json b/tools/perf/pmu-events/arch/x86/amdzen3/cache.json new file mode 100644 index 000000000000..fa1d7499a2e3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/cache.json @@ -0,0 +1,402 @@ +[ + { + "EventName": "l2_request_g1.rd_blk_l", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch).", + "UMask": "0x80" + }, + { + "EventName": "l2_request_g1.rd_blk_x", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", + "UMask": "0x40" + }, + { + "EventName": "l2_request_g1.ls_rd_blk_c_s", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", + "UMask": "0x20" + }, + { + "EventName": "l2_request_g1.cacheable_ic_read", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", + "UMask": "0x10" + }, + { + "EventName": "l2_request_g1.change_to_x", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state.", + "UMask": "0x08" + }, + { + "EventName": "l2_request_g1.prefetch_l2_cmd", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", + "UMask": "0x04" + }, + { + "EventName": "l2_request_g1.l2_hw_pf", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event.", + "UMask": "0x02" + }, + { + "EventName": "l2_request_g1.group2", + "EventCode": "0x60", + "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).", + "UMask": "0x01" + }, + { + "EventName": "l2_request_g1.all_no_prefetch", + "EventCode": "0x60", + "UMask": "0xf9" + }, + { + "EventName": "l2_request_g2.group1", + "EventCode": "0x61", + "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g1 (PMCx060).", + "UMask": "0x80" + }, + { + "EventName": "l2_request_g2.ls_rd_sized", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", + "UMask": "0x40" + }, + { + "EventName": "l2_request_g2.ls_rd_sized_nc", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", + "UMask": "0x20" + }, + { + "EventName": "l2_request_g2.ic_rd_sized", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", + "UMask": "0x10" + }, + { + "EventName": "l2_request_g2.ic_rd_sized_nc", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", + "UMask": "0x08" + }, + { + "EventName": "l2_request_g2.smc_inval", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.", + "UMask": "0x04" + }, + { + "EventName": "l2_request_g2.bus_locks_originator", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.", + "UMask": "0x02" + }, + { + "EventName": "l2_request_g2.bus_locks_responses", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.", + "UMask": "0x01" + }, + { + "EventName": "l2_latency.l2_cycles_waiting_on_fills", + "EventCode": "0x62", + "BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.", + "UMask": "0x01" + }, + { + "EventName": "l2_wcb_req.wcb_write", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests.", + "UMask": "0x40" + }, + { + "EventName": "l2_wcb_req.wcb_close", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests.", + "UMask": "0x20" + }, + { + "EventName": "l2_wcb_req.zero_byte_store", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests.", + "UMask": "0x04" + }, + { + "EventName": "l2_wcb_req.cl_zero", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests.", + "UMask": "0x01" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_cs", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", + "UMask": "0x80" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable.", + "UMask": "0x40" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2.", + "UMask": "0x20" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_x", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", + "UMask": "0x10" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_c", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses instead.", + "UMask": "0x08" + }, + { + "EventName": "l2_cache_req_stat.ic_fill_hit_x", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2.", + "UMask": "0x04" + }, + { + "EventName": "l2_cache_req_stat.ic_fill_hit_s", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2.", + "UMask": "0x02" + }, + { + "EventName": "l2_cache_req_stat.ic_fill_miss", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss instead.", + "UMask": "0x01" + }, + { + "EventName": "l2_cache_req_stat.ic_access_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.", + "UMask": "0x07" + }, + { + "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).", + "UMask": "0x09" + }, + { + "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).", + "UMask": "0xf6" + }, + { + "EventName": "l2_fill_pending.l2_fill_busy", + "EventCode": "0x6d", + "BriefDescription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2.", + "UMask": "0x01" + }, + { + "EventName": "l2_pf_hit_l2", + "EventCode": "0x70", + "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_hit_l3", + "EventCode": "0x71", + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_l3", + "EventCode": "0x72", + "BriefDescription": "L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.", + "UMask": "0xff" + }, + { + "EventName": "ic_fw32", + "EventCode": "0x80", + "BriefDescription": "The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)." + }, + { + "EventName": "ic_fw32_miss", + "EventCode": "0x81", + "BriefDescription": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag." + }, + { + "EventName": "ic_cache_fill_l2", + "EventCode": "0x82", + "BriefDescription": "Instruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cache." + }, + { + "EventName": "ic_cache_fill_sys", + "EventCode": "0x83", + "BriefDescription": "Instruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cache." + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_hit", + "EventCode": "0x84", + "BriefDescription": "L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB." + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss", + "EventCode": "0x85", + "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs.", + "UMask": "0xff" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced page.", + "UMask": "0x08" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G page.", + "UMask": "0x04" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M page.", + "UMask": "0x02" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K page.", + "UMask": "0x01" + }, + { + "EventName": "bp_snp_re_sync", + "EventCode": "0x86", + "BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event." + }, + { + "EventName": "ic_fetch_stall.ic_stall_any", + "EventCode": "0x87", + "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).", + "UMask": "0x04" + }, + { + "EventName": "ic_fetch_stall.ic_stall_dq_empty", + "EventCode": "0x87", + "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.", + "UMask": "0x02" + }, + { + "EventName": "ic_fetch_stall.ic_stall_back_pressure", + "EventCode": "0x87", + "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", + "UMask": "0x01" + }, + { + "EventName": "ic_cache_inval.l2_invalidating_probe", + "EventCode": "0x8c", + "BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.", + "UMask": "0x02" + }, + { + "EventName": "ic_cache_inval.fill_invalidated", + "EventCode": "0x8c", + "BriefDescription": "IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.", + "UMask": "0x01" + }, + { + "EventName": "ic_tag_hit_miss.all_instruction_cache_accesses", + "EventCode": "0x18e", + "BriefDescription": "All Instruction Cache Accesses. Counts various IC tag related hit and miss events.", + "UMask": "0x1f" + }, + { + "EventName": "ic_tag_hit_miss.instruction_cache_miss", + "EventCode": "0x18e", + "BriefDescription": "Instruction Cache Miss. Counts various IC tag related hit and miss events.", + "UMask": "0x18" + }, + { + "EventName": "ic_tag_hit_miss.instruction_cache_hit", + "EventCode": "0x18e", + "BriefDescription": "Instruction Cache Hit. Counts various IC tag related hit and miss events.", + "UMask": "0x07" + }, + { + "EventName": "ic_oc_mode_switch.oc_ic_mode_switch", + "EventCode": "0x28a", + "BriefDescription": "OC Mode Switch. OC to IC mode switch.", + "UMask": "0x02" + }, + { + "EventName": "ic_oc_mode_switch.ic_oc_mode_switch", + "EventCode": "0x28a", + "BriefDescription": "OC Mode Switch. IC to OC mode switch.", + "UMask": "0x01" + }, + { + "EventName": "op_cache_hit_miss.all_op_cache_accesses", + "EventCode": "0x28f", + "BriefDescription": "All Op Cache accesses. Counts Op Cache micro-tag hit/miss events", + "UMask": "0x07" + }, + { + "EventName": "op_cache_hit_miss.op_cache_miss", + "EventCode": "0x28f", + "BriefDescription": "Op Cache Miss. Counts Op Cache micro-tag hit/miss events", + "UMask": "0x04" + }, + { + "EventName": "op_cache_hit_miss.op_cache_hit", + "EventCode": "0x28f", + "BriefDescription": "Op Cache Hit. Counts Op Cache micro-tag hit/miss events", + "UMask": "0x03" + }, + { + "EventName": "l3_request_g1.caching_l3_cache_accesses", + "EventCode": "0x01", + "BriefDescription": "Caching: L3 cache accesses", + "UMask": "0x80", + "Unit": "L3PMC" + }, + { + "EventName": "l3_lookup_state.all_l3_req_typs", + "EventCode": "0x04", + "BriefDescription": "All L3 Request Types. All L3 cache Requests", + "UMask": "0xff", + "Unit": "L3PMC" + }, + { + "EventName": "l3_comb_clstr_state.other_l3_miss_typs", + "EventCode": "0x06", + "BriefDescription": "Other L3 Miss Request Types", + "UMask": "0xfe", + "Unit": "L3PMC" + }, + { + "EventName": "l3_comb_clstr_state.request_miss", + "EventCode": "0x06", + "BriefDescription": "L3 cache misses", + "UMask": "0x01", + "Unit": "L3PMC" + }, + { + "EventName": "xi_sys_fill_latency", + "EventCode": "0x90", + "BriefDescription": "L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask.", + "Unit": "L3PMC" + }, + { + "EventName": "xi_ccx_sdp_req1", + "EventCode": "0x9a", + "BriefDescription": "L3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting.", + "UMask": "0xff", + "Unit": "L3PMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/core.json b/tools/perf/pmu-events/arch/x86/amdzen3/core.json new file mode 100644 index 000000000000..4e27a2be359e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/core.json @@ -0,0 +1,137 @@ +[ + { + "EventName": "ex_ret_instr", + "EventCode": "0xc0", + "BriefDescription": "Retired Instructions." + }, + { + "EventName": "ex_ret_ops", + "EventCode": "0xc1", + "BriefDescription": "Retired Ops. Use macro_ops_retired instead.", + "PublicDescription": "The number of macro-ops retired." + }, + { + "EventName": "ex_ret_brn", + "EventCode": "0xc2", + "BriefDescription": "Retired Branch Instructions.", + "PublicDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts." + }, + { + "EventName": "ex_ret_brn_misp", + "EventCode": "0xc3", + "BriefDescription": "Retired Branch Instructions Mispredicted.", + "PublicDescription": "The number of retired branch instructions, that were mispredicted." + }, + { + "EventName": "ex_ret_brn_tkn", + "EventCode": "0xc4", + "BriefDescription": "Retired Taken Branch Instructions.", + "PublicDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts." + }, + { + "EventName": "ex_ret_brn_tkn_misp", + "EventCode": "0xc5", + "BriefDescription": "Retired Taken Branch Instructions Mispredicted.", + "PublicDescription": "The number of retired taken branch instructions that were mispredicted." + }, + { + "EventName": "ex_ret_brn_far", + "EventCode": "0xc6", + "BriefDescription": "Retired Far Control Transfers.", + "PublicDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction." + }, + { + "EventName": "ex_ret_brn_resync", + "EventCode": "0xc7", + "BriefDescription": "Retired Branch Resyncs.", + "PublicDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare." + }, + { + "EventName": "ex_ret_near_ret", + "EventCode": "0xc8", + "BriefDescription": "Retired Near Returns.", + "PublicDescription": "The number of near return instructions (RET or RET Iw) retired." + }, + { + "EventName": "ex_ret_near_ret_mispred", + "EventCode": "0xc9", + "BriefDescription": "Retired Near Returns Mispredicted.", + "PublicDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction." + }, + { + "EventName": "ex_ret_brn_ind_misp", + "EventCode": "0xca", + "BriefDescription": "Retired Indirect Branch Instructions Mispredicted.", + "PublicDescription": "The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted." + }, + { + "EventName": "ex_ret_mmx_fp_instr.sse_instr", + "EventCode": "0xcb", + "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).", + "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS.", + "UMask": "0x04" + }, + { + "EventName": "ex_ret_mmx_fp_instr.mmx_instr", + "EventCode": "0xcb", + "BriefDescription": "MMX instructions.", + "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.", + "UMask": "0x02" + }, + { + "EventName": "ex_ret_mmx_fp_instr.x87_instr", + "EventCode": "0xcb", + "BriefDescription": "x87 instructions.", + "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.", + "UMask": "0x01" + }, + { + "EventName": "ex_ret_ind_brch_instr", + "EventCode": "0xcc", + "BriefDescription": "Retired Indirect Branch Instructions. The number of indirect branches retired." + }, + { + "EventName": "ex_ret_cond", + "EventCode": "0xd1", + "BriefDescription": "Retired Conditional Branch Instructions." + }, + { + "EventName": "ex_div_busy", + "EventCode": "0xd3", + "BriefDescription": "Div Cycles Busy count." + }, + { + "EventName": "ex_div_count", + "EventCode": "0xd4", + "BriefDescription": "Div Op Count." + }, + { + "EventName": "ex_ret_msprd_brnch_instr_dir_msmtch", + "EventCode": "0x1c7", + "BriefDescription": "Retired Mispredicted Branch Instructions due to Direction Mismatch", + "PublicDescription": "The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch." + }, + { + "EventName": "ex_tagged_ibs_ops.ibs_count_rollover", + "EventCode": "0x1cf", + "BriefDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.", + "UMask": "0x04" + }, + { + "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret", + "EventCode": "0x1cf", + "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.", + "UMask": "0x02" + }, + { + "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops", + "EventCode": "0x1cf", + "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.", + "UMask": "0x01" + }, + { + "EventName": "ex_ret_fused_instr", + "EventCode": "0x1d0", + "BriefDescription": "Counts retired Fused Instructions." + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json b/tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json new file mode 100644 index 000000000000..40271df40015 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json @@ -0,0 +1,98 @@ +[ + { + "EventName": "remote_outbound_data_controller_0", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0", + "EventCode": "0x7c7", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "remote_outbound_data_controller_1", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1", + "EventCode": "0x807", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "remote_outbound_data_controller_2", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2", + "EventCode": "0x847", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "remote_outbound_data_controller_3", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3", + "EventCode": "0x887", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_0", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x07", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_1", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x47", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_2", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x87", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_3", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0xc7", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_4", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x107", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_5", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x147", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_6", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x187", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_7", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x1c7", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json b/tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json new file mode 100644 index 000000000000..98cfcb9c78ec --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json @@ -0,0 +1,139 @@ +[ + { + "EventName": "fpu_pipe_assignment.total", + "EventCode": "0x00", + "BriefDescription": "Total number of fp uOps.", + "PublicDescription": "Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS.", + "UMask": "0x0f" + }, + { + "EventName": "fpu_pipe_assignment.total3", + "EventCode": "0x00", + "BriefDescription": "Total number uOps assigned to pipe 3.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3.", + "UMask": "0x08" + }, + { + "EventName": "fpu_pipe_assignment.total2", + "EventCode": "0x00", + "BriefDescription": "Total number uOps assigned to pipe 2.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2.", + "UMask": "0x04" + }, + { + "EventName": "fpu_pipe_assignment.total1", + "EventCode": "0x00", + "BriefDescription": "Total number uOps assigned to pipe 1.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1.", + "UMask": "0x02" + }, + { + "EventName": "fpu_pipe_assignment.total0", + "EventCode": "0x00", + "BriefDescription": "Total number of fp uOps on pipe 0.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0.", + "UMask": "0x01" + }, + { + "EventName": "fp_ret_sse_avx_ops.all", + "EventCode": "0x03", + "BriefDescription": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.", + "UMask": "0xff" + }, + { + "EventName": "fp_ret_sse_avx_ops.mac_flops", + "EventCode": "0x03", + "BriefDescription": "Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x08" + }, + { + "EventName": "fp_ret_sse_avx_ops.div_flops", + "EventCode": "0x03", + "BriefDescription": "Divide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x04" + }, + { + "EventName": "fp_ret_sse_avx_ops.mult_flops", + "EventCode": "0x03", + "BriefDescription": "Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x02" + }, + { + "EventName": "fp_ret_sse_avx_ops.add_sub_flops", + "EventCode": "0x03", + "BriefDescription": "Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x01" + }, + { + "EventName": "fp_num_mov_elim_scal_op.optimized", + "EventCode": "0x04", + "BriefDescription": "Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x08" + }, + { + "EventName": "fp_num_mov_elim_scal_op.opt_potential", + "EventCode": "0x04", + "BriefDescription": "Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x04" + }, + { + "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops_elim", + "EventCode": "0x04", + "BriefDescription": "Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x02" + }, + { + "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops", + "EventCode": "0x04", + "BriefDescription": "Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x01" + }, + { + "EventName": "fp_retired_ser_ops.sse_bot_ret", + "EventCode": "0x05", + "BriefDescription": "SSE/AVX bottom-executing ops retired. The number of serializing Ops retired.", + "UMask": "0x08" + }, + { + "EventName": "fp_retired_ser_ops.sse_ctrl_ret", + "EventCode": "0x05", + "BriefDescription": "SSE/AVX control word mispredict traps. The number of serializing Ops retired.", + "UMask": "0x04" + }, + { + "EventName": "fp_retired_ser_ops.x87_bot_ret", + "EventCode": "0x05", + "BriefDescription": "x87 bottom-executing ops retired. The number of serializing Ops retired.", + "UMask": "0x02" + }, + { + "EventName": "fp_retired_ser_ops.x87_ctrl_ret", + "EventCode": "0x05", + "BriefDescription": "x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired.", + "UMask": "0x01" + }, + { + "EventName": "fp_disp_faults.ymm_spill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. YMM spill fault.", + "UMask": "0x08" + }, + { + "EventName": "fp_disp_faults.ymm_fill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. YMM fill fault.", + "UMask": "0x04" + }, + { + "EventName": "fp_disp_faults.xmm_fill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. XMM fill fault.", + "UMask": "0x02" + }, + { + "EventName": "fp_disp_faults.x87_fill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. x87 fill fault.", + "UMask": "0x01" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/memory.json b/tools/perf/pmu-events/arch/x86/amdzen3/memory.json new file mode 100644 index 000000000000..a2833955dcd2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/memory.json @@ -0,0 +1,428 @@ +[ + { + "EventName": "ls_bad_status2.stli_other", + "EventCode": "0x24", + "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.", + "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.", + "UMask": "0x02" + }, + { + "EventName": "ls_locks.spec_lock_hi_spec", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.", + "UMask": "0x08" + }, + { + "EventName": "ls_locks.spec_lock_lo_spec", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.", + "UMask": "0x04" + }, + { + "EventName": "ls_locks.non_spec_lock", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", + "UMask": "0x02" + }, + { + "EventName": "ls_locks.bus_lock", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. Comparable to legacy bus lock.", + "UMask": "0x01" + }, + { + "EventName": "ls_ret_cl_flush", + "EventCode": "0x26", + "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." + }, + { + "EventName": "ls_ret_cpuid", + "EventCode": "0x27", + "BriefDescription": "The number of CPUID instructions retired." + }, + { + "EventName": "ls_dispatch.ld_st_dispatch", + "EventCode": "0x29", + "BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", + "UMask": "0x04" + }, + { + "EventName": "ls_dispatch.store_dispatch", + "EventCode": "0x29", + "BriefDescription": "Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", + "UMask": "0x02" + }, + { + "EventName": "ls_dispatch.ld_dispatch", + "EventCode": "0x29", + "BriefDescription": "Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", + "UMask": "0x01" + }, + { + "EventName": "ls_smi_rx", + "EventCode": "0x2b", + "BriefDescription": "Counts the number of SMIs received." + }, + { + "EventName": "ls_int_taken", + "EventCode": "0x2c", + "BriefDescription": "Counts the number of interrupts taken." + }, + { + "EventName": "ls_rdtsc", + "EventCode": "0x2d", + "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative." + }, + { + "EventName": "ls_stlf", + "EventCode": "0x35", + "BriefDescription": "Number of STLF hits." + }, + { + "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full", + "EventCode": "0x37", + "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", + "UMask": "0x01" + }, + { + "EventName": "ls_dc_accesses", + "EventCode": "0x40", + "BriefDescription": "Number of accesses to the dcache for load/store references.", + "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event." + }, + { + "EventName": "ls_mab_alloc.all_allocations", + "EventCode": "0x41", + "BriefDescription": "All Allocations. Counts when a LS pipe allocates a MAB entry.", + "UMask": "0x7f" + }, + { + "EventName": "ls_mab_alloc.hardware_prefetcher_allocations", + "EventCode": "0x41", + "BriefDescription": "Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry.", + "UMask": "0x40" + }, + { + "EventName": "ls_mab_alloc.load_store_allocations", + "EventCode": "0x41", + "BriefDescription": "Load Store Allocations. Counts when a LS pipe allocates a MAB entry.", + "UMask": "0x3f" + }, + { + "EventName": "ls_mab_alloc.dc_prefetcher", + "EventCode": "0x41", + "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.", + "UMask": "0x08" + }, + { + "EventName": "ls_mab_alloc.stores", + "EventCode": "0x41", + "BriefDescription": "LS MAB Allocates by Type. Stores.", + "UMask": "0x02" + }, + { + "EventName": "ls_mab_alloc.loads", + "EventCode": "0x41", + "BriefDescription": "LS MAB Allocates by Type. Loads.", + "UMask": "0x01" + }, + { + "EventName": "ls_dmnd_fills_from_sys.mem_io_remote", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_dmnd_fills_from_sys.ext_cache_remote", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_dmnd_fills_from_sys.mem_io_local", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_dmnd_fills_from_sys.ext_cache_local", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_dmnd_fills_from_sys.int_cache", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_dmnd_fills_from_sys.lcl_l2", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_any_fills_from_sys.mem_io_remote", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_any_fills_from_sys.ext_cache_remote", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_any_fills_from_sys.mem_io_local", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_any_fills_from_sys.ext_cache_local", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_any_fills_from_sys.int_cache", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_any_fills_from_sys.lcl_l2", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_l1_d_tlb_miss.all", + "EventCode": "0x45", + "BriefDescription": "All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead.", + "UMask": "0xff" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB.", + "UMask": "0x80" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB.", + "UMask": "0x40" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB.", + "UMask": "0x20" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB.", + "UMask": "0x10" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.", + "UMask": "0x08" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.", + "UMask": "0x04" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB.", + "UMask": "0x02" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.", + "UMask": "0x01" + }, + { + "EventName": "ls_tablewalker.iside", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks on I-side.", + "UMask": "0x0c" + }, + { + "EventName": "ls_tablewalker.ic_type1", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks IC Type 1.", + "UMask": "0x08" + }, + { + "EventName": "ls_tablewalker.ic_type0", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks IC Type 0.", + "UMask": "0x04" + }, + { + "EventName": "ls_tablewalker.dside", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks on D-side.", + "UMask": "0x03" + }, + { + "EventName": "ls_tablewalker.dc_type1", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks DC Type 1.", + "UMask": "0x02" + }, + { + "EventName": "ls_tablewalker.dc_type0", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks DC Type 0.", + "UMask": "0x01" + }, + { + "EventName": "ls_misal_loads.ma4k", + "EventCode": "0x47", + "BriefDescription": "The number of 4KB misaligned (i.e., page crossing) loads.", + "UMask": "0x02" + }, + { + "EventName": "ls_misal_loads.ma64", + "EventCode": "0x47", + "BriefDescription": "The number of 64B misaligned (i.e., cacheline crossing) loads.", + "UMask": "0x01" + }, + { + "EventName": "ls_pref_instr_disp", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).", + "UMask": "0xff" + }, + { + "EventName": "ls_pref_instr_disp.prefetch_nta", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.", + "UMask": "0x04" + }, + { + "EventName": "ls_pref_instr_disp.prefetch_w", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW.", + "UMask": "0x02" + }, + { + "EventName": "ls_pref_instr_disp.prefetch", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.", + "UMask": "0x01" + }, + { + "EventName": "ls_inef_sw_pref.mab_mch_cnt", + "EventCode": "0x52", + "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.", + "UMask": "0x02" + }, + { + "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit", + "EventCode": "0x52", + "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.", + "UMask": "0x01" + }, + { + "EventName": "ls_sw_pf_dc_fills.mem_io_remote", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_sw_pf_dc_fills.ext_cache_remote", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_sw_pf_dc_fills.mem_io_local", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_sw_pf_dc_fills.ext_cache_local", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_sw_pf_dc_fills.int_cache", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_sw_pf_dc_fills.lcl_l2", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_hw_pf_dc_fills.mem_io_remote", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_hw_pf_dc_fills.ext_cache_remote", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_hw_pf_dc_fills.mem_io_local", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_hw_pf_dc_fills.ext_cache_local", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_hw_pf_dc_fills.int_cache", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_hw_pf_dc_fills.lcl_l2", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_alloc_mab_count", + "EventCode": "0x5f", + "BriefDescription": "Count of Allocated Mabs", + "PublicDescription": "This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]." + }, + { + "EventName": "ls_not_halted_cyc", + "EventCode": "0x76", + "BriefDescription": "Cycles not in Halt." + }, + { + "EventName": "ls_tlb_flush.all_tlb_flushes", + "EventCode": "0x78", + "BriefDescription": "All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead", + "UMask": "0xff" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/other.json b/tools/perf/pmu-events/arch/x86/amdzen3/other.json new file mode 100644 index 000000000000..7da5d0791ea3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/other.json @@ -0,0 +1,103 @@ +[ + { + "EventName": "de_dis_uop_queue_empty_di0", + "EventCode": "0xa9", + "BriefDescription": "Cycles where the Micro-Op Queue is empty." + }, + { + "EventName": "de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch", + "EventCode": "0xab", + "BriefDescription": "Any Integer dispatch. Types of Oops Dispatched from Decoder.", + "UMask": "0x08" + }, + { + "EventName": "de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch", + "EventCode": "0xab", + "BriefDescription": "Any FP dispatch. Types of Oops Dispatched from Decoder.", + "UMask": "0x04" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.fp_flush_recovery_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stall.", + "UMask": "0x80" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP scheduler.", + "UMask": "0x40" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination register.", + "UMask": "0x20" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stall.", + "UMask": "0x10" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.int_sched_misc_token_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall.", + "UMask": "0x08" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.store_queue_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semantics.", + "UMask": "0x04" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.load_queue_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semantics.", + "UMask": "0x02" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register.", + "UMask": "0x01" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.retire_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens available.", + "UMask": "0x20" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.agsq_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.", + "UMask": "0x10" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch3_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 available.", + "UMask": "0x08" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch2_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 available.", + "UMask": "0x04" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch1_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 available.", + "UMask": "0x02" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch0_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 available.", + "UMask": "0x01" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/recommended.json b/tools/perf/pmu-events/arch/x86/amdzen3/recommended.json new file mode 100644 index 000000000000..988cf68ae825 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/recommended.json @@ -0,0 +1,214 @@ +[ + { + "MetricName": "branch_misprediction_ratio", + "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", + "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)", + "MetricGroup": "branch_prediction", + "ScaleUnit": "100%" + }, + { + "EventName": "all_data_cache_accesses", + "EventCode": "0x29", + "BriefDescription": "All L1 Data Cache Accesses", + "UMask": "0x07" + }, + { + "MetricName": "all_l2_cache_accesses", + "BriefDescription": "All L2 Cache Accesses", + "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "EventName": "l2_cache_accesses_from_ic_misses", + "EventCode": "0x60", + "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", + "UMask": "0x10" + }, + { + "EventName": "l2_cache_accesses_from_dc_misses", + "EventCode": "0x60", + "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", + "UMask": "0xe8" + }, + { + "MetricName": "l2_cache_accesses_from_l2_hwpf", + "BriefDescription": "L2 Cache Accesses from L2 HWPF", + "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "MetricName": "all_l2_cache_misses", + "BriefDescription": "All L2 Cache Misses", + "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "EventName": "l2_cache_misses_from_ic_miss", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", + "UMask": "0x01" + }, + { + "EventName": "l2_cache_misses_from_dc_misses", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", + "UMask": "0x08" + }, + { + "MetricName": "l2_cache_misses_from_l2_hwpf", + "BriefDescription": "L2 Cache Misses from L2 Cache HWPF", + "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "MetricName": "all_l2_cache_hits", + "BriefDescription": "All L2 Cache Hits", + "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2", + "MetricGroup": "l2_cache" + }, + { + "EventName": "l2_cache_hits_from_ic_misses", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", + "UMask": "0x06" + }, + { + "EventName": "l2_cache_hits_from_dc_misses", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", + "UMask": "0xf0" + }, + { + "EventName": "l2_cache_hits_from_l2_hwpf", + "EventCode": "0x70", + "BriefDescription": "L2 Cache Hits from L2 Cache HWPF", + "UMask": "0xff" + }, + { + "EventName": "l3_cache_accesses", + "EventCode": "0x04", + "BriefDescription": "L3 Cache Accesses", + "UMask": "0xff", + "Unit": "L3PMC" + }, + { + "EventName": "l3_misses", + "EventCode": "0x04", + "BriefDescription": "L3 Misses (includes cacheline state change requests)", + "UMask": "0x01", + "Unit": "L3PMC" + }, + { + "MetricName": "l3_read_miss_latency", + "BriefDescription": "Average L3 Read Miss Latency (in core clocks)", + "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1", + "MetricGroup": "l3_cache", + "ScaleUnit": "1core clocks" + }, + { + "MetricName": "op_cache_fetch_miss_ratio", + "BriefDescription": "Op Cache (64B) Fetch Miss Ratio", + "MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)", + "MetricGroup": "l2_cache" + }, + { + "MetricName": "ic_fetch_miss_ratio", + "BriefDescription": "Instruction Cache (32B) Fetch Miss Ratio", + "MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)", + "MetricGroup": "l2_cache", + "ScaleUnit": "100%" + }, + { + "EventName": "l1_data_cache_fills_from_memory", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From Memory", + "UMask": "0x48" + }, + { + "EventName": "l1_data_cache_fills_from_remote_node", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From Remote Node", + "UMask": "0x50" + }, + { + "EventName": "l1_data_cache_fills_from_within_same_ccx", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From within same CCX", + "UMask": "0x03" + }, + { + "EventName": "l1_data_cache_fills_from_external_ccx_cache", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From External CCX Cache", + "UMask": "0x14" + }, + { + "EventName": "l1_data_cache_fills_all", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: All", + "UMask": "0xff" + }, + { + "MetricName": "l1_itlb_misses", + "BriefDescription": "L1 ITLB Misses", + "MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss", + "MetricGroup": "tlb" + }, + { + "EventName": "l2_itlb_misses", + "EventCode": "0x85", + "BriefDescription": "L2 ITLB Misses & Instruction page walks", + "UMask": "0x07" + }, + { + "EventName": "l1_dtlb_misses", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Misses", + "UMask": "0xff" + }, + { + "EventName": "l2_dtlb_misses", + "EventCode": "0x45", + "BriefDescription": "L2 DTLB Misses & Data page walks", + "UMask": "0xf0" + }, + { + "EventName": "all_tlbs_flushed", + "EventCode": "0x78", + "BriefDescription": "All TLBs Flushed", + "UMask": "0xff" + }, + { + "MetricName": "macro_ops_dispatched", + "BriefDescription": "Macro-ops Dispatched", + "MetricExpr": "de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch", + "MetricGroup": "decoder" + }, + { + "EventName": "sse_avx_stalls", + "EventCode": "0x0e", + "BriefDescription": "Mixed SSE/AVX Stalls", + "UMask": "0x0e" + }, + { + "EventName": "macro_ops_retired", + "EventCode": "0xc1", + "BriefDescription": "Macro-ops Retired" + }, + { + "MetricName": "all_remote_links_outbound", + "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)", + "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3", + "MetricGroup": "data_fabric", + "PerPkg": "1", + "ScaleUnit": "3e-5MiB" + }, + { + "MetricName": "nps1_die_to_dram", + "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)", + "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7", + "MetricGroup": "data_fabric", + "PerPkg": "1", + "ScaleUnit": "6.1e-5MiB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 2f2a209e87e1..9f97b32533a0 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -38,4 +38,4 @@ GenuineIntel-6-7E,v1,icelake,core GenuineIntel-6-86,v1,tremontx,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core -AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen2,core +AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core -- 2.20.1

1 21

Re: [PATCH] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by QiuLaibin 20 Jan '22

20 Jan '22

您好，您的补丁已经提交 CI 进行检查。后续合入进展可以在以下issue下关注 https://gitee.com/openeuler/kernel/issues/I4RK58 谢谢 BR Laibin On 2022/1/20 10:35, Chen Baozi wrote: > phytium inclusion > category: bugfix > bugzilla: NA > CVE: NA > > -------------------------------- > > The system would hang up when the Phytium S2500 communicates with > some BMCs after several rounds of transactions, unless we reset > the controller timeout counter manually by calling firmware through > SMC. > > Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> > Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> > --- > drivers/char/ipmi/ipmi_si_mem_io.c | 117 ++++++++++++++++++++++++++++- > 1 file changed, 113 insertions(+), 4 deletions(-) > > diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c > index 75583612ab10..73a3d6979eaa 100644 > --- a/drivers/char/ipmi/ipmi_si_mem_io.c > +++ b/drivers/char/ipmi/ipmi_si_mem_io.c > @@ -3,6 +3,105 @@ > #include <linux/io.h> > #include "ipmi_si.h" > > +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 > +#include <linux/arm-smccc.h> > + > +#define CTL_RST_FUNC_ID 0xC2000011 > + > +static void ctl_smc(unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); > + if (res.a0 != 0) > + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", > + (int)res.a0, arg2); > +} > + > +static void ctl_timeout_reset(void) > +{ > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); > +} > + > +static unsigned char intf_mem_inb_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return readb((io->addr)+(offset * io->regspacing)); > +} > + > +static unsigned char intf_mem_inw_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char intf_mem_inl_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char mem_inq_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > +#else > +#define intf_mem_inb_2500 intf_mem_inb > +#define intf_mem_inw_2500 intf_mem_inw > +#define intf_mem_inl_2500 intf_mem_inl > +#define mem_inq_2500 mem_inq > +#endif > + > +static bool apply_phytium2500_workaround; > + > +#ifdef CONFIG_ACPI > +struct ipmi_workaround_oem_info { > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > +}; > + > +static struct ipmi_workaround_oem_info wa_info[] = { > + { > + .oem_id = "KPSVVJ", > + } > +}; > + > +static void ipmi_check_phytium_workaround(void) > +{ > + struct acpi_table_header tbl; > + int i; > + > + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) > + return; > + > + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { > + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) > + continue; > + > + apply_phytium2500_workaround = true; > + break; > + } > +} > +#else > +static void ipmi_check_phytium_workaround(void) > +{ > + apply_phytium2500_workaround = false; > +} > +#endif > + > static unsigned char intf_mem_inb(const struct si_sm_io *io, > unsigned int offset) > { > @@ -81,26 +180,36 @@ int ipmi_si_mem_setup(struct si_sm_io *io) > if (!addr) > return -ENODEV; > > + ipmi_check_phytium_workaround(); > + > /* > * Figure out the actual readb/readw/readl/etc routine to use based > * upon the register size. > */ > switch (io->regsize) { > case 1: > - io->inputb = intf_mem_inb; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inb_2500 : > + intf_mem_inb; > io->outputb = intf_mem_outb; > break; > case 2: > - io->inputb = intf_mem_inw; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inw_2500 : > + intf_mem_inw; > io->outputb = intf_mem_outw; > break; > case 4: > - io->inputb = intf_mem_inl; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inl_2500 : > + intf_mem_inl; > io->outputb = intf_mem_outl; > break; > #ifdef readq > case 8: > - io->inputb = mem_inq; > + io->inputb = apply_phytium2500_workaround ? > + mem_inq_2500 : > + mem_inq; > io->outputb = mem_outq; > break; > #endif >

1 0

[PATCH openEuler-1.0-LTS] audit: bugfix for infinite loop when flush the hold queue
by Yang Yingliang 20 Jan '22

20 Jan '22

From: Cui GaoSheng <cuigaosheng1(a)huawei.com> hulk inclusion category: bugfix bugzilla: 186105, https://gitee.com/openeuler/kernel/issues/I4RGWS?from=project-issue CVE: NA ----------------------------------------------------------------- When we add "audit=1" to the cmdline, if we keep the audit_hold_queue non-empty, flush the hold queue will fall into an infinite loop. So we need to fix it by stoping flush the hold queue when netlink abnormal. Fixes: 3413ddc91e02a ("audit: improve robustness of the audit queue handling") Signed-off-by: Cui GaoSheng <cuigaosheng1(a)huawei.com> Reviewed-by: Xiu Jianfeng <xiujianfeng(a)huawei.com> Reviewed-by: weiyang wang <wangweiyang2(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- kernel/audit.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/kernel/audit.c b/kernel/audit.c index c5e034fe14bbb..3de5ebb945592 100644 --- a/kernel/audit.c +++ b/kernel/audit.c @@ -740,6 +740,8 @@ static int kauditd_send_queue(struct sock *sk, u32 portid, if (!sk) { if (err_hook) (*err_hook)(skb); + if (queue == &audit_hold_queue) + goto out; continue; } @@ -756,6 +758,8 @@ static int kauditd_send_queue(struct sock *sk, u32 portid, (*err_hook)(skb); if (rc == -EAGAIN) rc = 0; + if (queue == &audit_hold_queue) + goto out; /* continue to drain the queue */ continue; } else @@ -767,6 +771,7 @@ static int kauditd_send_queue(struct sock *sk, u32 portid, } } +out: return (rc >= 0 ? 0 : rc); } -- 2.25.1

1 0

[PATCH openEuler-1.0-LTS] blk-throttle: enable hierarchical throttle in cgroup v1
by Yang Yingliang 19 Jan '22

19 Jan '22

From: Yu Kuai <yukuai3(a)huawei.com> hulk inclusion category: feature bugzilla: 186072, https://gitee.com/openeuler/kernel/issues/I4RH0V CVE: NA ----------------------------------------------- blkio subsytem is not under default hierarchy in cgroup v1 by default, which means configurations will only be effective on current cgroup for io throttle. This patch introduces a new feature that enable default hierarchy for io throttle, which means configurations will be effective on child cgroups. Such feature is disabled by default, and can be enabled by adding "blkcg_global_limit=1" or "blkcg_global_limit=Y" or "blkcg_global_limit=y" in boot cmd. Signed-off-by: Yu Kuai <yukuai3(a)huawei.com> Reviewed-by: Hou Tao <houtao1(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- block/blk-throttle.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/block/blk-throttle.c b/block/blk-throttle.c index ceeb17104aa82..6b3ced8ae1a5f 100644 --- a/block/blk-throttle.c +++ b/block/blk-throttle.c @@ -43,6 +43,19 @@ static struct blkcg_policy blkcg_policy_throtl; /* A workqueue to queue throttle related work */ static struct workqueue_struct *kthrotld_workqueue; +/* True if global limit is enabled in cgroup v1 */ +static bool global_limit; + +static int __init setup_global_limit(char *str) +{ + if (!strcmp(str, "1") || !strcmp(str, "Y") || !strcmp(str, "y")) + global_limit = true; + + return 1; +} + +__setup("blkcg_global_limit=", setup_global_limit); + /* * To implement hierarchical throttling, throtl_grps form a tree and bios * are dispatched upwards level by level until they reach the top and get @@ -537,7 +550,8 @@ static void throtl_pd_init(struct blkg_policy_data *pd) * regardless of the position of the group in the hierarchy. */ sq->parent_sq = &td->service_queue; - if (cgroup_subsys_on_dfl(io_cgrp_subsys) && blkg->parent) + if ((cgroup_subsys_on_dfl(io_cgrp_subsys) || global_limit) && + blkg->parent) sq->parent_sq = &blkg_to_tg(blkg->parent)->service_queue; tg->td = td; } -- 2.25.1

1 0

[PATCH openEuler-1.0-LTS] xfs: map unwritten blocks in XFS_IOC_{ALLOC,FREE}SP just like fallocate
by Yang Yingliang 19 Jan '22

19 Jan '22

From: "Darrick J. Wong" <djwong(a)kernel.org> mainline inclusion from mainline-v5.16-rc5 commit 983d8e60f50806f90534cc5373d0ce867e5aaf79 category: bugfix bugzilla: 186083 CVE: CVE-2021-4155 Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… -------------------------------- The old ALLOCSP/FREESP ioctls in XFS can be used to preallocate space at the end of files, just like fallocate and RESVSP. Make the behavior consistent with the other ioctls. Reported-by: Kirill Tkhai <ktkhai(a)virtuozzo.com> Signed-off-by: Darrick J. Wong <djwong(a)kernel.org> Signed-off-by: Darrick J. Wong <darrick.wong(a)oracle.com> Reviewed-by: Dave Chinner <dchinner(a)redhat.com> Reviewed-by: Eric Sandeen <sandeen(a)redhat.com> Signed-off-by: Guo Xuenan <guoxuenan(a)huawei.com> Reviewed-by: Zhang Yi <yi.zhang(a)huawei.com> Reviewed-by: Xiu Jianfeng <xiujianfeng(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- fs/xfs/xfs_ioctl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/xfs/xfs_ioctl.c b/fs/xfs/xfs_ioctl.c index 263436977c39e..b6d85da7f3508 100644 --- a/fs/xfs/xfs_ioctl.c +++ b/fs/xfs/xfs_ioctl.c @@ -701,7 +701,8 @@ xfs_ioc_space( flags |= XFS_PREALLOC_CLEAR; if (bf->l_start > XFS_ISIZE(ip)) { error = xfs_alloc_file_space(ip, XFS_ISIZE(ip), - bf->l_start - XFS_ISIZE(ip), 0); + bf->l_start - XFS_ISIZE(ip), + XFS_BMAPI_PREALLOC); if (error) goto out_unlock; } -- 2.25.1

1 0

openEuler 20.03 support AMD Milan
by QiuLaibin 19 Jan '22

19 Jan '22

Hi Liu 感谢您的提交，针对先前提交的AMD适配milan V2相关patch，我们总共有两条意见，麻烦再确认下。 1、Essential下 08ed77e414ab v5.10-rc1 perf vendor events amd: Add recommended events 未合入 2、41cd02c6f7f6：kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID 后向有两个bugfix需要确认 new fix: 36fa06f9ff39 ("KVM: x86: Add support for RDPID without RDTSCP") new fix: 8aec21c04caa ("KVM: VMX: Do not advertise RDPID if ENABLE_RDTSCP control is unsupported") BR Laibin On 2021/12/16 10:27, Jackie Liu wrote: > Hi, ALL > > 附件是加入到 KYLIN 内核的 AMD patch 并且基于欧拉分支 rebase 了一下 > ，head 的创建规则没搞懂，这个脚本好像也不合适，就没有更改。请查收。 > > -- > Jackie Liu > > 在 2021/12/15 上午11:44, Zheng Zengkai 写道: >> #!/bin/sh >> # >> # Usage: >> # >> # prerequisite: >> # The patches to add header should be patches from linux mainline. >> # >> # command: >> # add-openeuler-patch-header.sh commit1..commit2 gitee_issue_url >> # >> # commit1: mainline start commit id; >> # commit2: mainline end commit id >> # gitee_issue_url: for example: >> https://gitee.com/openeuler/kernel/issues/I4MKP4 >> >> # Example: >> # add-openeuler-patch-header.sh afd2ff9b7e1b..8bb7eca972a >> https://gitee.com/openeuler/kernel/issues/I4MKP4 >> # >> >> for p in `ls *.patch` >> do >> if [ $p == "0000-cover-letter.patch" ]; then >> continue >> fi >> >> title=$(sed '/^Subject: \[PATCH .*\]/{N;s/\n / /g}' $p | grep >> -E "^Subject: \[PATCH .*\]" | cut -d ']' -f 2) >> commit=$(git log --pretty=oneline $1 | grep -F "$title" | cut >> -d ' ' -f 1) >> if [ -n "$multi" ]; then >> echo "$p" has multi-commits >> commit="multi" >> continue >> fi >> if [ -z "$commit" ]; then >> echo "$p" commit is null >> commit="null" >> continue >> fi >> >> # find insert line >> i=5 >> while true >> do >> ln=""$i"p" >> sub=`cat $p | sed -n "$ln"` >> i=$(($i+1)) >> if [ -z "$sub" ]; then >> break >> fi >> done >> i=$(($i-1)) >> >> version=`git name-rev $commit | awk -F '[v~^]' '{print $2}'` >> >> sed ""$i"a mainline inclusion\nfrom >> mainline-v$version\ncommit $commit\ncategory: feature\nbugzilla: >> $2\nCVE: NA\n\n--------------------------------\n" -i $p >> done >> > > No virus found > Checked by Hillstone Network AntiVirus >

1 0

[PATCH openEuler-1.0-LTS V2 00/90] Enabling AMD Milan series processor support
by Laibin Qiu 19 Jan '22

19 Jan '22

bugzilla: https://gitee.com/openeuler/kernel/issues/I4MKP4 Babu Moger (1): KVM: SVM: Clear the CR4 register on reset David Edmondson (1): KVM: x86: clflushopt should be treated as a no-op by emulation Fenghua Yu (2): x86/cpufeatures: Enumerate MOVDIRI instruction x86/cpufeatures: Enumerate MOVDIR64B instruction Haiyan Song (2): perf vendor events intel: Add Icelake V1.00 event file perf vendor events intel: Add Tremontx event file v1.02 Isaac Vaughn (1): EDAC/amd64: Add PCI device IDs for family 17h, model 70h Jan H. Schönherr (1): x86/mce: Fix use of uninitialized MCE message string Jim Mattson (1): kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID John Allen (2): kvm/svm: PKU not currently supported x86/microcode/AMD: Increase microcode PATCH_MAX_SIZE Kai Huang (3): kvm: x86: Move kvm_set_mmio_spte_mask() from x86.c to mmu.c kvm: x86: Fix reserved bits related calculation errors caused by MKTME kvm: x86: Fix L1TF mitigation for shadow MMU Kan Liang (1): perf vendor events intel: Add uncore_upi JSON support Kim Phillips (17): x86/cpu/amd: Call init_amd_zn() om Family 19h processors too perf/amd/uncore: Prepare L3 thread mask code for Family 19h perf/amd/uncore: Make L3 thread mask code more readable perf/amd/uncore: Add support for Family 19h L3 PMU arch/x86/amd/ibs: Fix re-arming IBS Fetch perf/x86/amd/ibs: Fix raw sample data accumulation perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour perf/x86/amd/ibs: Don't include randomized bits in get_ibs_op_count() perf/amd/uncore: Prepare to scale for more attributes that vary per family perf/amd/uncore: Allow F17h user threadmask and slicemask specification perf/amd/uncore: Allow F19h user coreid, threadmask, and sliceid specification perf vendor events amd: Add L3 cache events for Family 17h perf vendor events amd: Remove redundant '[' perf vendor events amd: Enable Family 19h users by matching Zen2 events perf/x86/amd/ibs: Support 27-bit extended Op/cycle counter tools/power turbostat: Support AMD Family 19h perf vendor events amd: Add L2 Prefetch events for zen1 Krish Sadhukhan (1): KVM: SVM: Replace hard-coded value with #define Like Xu (1): perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest Liu Jingqi (2): KVM: x86: expose MOVDIRI CPU feature into VM. KVM: x86: expose MOVDIR64B CPU feature into VM. Maciej S. Szmigiero (1): KVM: mmu: Fix SPTE encoding of MMIO generation upper half Marcel Bocu (1): x86/amd_nb: Add PCI device IDs for family 17h, model 70h Martin Liška (1): perf vendor events amd: perf PMU events for AMD Family 17h Nathan Chancellor (1): perf/amd/uncore: Fix sysfs type mismatch Paolo Bonzini (3): KVM: x86: only do L1TF workaround on affected processors KVM: x86: assign two bits to track SPTE kinds KVM: x86: fix overlap between SPTE_MMIO_MASK and generation Rasmus Villemoes (1): build_bug.h: add wrapper for _Static_assert Sean Christopherson (13): KVM: nVMX: Allocate and configure VM{READ,WRITE} bitmaps iff enable_shadow_vmcs KVM: x86: Add requisite includes to kvm_cache_regs.h KVM: x86: Add requisite includes to hyperv.h KVM: x86: Use a u64 when passing the MMIO gen around KVM: Explicitly define the "memslot update in-progress" bit KVM: x86: Refactor the MMIO SPTE generation handling KVM: x86: Rename access permissions cache member in struct kvm_vcpu_arch KVM: x86/mmu: Add explicit access mask for MMIO SPTEs KVM: x86/mmu: Consolidate "is MMIO SPTE" code KVM: x86/mmu: Apply max PA check for MMIO sptes to 32-bit KVM KVM: x86/mmu: Set mmio_value to '0' if reserved #PF can't be generated KVM: Remove the hack to trigger memslot generation wraparound KVM: Move the memslot update in-progress flag to bit 63 Sebastian Andrzej Siewior (3): x86/pkeys: Provide *pkru() helpers x86/fpu: Only write PKRU if it is different from current x86/pkeys: Don't check if PKRU is zero before writing it Tom Lendacky (1): KVM: SVM: Override default MMIO mask if memory encryption is enabled Vijay Thakkar (3): perf vendor events amd: Restrict model detection for zen1 based processors perf vendor events amd: Add Zen2 events perf vendor events amd: Update Zen1 events to V2 Woods, Brian (2): hwmon/k10temp, x86/amd_nb: Consolidate shared device IDs x86/amd_nb: Add PCI device IDs for family 17h, model 30h Yazen Ghannam (24): EDAC/amd64: Drop some family checks for newer systems x86/amd_nb: Add Family 19h PCI IDs EDAC/mce_amd: Always load on SMCA systems x86/MCE/AMD, EDAC/mce_amd: Add new MP5, NBIO, and PCIE SMCA bank types x86/MCE/AMD, EDAC/mce_amd: Add new McaTypes for CS, PSP, and SMU units x86/MCE/AMD, EDAC/mce_amd: Add new error descriptions for some SMCA bank types x86/MCE/AMD, EDAC/mce_amd: Add new Load Store unit McaType EDAC/amd64: Use a macro for iterating over Unified Memory Controllers EDAC/amd64: Support more than two controllers for chip selects handling EDAC/amd64: Initialize DIMM info for systems with more than two channels EDAC/amd64: Add Family 17h Model 30h PCI IDs EDAC/amd64: Support more than two Unified Memory Controllers EDAC/amd64: Set maximum channel layer size depending on family EDAC/amd64: Recognize x16 symbol size EDAC/amd64: Adjust printed chip select sizes when interleaved EDAC/amd64: Find Chip Select memory size using Address Mask EDAC/amd64: Cache secondary Chip Select registers EDAC/amd64: Support asymmetric dual-rank DIMMs EDAC/amd64: Set grain per DIMM EDAC/amd64: Make struct amd64_family_type global EDAC/amd64: Gather hardware information early EDAC/amd64: Save max number of controllers to family type EDAC/amd64: Add family ops for Family 19h Models 00h-0Fh EDAC/amd64: Handle three rank interleaving mode Documentation/virtual/kvm/mmu.txt | 13 +- arch/x86/events/amd/ibs.c | 93 +- arch/x86/events/amd/uncore.c | 179 ++-- arch/x86/events/perf_event.h | 3 +- arch/x86/include/asm/cpufeatures.h | 4 +- arch/x86/include/asm/kvm_host.h | 10 +- arch/x86/include/asm/mce.h | 7 + arch/x86/include/asm/microcode_amd.h | 2 +- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/perf_event.h | 16 +- arch/x86/include/asm/pgtable.h | 2 +- arch/x86/include/asm/special_insns.h | 19 +- arch/x86/kernel/amd_nb.c | 15 +- arch/x86/kernel/cpu/amd.c | 3 +- arch/x86/kernel/cpu/mce/amd.c | 28 +- arch/x86/kernel/cpu/mce/core.c | 4 +- arch/x86/kvm/cpuid.c | 6 +- arch/x86/kvm/emulate.c | 8 +- arch/x86/kvm/hyperv.h | 2 + arch/x86/kvm/kvm_cache_regs.h | 2 + arch/x86/kvm/mmu.c | 215 +++-- arch/x86/kvm/mmu.h | 2 +- arch/x86/kvm/svm.c | 53 +- arch/x86/kvm/vmx.c | 53 +- arch/x86/kvm/x86.c | 33 +- arch/x86/kvm/x86.h | 4 +- arch/x86/mm/pkeys.c | 7 - drivers/edac/amd64_edac.c | 609 ++++++++---- drivers/edac/amd64_edac.h | 31 +- drivers/edac/mce_amd.c | 134 ++- drivers/hwmon/k10temp.c | 9 +- include/linux/build_bug.h | 19 + include/linux/kvm_host.h | 21 + include/linux/pci_ids.h | 5 + .../pmu-events/arch/x86/amdzen1/branch.json | 23 + .../pmu-events/arch/x86/amdzen1/cache.json | 312 ++++++ .../pmu-events/arch/x86/amdzen1/core.json | 125 +++ .../arch/x86/amdzen1/floating-point.json | 224 +++++ .../pmu-events/arch/x86/amdzen1/memory.json | 184 ++++ .../pmu-events/arch/x86/amdzen1/other.json | 56 ++ .../pmu-events/arch/x86/amdzen2/branch.json | 52 + .../pmu-events/arch/x86/amdzen2/cache.json | 338 +++++++ .../pmu-events/arch/x86/amdzen2/core.json | 130 +++ .../arch/x86/amdzen2/floating-point.json | 140 +++ .../pmu-events/arch/x86/amdzen2/memory.json | 341 +++++++ .../pmu-events/arch/x86/amdzen2/other.json | 115 +++ .../pmu-events/arch/x86/icelake/cache.json | 552 +++++++++++ .../arch/x86/icelake/floating-point.json | 102 ++ .../pmu-events/arch/x86/icelake/frontend.json | 424 +++++++++ .../pmu-events/arch/x86/icelake/memory.json | 410 ++++++++ .../pmu-events/arch/x86/icelake/other.json | 121 +++ .../pmu-events/arch/x86/icelake/pipeline.json | 892 ++++++++++++++++++ .../arch/x86/icelake/virtual-memory.json | 236 +++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 6 + .../pmu-events/arch/x86/tremontx/cache.json | 111 +++ .../arch/x86/tremontx/frontend.json | 26 + .../pmu-events/arch/x86/tremontx/memory.json | 26 + .../pmu-events/arch/x86/tremontx/other.json | 26 + .../arch/x86/tremontx/pipeline.json | 111 +++ .../arch/x86/tremontx/uncore-memory.json | 73 ++ .../arch/x86/tremontx/uncore-other.json | 431 +++++++++ .../arch/x86/tremontx/uncore-power.json | 11 + .../arch/x86/tremontx/virtual-memory.json | 86 ++ tools/perf/pmu-events/jevents.c | 2 + tools/power/x86/turbostat/turbostat.c | 34 +- virt/kvm/kvm_main.c | 36 +- 66 files changed, 6839 insertions(+), 529 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/branch.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/core.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/other.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/branch.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/core.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/other.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/other.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/other.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-power.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json -- 2.22.0

2 89

2024

2023

2022

2021

2020

2019

Kernel