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Re: [PATCH openEuler-1.0-LTS V3 16/92] kvm: x86: Move kvm_set_mmio_spte_mask() from x86.c to mmu.c
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 15/92] kvm/svm: PKU not currently supported
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 14/92] kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 10/92] KVM: x86: expose MOVDIR64B CPU feature into VM.
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 09/92] KVM: x86: expose MOVDIRI CPU feature into VM.
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 08/92] KVM: x86: Add requisite includes to hyperv.h
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 07/92] KVM: x86: Add requisite includes to kvm_cache_regs.h
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

Re: [PATCH openEuler-1.0-LTS V3 06/92] KVM: nVMX: Allocate and configure VM{READ,WRITE} bitmaps iff enable_shadow_vmcs
by Zenghui Yu 26 Jan '22

26 Jan '22

Reviewed-by: Zenghui Yu <yuzenghui(a)huawei.com>

1 0

[PATCH OLK-5.10] eulerfs: remove redundant calculations
by Gou Hao 26 Jan '22

26 Jan '22

uniontech inclusion category: cleanup CVE: NA The 'left' always is 0. If it is not 0, it will 'goto out;' from the previous if judgment. --- Signed-off-by: Gou Hao <gouhao(a)uniontech.com> --- fs/eulerfs/dax.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/eulerfs/dax.c b/fs/eulerfs/dax.c index 9ec8ad7..131d08f 100644 --- a/fs/eulerfs/dax.c +++ b/fs/eulerfs/dax.c @@ -1172,8 +1172,8 @@ static ssize_t do_mapping_read(struct address_space *mapping, goto out; } - copied += (nr - left); - offset += (nr - left); + copied += nr; + offset += nr; index += offset >> PAGE_SHIFT; offset &= ~PAGE_MASK; } while (copied < len); -- 2.20.1

1 0

[PATCH] eulerfs: remove redundant calculations
by Gou Hao 26 Jan '22

26 Jan '22

uniontech inclusion category: cleanup CVE: NA The 'left' always is 0. If it is not 0, it will 'goto out;' from the previous if judgment. --- Signed-off-by: Gou Hao <gouhao(a)uniontech.com> --- fs/eulerfs/dax.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/eulerfs/dax.c b/fs/eulerfs/dax.c index 9ec8ad7..131d08f 100644 --- a/fs/eulerfs/dax.c +++ b/fs/eulerfs/dax.c @@ -1172,8 +1172,8 @@ static ssize_t do_mapping_read(struct address_space *mapping, goto out; } - copied += (nr - left); - offset += (nr - left); + copied += nr; + offset += nr; index += offset >> PAGE_SHIFT; offset &= ~PAGE_MASK; } while (copied < len); -- 2.20.1

1 0

[PATCH OLK-5.10 v6 0/2] change arm64 and x86 configs
by Chao Liu 26 Jan '22

26 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 265 +++++++----- arch/x86/configs/openeuler_defconfig | 549 +++++++++---------------- 2 files changed, 349 insertions(+), 465 deletions(-) -- 2.27.0

3 5

[PATCH openEuler-1.0-LTS 1/3] etmem: add original kernel swap enabled options
by Yang Yingliang 26 Jan '22

26 Jan '22

From: liubo <liubo254(a)huawei.com> euleros inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4QVXW CVE: NA ------------------------------------------------- etmem, the memory vertical expansion technology, uses DRAM and high-performance storage new media to form multi-level memory storage. By grading the stored data, etmem migrates the classified cold storage data from the storage medium to the high-performance storage medium, so as to achieve the purpose of memory capacity expansion and memory cost reduction. When the memory expansion function etmem is running, the native swap function of the kernel needs to be disabled in certain scenarios to avoid the impact of kernel swap. This feature provides the preceding functions. The /sys/kernel/mm/swap/ directory provides the kernel_swap_enable sys interface to enable or disable the native swap function of the kernel. The default value of /sys/kernel/mm/swap/kernel_swap_enable is true, that is, kernel swap is enabled by default. Turn on kernel swap: echo true > /sys/kernel/mm/swap/kernel_swap_enable Turn off kernel swap: echo false > /sys/kernel/mm/swap/kernel_swap_enable Signed-off-by: liubo <liubo254(a)huawei.com> Reviewed-by: Miaohe Lin <linmiaohe(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- include/linux/swap.h | 1 + mm/swap_state.c | 29 +++++++++++++++++++++++++++++ mm/vmscan.c | 18 ++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/include/linux/swap.h b/include/linux/swap.h index b7cfad35987a2..23549741336a4 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h @@ -476,6 +476,7 @@ extern struct page *swap_cluster_readahead(swp_entry_t entry, gfp_t flag, struct vm_fault *vmf); extern struct page *swapin_readahead(swp_entry_t entry, gfp_t flag, struct vm_fault *vmf); +extern bool kernel_swap_enabled(void); /* linux/mm/swapfile.c */ extern atomic_long_t nr_swap_pages; diff --git a/mm/swap_state.c b/mm/swap_state.c index 2137e2d571965..1527ac72928b6 100644 --- a/mm/swap_state.c +++ b/mm/swap_state.c @@ -40,6 +40,7 @@ static const struct address_space_operations swap_aops = { struct address_space *swapper_spaces[MAX_SWAPFILES] __read_mostly; static unsigned int nr_swapper_spaces[MAX_SWAPFILES] __read_mostly; static bool enable_vma_readahead __read_mostly = true; +static bool enable_kernel_swap __read_mostly = true; #define SWAP_RA_WIN_SHIFT (PAGE_SHIFT / 2) #define SWAP_RA_HITS_MASK ((1UL << SWAP_RA_WIN_SHIFT) - 1) @@ -326,6 +327,11 @@ static inline bool swap_use_vma_readahead(void) return READ_ONCE(enable_vma_readahead) && !atomic_read(&nr_rotate_swap); } +bool kernel_swap_enabled(void) +{ + return READ_ONCE(enable_kernel_swap); +} + /* * Lookup a swap entry in the swap cache. A found page will be returned * unlocked and with its refcount incremented - we rely on the kernel @@ -828,8 +834,31 @@ static struct kobj_attribute vma_ra_enabled_attr = __ATTR(vma_ra_enabled, 0644, vma_ra_enabled_show, vma_ra_enabled_store); +static ssize_t kernel_swap_enable_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", enable_kernel_swap ? "true" : "false"); +} +static ssize_t kernel_swap_enable_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + if (!strncmp(buf, "true", 4) || !strncmp(buf, "1", 1)) + WRITE_ONCE(enable_kernel_swap, true); + else if (!strncmp(buf, "false", 5) || !strncmp(buf, "0", 1)) + WRITE_ONCE(enable_kernel_swap, false); + else + return -EINVAL; + + return count; +} +static struct kobj_attribute kernel_swap_enable_attr = + __ATTR(kernel_swap_enable, 0644, kernel_swap_enable_show, + kernel_swap_enable_store); + static struct attribute *swap_attrs[] = { &vma_ra_enabled_attr.attr, + &kernel_swap_enable_attr.attr, NULL, }; diff --git a/mm/vmscan.c b/mm/vmscan.c index e8befe70d2800..2676d6cf2ccac 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -3248,6 +3248,16 @@ static bool throttle_direct_reclaim(gfp_t gfp_mask, struct zonelist *zonelist, return false; } +/* + * Check if original kernel swap is enabled + * turn off kernel swap,but leave page cache reclaim on + */ +static inline void kernel_swap_check(struct scan_control *sc) +{ + if (sc != NULL && !kernel_swap_enabled()) + sc->may_swap = 0; +} + unsigned long try_to_free_pages(struct zonelist *zonelist, int order, gfp_t gfp_mask, nodemask_t *nodemask) { @@ -3264,6 +3274,7 @@ unsigned long try_to_free_pages(struct zonelist *zonelist, int order, .may_swap = 1, }; + kernel_swap_check(&sc); /* * scan_control uses s8 fields for order, priority, and reclaim_idx. * Confirm they are large enough for max values. @@ -3548,6 +3559,8 @@ static int balance_pgdat(pg_data_t *pgdat, int order, int classzone_idx) count_vm_event(PAGEOUTRUN); + kernel_swap_check(&sc); + #ifdef CONFIG_SHRINK_PAGECACHE if (vm_cache_limit_mbytes && page_cache_over_limit()) shrink_page_cache(GFP_KERNEL); @@ -3963,6 +3976,8 @@ static unsigned long __shrink_page_cache(gfp_t mask) struct zonelist *zonelist = node_zonelist(numa_node_id(), mask); + kernel_swap_check(&sc); + return do_try_to_free_pages(zonelist, &sc); } @@ -4282,6 +4297,9 @@ static int __node_reclaim(struct pglist_data *pgdat, gfp_t gfp_mask, unsigned in cond_resched(); fs_reclaim_acquire(sc.gfp_mask); + + kernel_swap_check(&sc); + /* * We need to be able to allocate from the reserves for RECLAIM_UNMAP * and we also need to be able to write out pages for RECLAIM_WRITE -- 2.25.1

1 2

[PATCH OLK-5.10 v5 0/2] change arm64 and x86 configs
by Chao Liu 25 Jan '22

25 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 260 +++++++----- arch/x86/configs/openeuler_defconfig | 531 ++++++++----------------- 2 files changed, 337 insertions(+), 454 deletions(-) -- 2.27.0

5 9

[PATCH openEuler-1.0-LTS] net: bridge: clear bridge's private skb space on xmit
by Yang Yingliang 24 Jan '22

24 Jan '22

From: Nikolay Aleksandrov <nikolay(a)cumulusnetworks.com> mainline inclusion from mainline-v5.9-rc1 commit fd65e5a95d08389444e8591a20538b3edece0e15 category: bugfix bugzilla: 186114 CVE: NA -------------------------------- We need to clear all of the bridge private skb variables as they can be stale due to the packet being recirculated through the stack and then transmitted through the bridge device. Similar memset is already done on bridge's input. We've seen cases where proxyarp_replied was 1 on routed multicast packets transmitted through the bridge to ports with neigh suppress which were getting dropped. Same thing can in theory happen with the port isolation bit as well. Fixes: 821f1b21cabb ("bridge: add new BR_NEIGH_SUPPRESS port flag to suppress arp and nd flood") Signed-off-by: Nikolay Aleksandrov <nikolay(a)cumulusnetworks.com> Signed-off-by: David S. Miller <davem(a)davemloft.net> Signed-off-by: Huang Guobin <huangguobin4(a)huawei.com> Reviewed-by: Yue Haibing <yuehaibing(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- net/bridge/br_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/bridge/br_device.c b/net/bridge/br_device.c index 7b7784bb1cb99..9475e0443ff92 100644 --- a/net/bridge/br_device.c +++ b/net/bridge/br_device.c @@ -41,6 +41,8 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) const unsigned char *dest; u16 vid = 0; + memset(skb->cb, 0, sizeof(struct br_input_skb_cb)); + rcu_read_lock(); nf_ops = rcu_dereference(nf_br_ops); if (nf_ops && nf_ops->br_dev_xmit_hook(skb)) { -- 2.25.1

1 0

[PATCH openEuler-5.10 01/38] tcp_comp: implement sendmsg for tcp compression
by Zheng Zengkai 22 Jan '22

22 Jan '22

From: Wei Yongjun <weiyongjun1(a)huawei.com> hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4PNEK CVE: NA ------------------------------------------------- This patch implement software level compression for sending tcp messages. All of the TCP payload will be compressed before xmit. Signed-off-by: Wei Yongjun <weiyongjun1(a)huawei.com> Signed-off-by: Wang Yufen <wangyufen(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> Signed-off-by: Lu Wei <luwei32(a)huawei.com> Reviewed-by: Wang Yufen <wangyufen(a)huawei.com> Reviewed-by: Wei Yongjun <weiyongjun1(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- net/ipv4/Kconfig | 1 + net/ipv4/tcp_comp.c | 415 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 412 insertions(+), 4 deletions(-) diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig index 59ffbf80f7f2..22c554d3a9ab 100644 --- a/net/ipv4/Kconfig +++ b/net/ipv4/Kconfig @@ -745,6 +745,7 @@ config TCP_MD5SIG config TCP_COMP bool "TCP: Transport Layer Compression support" + depends on ZSTD_COMPRESS=y help Enable kernel payload compression support for TCP protocol. This allows payload compression handling of the TCP protocol to be done in-kernel. diff --git a/net/ipv4/tcp_comp.c b/net/ipv4/tcp_comp.c index fb90be4d9e9c..e85803da3924 100644 --- a/net/ipv4/tcp_comp.c +++ b/net/ipv4/tcp_comp.c @@ -5,7 +5,15 @@ * Copyright(c) 2021 Huawei Technologies Co., Ltd */ -#include <net/tcp.h> +#include <linux/skmsg.h> +#include <linux/zstd.h> + +#define TCP_COMP_MAX_PADDING 64 +#define TCP_COMP_SCRATCH_SIZE 65400 +#define TCP_COMP_MAX_CSIZE (TCP_COMP_SCRATCH_SIZE + TCP_COMP_MAX_PADDING) + +#define TCP_COMP_SEND_PENDING 1 +#define ZSTD_COMP_DEFAULT_LEVEL 1 static unsigned long tcp_compression_ports[65536 / 8]; @@ -14,11 +22,37 @@ int sysctl_tcp_compression_local __read_mostly; static struct proto tcp_prot_override; +struct tcp_comp_context_tx { + ZSTD_CStream *cstream; + void *cworkspace; + void *plaintext_data; + void *compressed_data; + struct sk_msg msg; + bool in_tcp_sendpages; +}; + struct tcp_comp_context { - struct proto *sk_proto; struct rcu_head rcu; + + struct proto *sk_proto; + void (*sk_write_space)(struct sock *sk); + + struct tcp_comp_context_tx tx; + + unsigned long flags; }; +static bool tcp_comp_is_write_pending(struct tcp_comp_context *ctx) +{ + return test_bit(TCP_COMP_SEND_PENDING, &ctx->flags); +} + +static void tcp_comp_err_abort(struct sock *sk, int err) +{ + sk->sk_err = err; + sk->sk_error_report(sk); +} + static bool tcp_comp_enabled(__be32 saddr, __be32 daddr, int port) { if (!sysctl_tcp_compression_local && @@ -55,11 +89,341 @@ static struct tcp_comp_context *comp_get_ctx(const struct sock *sk) return (__force void *)icsk->icsk_ulp_data; } -static int tcp_comp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) +static int tcp_comp_tx_context_init(struct tcp_comp_context *ctx) +{ + ZSTD_parameters params; + int csize; + + params = ZSTD_getParams(ZSTD_COMP_DEFAULT_LEVEL, PAGE_SIZE, 0); + csize = ZSTD_CStreamWorkspaceBound(params.cParams); + if (csize <= 0) + return -EINVAL; + + ctx->tx.cworkspace = kmalloc(csize, GFP_KERNEL); + if (!ctx->tx.cworkspace) + return -ENOMEM; + + ctx->tx.cstream = ZSTD_initCStream(params, 0, ctx->tx.cworkspace, + csize); + if (!ctx->tx.cstream) + goto err_cstream; + + ctx->tx.plaintext_data = kvmalloc(TCP_COMP_SCRATCH_SIZE, GFP_KERNEL); + if (!ctx->tx.plaintext_data) + goto err_cstream; + + ctx->tx.compressed_data = kvmalloc(TCP_COMP_MAX_CSIZE, GFP_KERNEL); + if (!ctx->tx.compressed_data) + goto err_compressed; + + return 0; + +err_compressed: + kvfree(ctx->tx.plaintext_data); + ctx->tx.plaintext_data = NULL; +err_cstream: + kfree(ctx->tx.cworkspace); + ctx->tx.cworkspace = NULL; + + return -ENOMEM; +} + +static void *tcp_comp_get_tx_stream(struct sock *sk) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + + if (!ctx->tx.plaintext_data) + tcp_comp_tx_context_init(ctx); + + return ctx->tx.plaintext_data; +} + +static int alloc_compressed_msg(struct sock *sk, int len) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct sk_msg *msg = &ctx->tx.msg; + + sk_msg_init(msg); + + return sk_msg_alloc(sk, msg, len, 0); +} + +static int memcopy_from_iter(struct sock *sk, struct iov_iter *from, int copy) +{ + void *dest; + int rc; + + dest = tcp_comp_get_tx_stream(sk); + if (!dest) + return -ENOSPC; + + if (sk->sk_route_caps & NETIF_F_NOCACHE_COPY) + rc = copy_from_iter_nocache(dest, copy, from); + else + rc = copy_from_iter(dest, copy, from); + + if (rc != copy) + rc = -EFAULT; + + return rc; +} + +static int memcopy_to_msg(struct sock *sk, int bytes) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct sk_msg *msg = &ctx->tx.msg; + int i = msg->sg.curr; + struct scatterlist *sge; + u32 copy, buf_size; + void *from, *to; + + from = ctx->tx.compressed_data; + do { + sge = sk_msg_elem(msg, i); + /* This is possible if a trim operation shrunk the buffer */ + if (msg->sg.copybreak >= sge->length) { + msg->sg.copybreak = 0; + sk_msg_iter_var_next(i); + if (i == msg->sg.end) + break; + sge = sk_msg_elem(msg, i); + } + buf_size = sge->length - msg->sg.copybreak; + copy = (buf_size > bytes) ? bytes : buf_size; + to = sg_virt(sge) + msg->sg.copybreak; + msg->sg.copybreak += copy; + memcpy(to, from, copy); + bytes -= copy; + from += copy; + if (!bytes) + break; + msg->sg.copybreak = 0; + sk_msg_iter_var_next(i); + } while (i != msg->sg.end); + + msg->sg.curr = i; + return bytes; +} + +static int tcp_comp_compress_to_msg(struct sock *sk, int bytes) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + ZSTD_outBuffer outbuf; + ZSTD_inBuffer inbuf; + size_t ret; + + inbuf.src = ctx->tx.plaintext_data; + outbuf.dst = ctx->tx.compressed_data; + inbuf.size = bytes; + outbuf.size = TCP_COMP_MAX_CSIZE; + inbuf.pos = 0; + outbuf.pos = 0; + + ret = ZSTD_compressStream(ctx->tx.cstream, &outbuf, &inbuf); + if (ZSTD_isError(ret)) + return -EIO; + + ret = ZSTD_flushStream(ctx->tx.cstream, &outbuf); + if (ZSTD_isError(ret)) + return -EIO; + + if (inbuf.pos != inbuf.size) + return -EIO; + + if (memcopy_to_msg(sk, outbuf.pos)) + return -EIO; + + sk_msg_trim(sk, &ctx->tx.msg, outbuf.pos); + + return 0; +} + +static int tcp_comp_push_msg(struct sock *sk, struct sk_msg *msg, int flags) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct scatterlist *sg; + int ret, offset; + struct page *p; + size_t size; + + ctx->tx.in_tcp_sendpages = true; + while (1) { + sg = sk_msg_elem(msg, msg->sg.start); + offset = sg->offset; + size = sg->length; + p = sg_page(sg); +retry: + ret = do_tcp_sendpages(sk, p, offset, size, flags); + if (ret != size) { + if (ret > 0) { + sk_mem_uncharge(sk, ret); + sg->offset += ret; + sg->length -= ret; + size -= ret; + offset += ret; + goto retry; + } + ctx->tx.in_tcp_sendpages = false; + return ret; + } + + sk_mem_uncharge(sk, ret); + msg->sg.size -= size; + put_page(p); + sk_msg_iter_next(msg, start); + if (msg->sg.start == msg->sg.end) + break; + } + + clear_bit(TCP_COMP_SEND_PENDING, &ctx->flags); + ctx->tx.in_tcp_sendpages = false; + + return 0; +} + +static int tcp_comp_push(struct sock *sk, int bytes, int flags) { struct tcp_comp_context *ctx = comp_get_ctx(sk); + int ret; - return ctx->sk_proto->sendmsg(sk, msg, size); + ret = tcp_comp_compress_to_msg(sk, bytes); + if (ret < 0) { + pr_debug("%s: failed to compress sg\n", __func__); + return ret; + } + + set_bit(TCP_COMP_SEND_PENDING, &ctx->flags); + + ret = tcp_comp_push_msg(sk, &ctx->tx.msg, flags); + if (ret) { + pr_debug("%s: failed to tcp_comp_push_sg\n", __func__); + return ret; + } + + return 0; +} + +static int wait_on_pending_writer(struct sock *sk, long *timeo) +{ + DEFINE_WAIT_FUNC(wait, woken_wake_function); + int ret = 0; + + add_wait_queue(sk_sleep(sk), &wait); + while (1) { + if (!*timeo) { + ret = -EAGAIN; + break; + } + + if (signal_pending(current)) { + ret = sock_intr_errno(*timeo); + break; + } + + if (sk_wait_event(sk, timeo, !sk->sk_write_pending, &wait)) + break; + } + remove_wait_queue(sk_sleep(sk), &wait); + + return ret; +} + +static int tcp_comp_push_pending_msg(struct sock *sk, int flags) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + struct sk_msg *msg = &ctx->tx.msg; + + if (msg->sg.start == msg->sg.end) + return 0; + + return tcp_comp_push_msg(sk, msg, flags); +} + +static int tcp_comp_complete_pending_work(struct sock *sk, int flags, + long *timeo) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + int ret = 0; + + if (unlikely(sk->sk_write_pending)) + ret = wait_on_pending_writer(sk, timeo); + + if (!ret && tcp_comp_is_write_pending(ctx)) + ret = tcp_comp_push_pending_msg(sk, flags); + + return ret; +} + +static int tcp_comp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + int copied = 0, err = 0; + size_t try_to_copy; + int required_size; + long timeo; + + lock_sock(sk); + + timeo = sock_sndtimeo(sk, msg->msg_flags & MSG_DONTWAIT); + + err = tcp_comp_complete_pending_work(sk, msg->msg_flags, &timeo); + if (err) + goto out_err; + + while (msg_data_left(msg)) { + if (sk->sk_err) { + err = -sk->sk_err; + goto out_err; + } + + try_to_copy = msg_data_left(msg); + if (try_to_copy > TCP_COMP_SCRATCH_SIZE) + try_to_copy = TCP_COMP_SCRATCH_SIZE; + required_size = try_to_copy + TCP_COMP_MAX_PADDING; + + if (!sk_stream_memory_free(sk)) + goto wait_for_sndbuf; + +alloc_compressed: + err = alloc_compressed_msg(sk, required_size); + if (err) { + if (err != -ENOSPC) + goto wait_for_memory; + goto out_err; + } + + err = memcopy_from_iter(sk, &msg->msg_iter, try_to_copy); + if (err < 0) + goto out_err; + + copied += try_to_copy; + + err = tcp_comp_push(sk, try_to_copy, msg->msg_flags); + if (err < 0) { + if (err == -ENOMEM) + goto wait_for_memory; + if (err != -EAGAIN) + tcp_comp_err_abort(sk, EBADMSG); + goto out_err; + } + + continue; +wait_for_sndbuf: + set_bit(SOCK_NOSPACE, &sk->sk_socket->flags); +wait_for_memory: + err = sk_stream_wait_memory(sk, &timeo); + if (err) + goto out_err; + if (ctx->tx.msg.sg.size < required_size) + goto alloc_compressed; + } + +out_err: + err = sk_stream_error(sk, msg->msg_flags, err); + + release_sock(sk); + + return copied ? copied : err; } static int tcp_comp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, @@ -70,10 +434,35 @@ static int tcp_comp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, return ctx->sk_proto->recvmsg(sk, msg, len, nonblock, flags, addr_len); } +static void tcp_comp_write_space(struct sock *sk) +{ + struct tcp_comp_context *ctx = comp_get_ctx(sk); + + if (ctx->tx.in_tcp_sendpages) { + ctx->sk_write_space(sk); + return; + } + + if (!sk->sk_write_pending && tcp_comp_is_write_pending(ctx)) { + gfp_t sk_allocation = sk->sk_allocation; + int rc; + + sk->sk_allocation = GFP_ATOMIC; + rc = tcp_comp_push_pending_msg(sk, MSG_DONTWAIT | MSG_NOSIGNAL); + sk->sk_allocation = sk_allocation; + + if (rc < 0) + return; + } + + ctx->sk_write_space(sk); +} + void tcp_init_compression(struct sock *sk) { struct inet_connection_sock *icsk = inet_csk(sk); struct tcp_comp_context *ctx = NULL; + struct sk_msg *msg = NULL; struct tcp_sock *tp = tcp_sk(sk); if (!tp->rx_opt.comp_ok) @@ -83,20 +472,38 @@ void tcp_init_compression(struct sock *sk) if (!ctx) return; + msg = &ctx->tx.msg; + sk_msg_init(msg); + + ctx->sk_write_space = sk->sk_write_space; ctx->sk_proto = sk->sk_prot; WRITE_ONCE(sk->sk_prot, &tcp_prot_override); + sk->sk_write_space = tcp_comp_write_space; rcu_assign_pointer(icsk->icsk_ulp_data, ctx); sock_set_flag(sk, SOCK_COMP); } +static void tcp_comp_context_tx_free(struct tcp_comp_context *ctx) +{ + kfree(ctx->tx.cworkspace); + ctx->tx.cworkspace = NULL; + + kvfree(ctx->tx.plaintext_data); + ctx->tx.plaintext_data = NULL; + + kvfree(ctx->tx.compressed_data); + ctx->tx.compressed_data = NULL; +} + static void tcp_comp_context_free(struct rcu_head *head) { struct tcp_comp_context *ctx; ctx = container_of(head, struct tcp_comp_context, rcu); + tcp_comp_context_tx_free(ctx); kfree(ctx); } -- 2.20.1

1 37

[PATCH OLK-5.10 v3 0/2] change arm64 and x86 configs
by Chao Liu 22 Jan '22

22 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 292 ++++++++----- arch/x86/configs/openeuler_defconfig | 548 +++++++++---------------- 2 files changed, 380 insertions(+), 460 deletions(-) -- 2.27.0

5 9

[PATCH OLK-5.10 v7 3/3] arm64: openeuler_defconfig: Enable ARM64_PMEM_LEGACY
by Zhuling 22 Jan '22

22 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Enable legacy pmem register feature for arm64. Signed-off-by: Zhuling <zhuling8(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> --- arch/arm64/configs/openeuler_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 771eb45..7745715 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -416,6 +416,8 @@ CONFIG_ARM64_CPU_PARK=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_ARM64_PMEM_RESERVE=y +CONFIG_ARM64_PMEM_LEGACY=m # CONFIG_ARM64_SW_TTBR0_PAN is not set CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_ILP32=y @@ -6027,6 +6029,8 @@ CONFIG_USB4=m # end of Android CONFIG_LIBNVDIMM=m +CONFIG_PMEM_LEGACY=m +CONFIG_PMEM_LEGACY_DEVICE=y CONFIG_BLK_DEV_PMEM=m CONFIG_ND_BLK=m CONFIG_ND_CLAIM=y -- 2.9.5

1 0

[PATCH OLK-5.10 v7 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by Zhuling 22 Jan '22

22 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of nd_e820.o, then the code could be reused by other architectures. Note，this patch fixs the nd_e820.c build introduced by commit 2499317e408e ("arm64: Revert feature: Add memmap parameter and register pmem"). Signed-off-by: Zhuling <zhuling8(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> --- arch/x86/Kconfig | 6 ++---- arch/x86/kernel/Makefile | 1 - drivers/nvdimm/Kconfig | 6 ++++++ drivers/nvdimm/Makefile | 2 ++ arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 tools/testing/nvdimm/Kbuild | 2 +- 6 files changed, 11 insertions(+), 6 deletions(-) rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c77ef59..1d3176a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE default 0 if X86_32 default 0xdead000000000000 if X86_64 -config X86_PMEM_LEGACY_DEVICE - bool - config X86_PMEM_LEGACY tristate "Support non-standard NVDIMMs and ADR protected memory" depends on PHYS_ADDR_T_64BIT depends on BLK_DEV - select X86_PMEM_LEGACY_DEVICE + select PMEM_LEGACY + select PMEM_LEGACY_DEVICE select NUMA_KEEP_MEMINFO if NUMA select LIBNVDIMM help diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f0606f8..1e12751 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index b7d1eb3..632b6ed 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM if LIBNVDIMM +config PMEM_LEGACY + tristate + +config PMEM_LEGACY_DEVICE + bool + config BLK_DEV_PMEM tristate "PMEM: Persistent memory block device support" default LIBNVDIMM diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 0407753..2098221 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_OF_PMEM) += of_pmem.o obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c similarity index 100% rename from arch/x86/kernel/pmem.c rename to drivers/nvdimm/pmem_legacy_device.c diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild index 47f9cc9..77aa117 100644 --- a/tools/testing/nvdimm/Kbuild +++ b/tools/testing/nvdimm/Kbuild @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_ACPI_NFIT) += nfit.o ifeq ($(CONFIG_DAX),m) obj-$(CONFIG_DAX) += dax.o -- 2.9.5

1 1

[PATCH OLK-5.10 v4 0/2] change arm64 and x86 configs
by Chao Liu 22 Jan '22

22 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 272 ++++++++----- arch/x86/configs/openeuler_defconfig | 540 +++++++++---------------- 2 files changed, 356 insertions(+), 456 deletions(-) -- 2.27.0

1 2

[PATCH openEuler-1.0-LTS V2] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Laibin Qiu 22 Jan '22

22 Jan '22

phytium inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4RK58 CVE: NA -------------------------------- The system would hang up when the Phytium S2500 communicates with some BMCs after several rounds of transactions, unless we reset the controller timeout counter manually by calling firmware through SMC. Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> #openEuler_contributor Signed-off-by: Laibin Qiu <qiulaibin(a)huawei.com> --- drivers/char/ipmi/ipmi_si_mem_io.c | 72 ++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c index 75583612ab10..9403e35a1993 100644 --- a/drivers/char/ipmi/ipmi_si_mem_io.c +++ b/drivers/char/ipmi/ipmi_si_mem_io.c @@ -3,9 +3,75 @@ #include <linux/io.h> #include "ipmi_si.h" +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 +#include <linux/arm-smccc.h> + +#define CTL_RST_FUNC_ID 0xC2000011 + +static bool apply_phytium2500_workaround; + +struct ipmi_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +}; + +static struct ipmi_workaround_oem_info wa_info[] = { + { + .oem_id = "KPSVVJ", + } +}; + +static void ipmi_check_phytium_workaround(void) +{ +#ifdef CONFIG_ACPI + struct acpi_table_header tbl; + int i; + + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) + return; + + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) + continue; + + apply_phytium2500_workaround = true; + break; + } +#endif +} + +static void ctl_smc(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3) +{ + struct arm_smccc_res res; + + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); + if (res.a0 != 0) + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", + (int)res.a0, arg2); +} + +static void ctl_timeout_reset(void) +{ + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); +} + +static inline void ipmi_phytium_workaround(void) +{ + if (apply_phytium2500_workaround) + ctl_timeout_reset(); +} + +#else +static inline void ipmi_check_phytium_workaround(void) {} +static inline void ipmi_phytium_workaround(void) {} +#endif + static unsigned char intf_mem_inb(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return readb((io->addr)+(offset * io->regspacing)); } @@ -31,6 +97,8 @@ static void intf_mem_outw(const struct si_sm_io *io, unsigned int offset, static unsigned char intf_mem_inl(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } @@ -44,6 +112,8 @@ static void intf_mem_outl(const struct si_sm_io *io, unsigned int offset, #ifdef readq static unsigned char mem_inq(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium_workaround(); + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } @@ -81,6 +151,8 @@ int ipmi_si_mem_setup(struct si_sm_io *io) if (!addr) return -ENODEV; + ipmi_check_phytium_workaround(); + /* * Figure out the actual readb/readw/readl/etc routine to use based * upon the register size. -- 2.22.0

1 0

Re: [PATCH V2] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Xie XiuQi 21 Jan '22

21 Jan '22

On 2022/1/21 18:06, Chen Baozi wrote: > phytium inclusion > category: bugfix > bugzilla: https://gitee.com/openeuler/kernel/issues/I4RK58 > CVE: NA > > --------------------------------- > > The system would hang up when the Phytium S2500 communicates with > some BMCs after several rounds of transactions, unless we reset > the controller timeout counter manually by calling firmware through > SMC. > > Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> > Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> Looks good to me, Reviewed-by: Xie XiuQi <xiexiuqi(a)huawei.com> > --- > drivers/char/ipmi/ipmi_si_mem_io.c | 74 ++++++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c > index 75583612ab10..bb4ed90a1153 100644 > --- a/drivers/char/ipmi/ipmi_si_mem_io.c > +++ b/drivers/char/ipmi/ipmi_si_mem_io.c > @@ -3,9 +3,75 @@ > #include <linux/io.h> > #include "ipmi_si.h" > > +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 > +#include <linux/arm-smccc.h> > + > +#define CTL_RST_FUNC_ID 0xC2000011 > + > +static bool apply_phytium2500_workaround; > + > +struct ipmi_workaround_oem_info { > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > +}; > + > +static struct ipmi_workaround_oem_info wa_info[] = { > + { > + .oem_id = "KPSVVJ", > + } > +}; > + > +static void ipmi_check_phytium_workaround(void) > +{ > +#ifdef CONFIG_ACPI > + struct acpi_table_header tbl; > + int i; > + > + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) > + return; > + > + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { > + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) > + continue; > + > + apply_phytium2500_workaround = true; > + break; > + } > +#endif > +} > + > +static void ctl_smc(unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); > + if (res.a0 != 0) > + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", > + (int)res.a0, arg2); > +} > + > +static void ctl_timeout_reset(void) > +{ > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); > +} > + > +static inline void ipmi_phytium_workaround(void) > +{ > + if (apply_phytium2500_workaround) > + ctl_timeout_reset(); > +} > + > +#else > +static inline void ipmi_check_phytium_workaround(void) {} > +static inline void ipmi_phytium_workaround(void) {} > +#endif > + > static unsigned char intf_mem_inb(const struct si_sm_io *io, > unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return readb((io->addr)+(offset * io->regspacing)); > } > > @@ -18,6 +84,8 @@ static void intf_mem_outb(const struct si_sm_io *io, unsigned int offset, > static unsigned char intf_mem_inw(const struct si_sm_io *io, > unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) > & 0xff; > } > @@ -31,6 +99,8 @@ static void intf_mem_outw(const struct si_sm_io *io, unsigned int offset, > static unsigned char intf_mem_inl(const struct si_sm_io *io, > unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) > & 0xff; > } > @@ -44,6 +114,8 @@ static void intf_mem_outl(const struct si_sm_io *io, unsigned int offset, > #ifdef readq > static unsigned char mem_inq(const struct si_sm_io *io, unsigned int offset) > { > + ipmi_phytium_workaround(); > + > return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) > & 0xff; > } > @@ -81,6 +153,8 @@ int ipmi_si_mem_setup(struct si_sm_io *io) > if (!addr) > return -ENODEV; > > + ipmi_check_phytium_workaround(); > + > /* > * Figure out the actual readb/readw/readl/etc routine to use based > * upon the register size. >

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Re: [PATCH] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Xie XiuQi 21 Jan '22

21 Jan '22

Hi, Thanks for your patch. There're some comments bellow. On 2022/1/19 14:57, Chen Baozi wrote: > The system would hang up when the Phytium S2500 communicates with > some BMCs after several rounds of transactions, unless we reset > the controller timeout counter manually by calling firmware through > SMC. > > Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> > Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> > --- > drivers/char/ipmi/ipmi_si_mem_io.c | 117 ++++++++++++++++++++++++++++- > 1 file changed, 113 insertions(+), 4 deletions(-) > > diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c > index 75583612ab10..73a3d6979eaa 100644 > --- a/drivers/char/ipmi/ipmi_si_mem_io.c > +++ b/drivers/char/ipmi/ipmi_si_mem_io.c > @@ -3,6 +3,105 @@ > #include <linux/io.h> > #include "ipmi_si.h" > > +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 > +#include <linux/arm-smccc.h> > + > +#define CTL_RST_FUNC_ID 0xC2000011 > + > +static void ctl_smc(unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); > + if (res.a0 != 0) > + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", > + (int)res.a0, arg2); > +} > + > +static void ctl_timeout_reset(void) > +{ > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); > +} > + > +static unsigned char intf_mem_inb_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return readb((io->addr)+(offset * io->regspacing)); 与 intf_mem_inb（）代码重复，下同。 > +} > + > +static unsigned char intf_mem_inw_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char intf_mem_inl_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char mem_inq_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > +#else > +#define intf_mem_inb_2500 intf_mem_inb > +#define intf_mem_inw_2500 intf_mem_inw > +#define intf_mem_inl_2500 intf_mem_inl > +#define mem_inq_2500 mem_inq > +#endif > + > +static bool apply_phytium2500_workaround; 这个变量全局存在的，其实只在 phytium2500 平台上才有意义。 > + > +#ifdef CONFIG_ACPI > +struct ipmi_workaround_oem_info { > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > +}; > + > +static struct ipmi_workaround_oem_info wa_info[] = { > + { > + .oem_id = "KPSVVJ", > + } > +}; > + > +static void ipmi_check_phytium_workaround(void) > +{ > + struct acpi_table_header tbl; > + int i; > + > + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) > + return; > + > + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { > + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) > + continue; > + > + apply_phytium2500_workaround = true; > + break; > + } > +} 这个 CONFIG_ACPI 和 PHYTIUM 没有依赖，即便不是 PHYTIUM 平台，仍然会做这些没必要的检查。而且在非 ARM64 架构上，这个 apply_phytium2500_workaround 仍然会全局存在。是不是类似这样比较好： #ifdef CONFIG_ARM_GIC_PHYTIUM_2500 static bool apply_phytium2500_workaround; static void ipmi_check_phytium_workaround(void) { #ifdef CONFIG_ACPI ... #endif } ... static inline void ipmi_phytium2500_workaround（void） { if (apply_phytium2500_workaround) ctl_timeout_reset(); } static unsigned char intf_mem_inb(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium2500_workaround(); return readb((io->addr)+(offset * io->regspacing)); } static unsigned char intf_mem_inw(const struct si_sm_io *io, unsigned int offset) { + ipmi_phytium2500_workaround(); return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) & 0xff; } ... #else static inline void ipmi_phytium2500_workaround（） {} static inline void ipmi_check_phytium_workaround(void) {} #endif > +#else > +static void ipmi_check_phytium_workaround(void) > +{ > + apply_phytium2500_workaround = false; > +} > +#endif > + > static unsigned char intf_mem_inb(const struct si_sm_io *io, > unsigned int offset) > { > @@ -81,26 +180,36 @@ int ipmi_si_mem_setup(struct si_sm_io *io) > if (!addr) > return -ENODEV; > > + ipmi_check_phytium_workaround(); > + > /* > * Figure out the actual readb/readw/readl/etc routine to use based > * upon the register size. > */ > switch (io->regsize) { > case 1: > - io->inputb = intf_mem_inb; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inb_2500 : > + intf_mem_inb; > io->outputb = intf_mem_outb; > break; > case 2: > - io->inputb = intf_mem_inw; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inw_2500 : > + intf_mem_inw; > io->outputb = intf_mem_outw; > break; > case 4: > - io->inputb = intf_mem_inl; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inl_2500 : > + intf_mem_inl; > io->outputb = intf_mem_outl; > break; > #ifdef readq > case 8: > - io->inputb = mem_inq; > + io->inputb = apply_phytium2500_workaround ? > + mem_inq_2500 : > + mem_inq; > io->outputb = mem_outq; > break; > #endif >

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[PATCH OLK-5.10 v6 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by Zhuling 21 Jan '22

21 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of nd_e820.o, then the code could be reused by other architectures. Note��this patch fixs the nd_e820.c build introduced by commit 2499317e408e ("arm64: Revert feature: Add memmap parameter and register pmem"). Signed-off-by: Zhuling <zhuling8(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> --- arch/x86/Kconfig | 6 ++---- arch/x86/kernel/Makefile | 1 - drivers/nvdimm/Kconfig | 6 ++++++ drivers/nvdimm/Makefile | 2 ++ arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 tools/testing/nvdimm/Kbuild | 2 +- 6 files changed, 11 insertions(+), 6 deletions(-) rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c77ef59..1d3176a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE default 0 if X86_32 default 0xdead000000000000 if X86_64 -config X86_PMEM_LEGACY_DEVICE - bool - config X86_PMEM_LEGACY tristate "Support non-standard NVDIMMs and ADR protected memory" depends on PHYS_ADDR_T_64BIT depends on BLK_DEV - select X86_PMEM_LEGACY_DEVICE + select PMEM_LEGACY + select PMEM_LEGACY_DEVICE select NUMA_KEEP_MEMINFO if NUMA select LIBNVDIMM help diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f0606f8..1e12751 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index b7d1eb3..632b6ed 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM if LIBNVDIMM +config PMEM_LEGACY + tristate + +config PMEM_LEGACY_DEVICE + bool + config BLK_DEV_PMEM tristate "PMEM: Persistent memory block device support" default LIBNVDIMM diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 0407753..2098221 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_OF_PMEM) += of_pmem.o obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c similarity index 100% rename from arch/x86/kernel/pmem.c rename to drivers/nvdimm/pmem_legacy_device.c diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild index 47f9cc9..77aa117 100644 --- a/tools/testing/nvdimm/Kbuild +++ b/tools/testing/nvdimm/Kbuild @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_ACPI_NFIT) += nfit.o ifeq ($(CONFIG_DAX),m) obj-$(CONFIG_DAX) += dax.o -- 2.9.5

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Re: [PATCH OLK-5.10 v5 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by zhuling 21 Jan '22

21 Jan '22

On 2022/1/21 14:25, Kefeng Wang wrote: > Move x86's pmem.c into nvdimm, and rename it pmem_legacy_device.c, > also rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE. > Meanwhile, add PMEM_LEGACY to control the built of nd_e820.o, then > the code could be reused by other architectures. > > Note，this patch fixs the nd_e820.c build introduced by commit 2499317e408e > ("arm64: Revert feature: Add memmap parameter and register pmem"). > > changelog改下；好的，我加下 > > On 2022/1/21 11:20, Zhuling wrote: >> hulk inclusion >> category: feature >> bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I >> >> Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to >> PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of >> nd_e820.o, then the code could be reused by other architectures. >> >> Signed-off-by: Zhuling <zhuling8(a)huawei.com> >> --- >> arch/x86/Kconfig | 6 ++---- >> arch/x86/kernel/Makefile | 1 - >> drivers/nvdimm/Kconfig | 6 ++++++ >> drivers/nvdimm/Makefile | 2 ++ >> arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 >> tools/testing/nvdimm/Kbuild | 2 +- >> 6 files changed, 11 insertions(+), 6 deletions(-) >> rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) >> >> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig >> index c77ef59..1d3176a 100644 >> --- a/arch/x86/Kconfig >> +++ b/arch/x86/Kconfig >> @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE >> default 0 if X86_32 >> default 0xdead000000000000 if X86_64 >> -config X86_PMEM_LEGACY_DEVICE >> - bool >> - >> config X86_PMEM_LEGACY >> tristate "Support non-standard NVDIMMs and ADR protected memory" >> depends on PHYS_ADDR_T_64BIT >> depends on BLK_DEV >> - select X86_PMEM_LEGACY_DEVICE >> + select PMEM_LEGACY >> + select PMEM_LEGACY_DEVICE >> select NUMA_KEEP_MEMINFO if NUMA >> select LIBNVDIMM >> help >> diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile >> index f0606f8..1e12751 100644 >> --- a/arch/x86/kernel/Makefile >> +++ b/arch/x86/kernel/Makefile >> @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o >> obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o >> obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o >> obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o >> -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o >> obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o >> diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig >> index b7d1eb3..632b6ed 100644 >> --- a/drivers/nvdimm/Kconfig >> +++ b/drivers/nvdimm/Kconfig >> @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM >> if LIBNVDIMM >> +config PMEM_LEGACY >> + tristate >> + >> +config PMEM_LEGACY_DEVICE >> + bool >> + >> config BLK_DEV_PMEM >> tristate "PMEM: Persistent memory block device support" >> default LIBNVDIMM >> diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile >> index 0407753..2098221 100644 >> --- a/drivers/nvdimm/Makefile >> +++ b/drivers/nvdimm/Makefile >> @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o >> obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o >> obj-$(CONFIG_ND_BTT) += nd_btt.o >> obj-$(CONFIG_ND_BLK) += nd_blk.o >> +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o >> +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o >> obj-$(CONFIG_OF_PMEM) += of_pmem.o >> obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o >> diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c >> similarity index 100% >> rename from arch/x86/kernel/pmem.c >> rename to drivers/nvdimm/pmem_legacy_device.c >> diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild >> index 47f9cc9..77aa117 100644 >> --- a/tools/testing/nvdimm/Kbuild >> +++ b/tools/testing/nvdimm/Kbuild >> @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o >> obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o >> obj-$(CONFIG_ND_BTT) += nd_btt.o >> obj-$(CONFIG_ND_BLK) += nd_blk.o >> -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o >> +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o >> obj-$(CONFIG_ACPI_NFIT) += nfit.o >> ifeq ($(CONFIG_DAX),m) >> obj-$(CONFIG_DAX) += dax.o > .

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[PATCH OLK-5.10 v5 1/3] x86: pmem: move persistent memory(legacy) code into nvdimm
by Zhuling 21 Jan '22

21 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I Move x86's pmem.c into nvdimm, and rename X86_PMEM_LEGACY_DEVICE to PMEM_LEGACY_DEVICE, also add PMEM_LEGACY to control the built of nd_e820.o, then the code could be reused by other architectures. Signed-off-by: Zhuling <zhuling8(a)huawei.com> --- arch/x86/Kconfig | 6 ++---- arch/x86/kernel/Makefile | 1 - drivers/nvdimm/Kconfig | 6 ++++++ drivers/nvdimm/Makefile | 2 ++ arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c | 0 tools/testing/nvdimm/Kbuild | 2 +- 6 files changed, 11 insertions(+), 6 deletions(-) rename arch/x86/kernel/pmem.c => drivers/nvdimm/pmem_legacy_device.c (100%) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c77ef59..1d3176a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1667,14 +1667,12 @@ config ILLEGAL_POINTER_VALUE default 0 if X86_32 default 0xdead000000000000 if X86_64 -config X86_PMEM_LEGACY_DEVICE - bool - config X86_PMEM_LEGACY tristate "Support non-standard NVDIMMs and ADR protected memory" depends on PHYS_ADDR_T_64BIT depends on BLK_DEV - select X86_PMEM_LEGACY_DEVICE + select PMEM_LEGACY + select PMEM_LEGACY_DEVICE select NUMA_KEEP_MEMINFO if NUMA select LIBNVDIMM help diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f0606f8..1e12751 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -130,7 +130,6 @@ obj-$(CONFIG_KVM_GUEST) += kvm.o kvmclock.o obj-$(CONFIG_PARAVIRT) += paravirt.o paravirt_patch.o obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= paravirt-spinlocks.o obj-$(CONFIG_PARAVIRT_CLOCK) += pvclock.o -obj-$(CONFIG_X86_PMEM_LEGACY_DEVICE) += pmem.o obj-$(CONFIG_JAILHOUSE_GUEST) += jailhouse.o diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index b7d1eb3..632b6ed 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -19,6 +19,12 @@ menuconfig LIBNVDIMM if LIBNVDIMM +config PMEM_LEGACY + tristate + +config PMEM_LEGACY_DEVICE + bool + config BLK_DEV_PMEM tristate "PMEM: Persistent memory block device support" default LIBNVDIMM diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 0407753..2098221 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -3,6 +3,8 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o +obj-$(CONFIG_PMEM_LEGACY_DEVICE) += pmem_legacy_device.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_OF_PMEM) += of_pmem.o obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o diff --git a/arch/x86/kernel/pmem.c b/drivers/nvdimm/pmem_legacy_device.c similarity index 100% rename from arch/x86/kernel/pmem.c rename to drivers/nvdimm/pmem_legacy_device.c diff --git a/tools/testing/nvdimm/Kbuild b/tools/testing/nvdimm/Kbuild index 47f9cc9..77aa117 100644 --- a/tools/testing/nvdimm/Kbuild +++ b/tools/testing/nvdimm/Kbuild @@ -28,7 +28,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o -obj-$(CONFIG_X86_PMEM_LEGACY) += nd_e820.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_ACPI_NFIT) += nfit.o ifeq ($(CONFIG_DAX),m) obj-$(CONFIG_DAX) += dax.o -- 2.9.5

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[PATCH openEuler-1.0-LTS] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by Laibin Qiu 20 Jan '22

20 Jan '22

phytium inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4RK58 CVE: NA -------------------------------- The system would hang up when the Phytium S2500 communicates with some BMCs after several rounds of transactions, unless we reset the controller timeout counter manually by calling firmware through SMC. Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> #openEuler_contributor Signed-off-by: Laibin Qiu <qiulaibin(a)huawei.com> --- drivers/char/ipmi/ipmi_si_mem_io.c | 117 ++++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 4 deletions(-) diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c index 75583612ab10..73a3d6979eaa 100644 --- a/drivers/char/ipmi/ipmi_si_mem_io.c +++ b/drivers/char/ipmi/ipmi_si_mem_io.c @@ -3,6 +3,105 @@ #include <linux/io.h> #include "ipmi_si.h" +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 +#include <linux/arm-smccc.h> + +#define CTL_RST_FUNC_ID 0xC2000011 + +static void ctl_smc(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3) +{ + struct arm_smccc_res res; + + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); + if (res.a0 != 0) + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", + (int)res.a0, arg2); +} + +static void ctl_timeout_reset(void) +{ + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); +} + +static unsigned char intf_mem_inb_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return readb((io->addr)+(offset * io->regspacing)); +} + +static unsigned char intf_mem_inw_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) + & 0xff; +} + +static unsigned char intf_mem_inl_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) + & 0xff; +} + +static unsigned char mem_inq_2500(const struct si_sm_io *io, + unsigned int offset) +{ + ctl_timeout_reset(); + + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) + & 0xff; +} +#else +#define intf_mem_inb_2500 intf_mem_inb +#define intf_mem_inw_2500 intf_mem_inw +#define intf_mem_inl_2500 intf_mem_inl +#define mem_inq_2500 mem_inq +#endif + +static bool apply_phytium2500_workaround; + +#ifdef CONFIG_ACPI +struct ipmi_workaround_oem_info { + char oem_id[ACPI_OEM_ID_SIZE + 1]; +}; + +static struct ipmi_workaround_oem_info wa_info[] = { + { + .oem_id = "KPSVVJ", + } +}; + +static void ipmi_check_phytium_workaround(void) +{ + struct acpi_table_header tbl; + int i; + + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) + return; + + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) + continue; + + apply_phytium2500_workaround = true; + break; + } +} +#else +static void ipmi_check_phytium_workaround(void) +{ + apply_phytium2500_workaround = false; +} +#endif + static unsigned char intf_mem_inb(const struct si_sm_io *io, unsigned int offset) { @@ -81,26 +180,36 @@ int ipmi_si_mem_setup(struct si_sm_io *io) if (!addr) return -ENODEV; + ipmi_check_phytium_workaround(); + /* * Figure out the actual readb/readw/readl/etc routine to use based * upon the register size. */ switch (io->regsize) { case 1: - io->inputb = intf_mem_inb; + io->inputb = apply_phytium2500_workaround ? + intf_mem_inb_2500 : + intf_mem_inb; io->outputb = intf_mem_outb; break; case 2: - io->inputb = intf_mem_inw; + io->inputb = apply_phytium2500_workaround ? + intf_mem_inw_2500 : + intf_mem_inw; io->outputb = intf_mem_outw; break; case 4: - io->inputb = intf_mem_inl; + io->inputb = apply_phytium2500_workaround ? + intf_mem_inl_2500 : + intf_mem_inl; io->outputb = intf_mem_outl; break; #ifdef readq case 8: - io->inputb = mem_inq; + io->inputb = apply_phytium2500_workaround ? + mem_inq_2500 : + mem_inq; io->outputb = mem_outq; break; #endif -- 2.22.0

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[PATCH openEuler-5.10 01/22] perf vendor events amd: Add Zen3 events
by Zheng Zengkai 20 Jan '22

20 Jan '22

From: Smita Koralahalli <Smita.KoralahalliChannabasappa(a)amd.com> mainline inclusion from mainline-v5.13-rc1 commit da66658638c947cab0fb157289f03698453ff8d5 category: feature feature: milan cpu bugzilla: https://gitee.com/openeuler/kernel/issues/I4OBEH?from=project-issue CVE: NA -------------------------------- Add PMU events for AMD Zen3 processors as documented in the AMD Processor Programming Reference for Family 19h and Model 01h [1]. Below are the events which are new on Zen3: PMCx041 ls_mab_alloc.{all_allocations|hardware_prefetcher_allocations|load_store_allocations} PMCx043 ls_dmnd_fills_from_sys.ext_cache_local PMCx044 ls_any_fills_from_sys.{mem_io_remote|ext_cache_remote|mem_io_local|ext_cache_local|int_cache|lcl_l2} PMCx047 ls_misal_loads.{ma4k|ma64} PMCx059 ls_sw_pf_dc_fills.ext_cache_local PMCx05a ls_hw_pf_dc_fills.ext_cache_local PMCx05f ls_alloc_mab_count PMCx085 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k PMCx0ab de_dis_cops_from_decoder.disp_op_type.{any_integer_dispatch|any_fp_dispatch} PMCx0cc ex_ret_ind_brch_instr PMCx18e ic_tag_hit_miss.{all_instruction_cache_accesses|instruction_cache_miss|instruction_cache_hit} PMCx1c7 ex_ret_msprd_brnch_instr_dir_msmtch PMCx28f op_cache_hit_miss.{all_op_cache_accesses|op_cache_miss|op_cache_hit} Section 2.1.17.2 "Performance Measurement" of "PPR for AMD Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, 2021." lists new metrics. Add them. Preserve the events for Zen3 if they are measurable and non-zero as taken from Zen2 directory even if the PPR of Zen3 [1] omits them. Those events are the following: PMCx000 fpu_pipe_assignment.{total|total0|total1|total2|total3} PMCx004 fp_num_mov_elim_scal_op.{optimized|opt_potential|sse_mov_ops_elim|sse_mov_ops} PMCx02D ls_rdtsc PMCx040 ls_dc_accesses PMCx046 ls_tablewalker.{iside|ic_type1|ic_type0|dside|dc_type1|dc_type0} PMCx061 l2_request_g2.{group1|ls_rd_sized|ls_rd_sized_nc|ic_rd_sized|ic_rd_sized_nc|smc_inval|bus_lock_originator|bus_locks_responses} PMCx062 l2_latency.l2_cycles_waiting_on_fills PMCx063 l2_wcb_req.{wcb_write|wcb_close|zero_byte_store|cl_zero} PMCx06d l2_fill_pending.l2_fill_busy PMCx080 ic_fw32 PMCx081 ic_fw32_miss PMCx086 bp_snp_re_sync PMCx087 ic_fetch_stall.{ic_stall_any|ic_stall_dq_empty|ic_stall_back_pressure} PMCx08a bp_l1_btb_correct PMCx08c ic_cache_inval.{l2_invalidating_probe|fill_invalidated} PMCx099 bp_tlb_rel PMCx0a9 de_dis_uop_queue_empty_di0 PMCx0c7 ex_ret_brn_resync PMCx28a ic_oc_mode_switch.{oc_ic_mode_switch|ic_oc_mode_switch} L3PMCx01 l3_request_g1.caching_l3_cache_accesses L3PMCx06 l3_comb_clstr_state.{other_l3_miss_typs|request_miss} [1] Processor Programming Reference (PPR) for AMD Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, 2021. [2] Processor Programming Reference (PPR) for AMD Family 17h Model 71h, Revision B0 Processors, 56176 Rev 3.06 - Jul 17, 2019. [3] Processor Programming Reference (PPR) for AMD Family 17h Models 01h,08h, Revision B2 Processors, 54945 Rev 3.03 - Jun 14, 2019. All of the PPRs can be found at: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Robert Richter <rrichter(a)amd.com> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa(a)amd.com> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Ian Rogers <irogers(a)google.com> Cc: Ingo Molnar <mingo(a)redhat.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Kim Phillips <kim.phillips(a)amd.com> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Martin Liška <mliska(a)suse.cz> Cc: Michael Petlan <mpetlan(a)redhat.com> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Vijay Thakkar <vijaythakkar(a)me.com> Cc: linux-perf-users(a)vger.kernel.org Link: https://lore.kernel.org/r/20210406215944.113332-5-Smita.KoralahalliChannaba… Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> Reviewed-by: Yang Jihong <yangjihong1(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- .../pmu-events/arch/x86/amdzen3/branch.json | 53 +++ .../pmu-events/arch/x86/amdzen3/cache.json | 402 ++++++++++++++++ .../pmu-events/arch/x86/amdzen3/core.json | 137 ++++++ .../arch/x86/amdzen3/data-fabric.json | 98 ++++ .../arch/x86/amdzen3/floating-point.json | 139 ++++++ .../pmu-events/arch/x86/amdzen3/memory.json | 428 ++++++++++++++++++ .../pmu-events/arch/x86/amdzen3/other.json | 103 +++++ .../arch/x86/amdzen3/recommended.json | 214 +++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 9 files changed, 1575 insertions(+), 1 deletion(-) create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/branch.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/core.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/other.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen3/recommended.json diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/branch.json b/tools/perf/pmu-events/arch/x86/amdzen3/branch.json new file mode 100644 index 000000000000..018a7fe94fb9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/branch.json @@ -0,0 +1,53 @@ +[ + { + "EventName": "bp_l1_btb_correct", + "EventCode": "0x8a", + "BriefDescription": "L1 Branch Prediction Overrides Existing Prediction (speculative)." + }, + { + "EventName": "bp_l2_btb_correct", + "EventCode": "0x8b", + "BriefDescription": "L2 Branch Prediction Overrides Existing Prediction (speculative)." + }, + { + "EventName": "bp_dyn_ind_pred", + "EventCode": "0x8e", + "BriefDescription": "Dynamic Indirect Predictions.", + "PublicDescription": "The number of times a branch used the indirect predictor to make a prediction." + }, + { + "EventName": "bp_de_redirect", + "EventCode": "0x91", + "BriefDescription": "Decode Redirects", + "PublicDescription": "The number of times the instruction decoder overrides the predicted target." + }, + { + "EventName": "bp_l1_tlb_fetch_hit", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.", + "UMask": "0xff" + }, + { + "EventName": "bp_l1_tlb_fetch_hit.if1g", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size).", + "UMask": "0x04" + }, + { + "EventName": "bp_l1_tlb_fetch_hit.if2m", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size).", + "UMask": "0x02" + }, + { + "EventName": "bp_l1_tlb_fetch_hit.if4k", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size).", + "UMask": "0x01" + }, + { + "EventName": "bp_tlb_rel", + "EventCode": "0x99", + "BriefDescription": "The number of ITLB reload requests." + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/cache.json b/tools/perf/pmu-events/arch/x86/amdzen3/cache.json new file mode 100644 index 000000000000..fa1d7499a2e3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/cache.json @@ -0,0 +1,402 @@ +[ + { + "EventName": "l2_request_g1.rd_blk_l", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch).", + "UMask": "0x80" + }, + { + "EventName": "l2_request_g1.rd_blk_x", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", + "UMask": "0x40" + }, + { + "EventName": "l2_request_g1.ls_rd_blk_c_s", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", + "UMask": "0x20" + }, + { + "EventName": "l2_request_g1.cacheable_ic_read", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", + "UMask": "0x10" + }, + { + "EventName": "l2_request_g1.change_to_x", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state.", + "UMask": "0x08" + }, + { + "EventName": "l2_request_g1.prefetch_l2_cmd", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", + "UMask": "0x04" + }, + { + "EventName": "l2_request_g1.l2_hw_pf", + "EventCode": "0x60", + "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event.", + "UMask": "0x02" + }, + { + "EventName": "l2_request_g1.group2", + "EventCode": "0x60", + "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).", + "UMask": "0x01" + }, + { + "EventName": "l2_request_g1.all_no_prefetch", + "EventCode": "0x60", + "UMask": "0xf9" + }, + { + "EventName": "l2_request_g2.group1", + "EventCode": "0x61", + "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g1 (PMCx060).", + "UMask": "0x80" + }, + { + "EventName": "l2_request_g2.ls_rd_sized", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", + "UMask": "0x40" + }, + { + "EventName": "l2_request_g2.ls_rd_sized_nc", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", + "UMask": "0x20" + }, + { + "EventName": "l2_request_g2.ic_rd_sized", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", + "UMask": "0x10" + }, + { + "EventName": "l2_request_g2.ic_rd_sized_nc", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", + "UMask": "0x08" + }, + { + "EventName": "l2_request_g2.smc_inval", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.", + "UMask": "0x04" + }, + { + "EventName": "l2_request_g2.bus_locks_originator", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.", + "UMask": "0x02" + }, + { + "EventName": "l2_request_g2.bus_locks_responses", + "EventCode": "0x61", + "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.", + "UMask": "0x01" + }, + { + "EventName": "l2_latency.l2_cycles_waiting_on_fills", + "EventCode": "0x62", + "BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.", + "UMask": "0x01" + }, + { + "EventName": "l2_wcb_req.wcb_write", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests.", + "UMask": "0x40" + }, + { + "EventName": "l2_wcb_req.wcb_close", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests.", + "UMask": "0x20" + }, + { + "EventName": "l2_wcb_req.zero_byte_store", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests.", + "UMask": "0x04" + }, + { + "EventName": "l2_wcb_req.cl_zero", + "EventCode": "0x63", + "BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests.", + "UMask": "0x01" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_cs", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2", + "UMask": "0x80" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable.", + "UMask": "0x40" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2.", + "UMask": "0x20" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_x", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2.", + "UMask": "0x10" + }, + { + "EventName": "l2_cache_req_stat.ls_rd_blk_c", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses instead.", + "UMask": "0x08" + }, + { + "EventName": "l2_cache_req_stat.ic_fill_hit_x", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2.", + "UMask": "0x04" + }, + { + "EventName": "l2_cache_req_stat.ic_fill_hit_s", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2.", + "UMask": "0x02" + }, + { + "EventName": "l2_cache_req_stat.ic_fill_miss", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss instead.", + "UMask": "0x01" + }, + { + "EventName": "l2_cache_req_stat.ic_access_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.", + "UMask": "0x07" + }, + { + "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).", + "UMask": "0x09" + }, + { + "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).", + "UMask": "0xf6" + }, + { + "EventName": "l2_fill_pending.l2_fill_busy", + "EventCode": "0x6d", + "BriefDescription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2.", + "UMask": "0x01" + }, + { + "EventName": "l2_pf_hit_l2", + "EventCode": "0x70", + "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_hit_l3", + "EventCode": "0x71", + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_l3", + "EventCode": "0x72", + "BriefDescription": "L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.", + "UMask": "0xff" + }, + { + "EventName": "ic_fw32", + "EventCode": "0x80", + "BriefDescription": "The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)." + }, + { + "EventName": "ic_fw32_miss", + "EventCode": "0x81", + "BriefDescription": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag." + }, + { + "EventName": "ic_cache_fill_l2", + "EventCode": "0x82", + "BriefDescription": "Instruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cache." + }, + { + "EventName": "ic_cache_fill_sys", + "EventCode": "0x83", + "BriefDescription": "Instruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cache." + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_hit", + "EventCode": "0x84", + "BriefDescription": "L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB." + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss", + "EventCode": "0x85", + "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs.", + "UMask": "0xff" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced page.", + "UMask": "0x08" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G page.", + "UMask": "0x04" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M page.", + "UMask": "0x02" + }, + { + "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k", + "EventCode": "0x85", + "BriefDescription": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K page.", + "UMask": "0x01" + }, + { + "EventName": "bp_snp_re_sync", + "EventCode": "0x86", + "BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event." + }, + { + "EventName": "ic_fetch_stall.ic_stall_any", + "EventCode": "0x87", + "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).", + "UMask": "0x04" + }, + { + "EventName": "ic_fetch_stall.ic_stall_dq_empty", + "EventCode": "0x87", + "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.", + "UMask": "0x02" + }, + { + "EventName": "ic_fetch_stall.ic_stall_back_pressure", + "EventCode": "0x87", + "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", + "UMask": "0x01" + }, + { + "EventName": "ic_cache_inval.l2_invalidating_probe", + "EventCode": "0x8c", + "BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.", + "UMask": "0x02" + }, + { + "EventName": "ic_cache_inval.fill_invalidated", + "EventCode": "0x8c", + "BriefDescription": "IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.", + "UMask": "0x01" + }, + { + "EventName": "ic_tag_hit_miss.all_instruction_cache_accesses", + "EventCode": "0x18e", + "BriefDescription": "All Instruction Cache Accesses. Counts various IC tag related hit and miss events.", + "UMask": "0x1f" + }, + { + "EventName": "ic_tag_hit_miss.instruction_cache_miss", + "EventCode": "0x18e", + "BriefDescription": "Instruction Cache Miss. Counts various IC tag related hit and miss events.", + "UMask": "0x18" + }, + { + "EventName": "ic_tag_hit_miss.instruction_cache_hit", + "EventCode": "0x18e", + "BriefDescription": "Instruction Cache Hit. Counts various IC tag related hit and miss events.", + "UMask": "0x07" + }, + { + "EventName": "ic_oc_mode_switch.oc_ic_mode_switch", + "EventCode": "0x28a", + "BriefDescription": "OC Mode Switch. OC to IC mode switch.", + "UMask": "0x02" + }, + { + "EventName": "ic_oc_mode_switch.ic_oc_mode_switch", + "EventCode": "0x28a", + "BriefDescription": "OC Mode Switch. IC to OC mode switch.", + "UMask": "0x01" + }, + { + "EventName": "op_cache_hit_miss.all_op_cache_accesses", + "EventCode": "0x28f", + "BriefDescription": "All Op Cache accesses. Counts Op Cache micro-tag hit/miss events", + "UMask": "0x07" + }, + { + "EventName": "op_cache_hit_miss.op_cache_miss", + "EventCode": "0x28f", + "BriefDescription": "Op Cache Miss. Counts Op Cache micro-tag hit/miss events", + "UMask": "0x04" + }, + { + "EventName": "op_cache_hit_miss.op_cache_hit", + "EventCode": "0x28f", + "BriefDescription": "Op Cache Hit. Counts Op Cache micro-tag hit/miss events", + "UMask": "0x03" + }, + { + "EventName": "l3_request_g1.caching_l3_cache_accesses", + "EventCode": "0x01", + "BriefDescription": "Caching: L3 cache accesses", + "UMask": "0x80", + "Unit": "L3PMC" + }, + { + "EventName": "l3_lookup_state.all_l3_req_typs", + "EventCode": "0x04", + "BriefDescription": "All L3 Request Types. All L3 cache Requests", + "UMask": "0xff", + "Unit": "L3PMC" + }, + { + "EventName": "l3_comb_clstr_state.other_l3_miss_typs", + "EventCode": "0x06", + "BriefDescription": "Other L3 Miss Request Types", + "UMask": "0xfe", + "Unit": "L3PMC" + }, + { + "EventName": "l3_comb_clstr_state.request_miss", + "EventCode": "0x06", + "BriefDescription": "L3 cache misses", + "UMask": "0x01", + "Unit": "L3PMC" + }, + { + "EventName": "xi_sys_fill_latency", + "EventCode": "0x90", + "BriefDescription": "L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask.", + "Unit": "L3PMC" + }, + { + "EventName": "xi_ccx_sdp_req1", + "EventCode": "0x9a", + "BriefDescription": "L3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting.", + "UMask": "0xff", + "Unit": "L3PMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/core.json b/tools/perf/pmu-events/arch/x86/amdzen3/core.json new file mode 100644 index 000000000000..4e27a2be359e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/core.json @@ -0,0 +1,137 @@ +[ + { + "EventName": "ex_ret_instr", + "EventCode": "0xc0", + "BriefDescription": "Retired Instructions." + }, + { + "EventName": "ex_ret_ops", + "EventCode": "0xc1", + "BriefDescription": "Retired Ops. Use macro_ops_retired instead.", + "PublicDescription": "The number of macro-ops retired." + }, + { + "EventName": "ex_ret_brn", + "EventCode": "0xc2", + "BriefDescription": "Retired Branch Instructions.", + "PublicDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts." + }, + { + "EventName": "ex_ret_brn_misp", + "EventCode": "0xc3", + "BriefDescription": "Retired Branch Instructions Mispredicted.", + "PublicDescription": "The number of retired branch instructions, that were mispredicted." + }, + { + "EventName": "ex_ret_brn_tkn", + "EventCode": "0xc4", + "BriefDescription": "Retired Taken Branch Instructions.", + "PublicDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts." + }, + { + "EventName": "ex_ret_brn_tkn_misp", + "EventCode": "0xc5", + "BriefDescription": "Retired Taken Branch Instructions Mispredicted.", + "PublicDescription": "The number of retired taken branch instructions that were mispredicted." + }, + { + "EventName": "ex_ret_brn_far", + "EventCode": "0xc6", + "BriefDescription": "Retired Far Control Transfers.", + "PublicDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction." + }, + { + "EventName": "ex_ret_brn_resync", + "EventCode": "0xc7", + "BriefDescription": "Retired Branch Resyncs.", + "PublicDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare." + }, + { + "EventName": "ex_ret_near_ret", + "EventCode": "0xc8", + "BriefDescription": "Retired Near Returns.", + "PublicDescription": "The number of near return instructions (RET or RET Iw) retired." + }, + { + "EventName": "ex_ret_near_ret_mispred", + "EventCode": "0xc9", + "BriefDescription": "Retired Near Returns Mispredicted.", + "PublicDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction." + }, + { + "EventName": "ex_ret_brn_ind_misp", + "EventCode": "0xca", + "BriefDescription": "Retired Indirect Branch Instructions Mispredicted.", + "PublicDescription": "The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted." + }, + { + "EventName": "ex_ret_mmx_fp_instr.sse_instr", + "EventCode": "0xcb", + "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).", + "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS.", + "UMask": "0x04" + }, + { + "EventName": "ex_ret_mmx_fp_instr.mmx_instr", + "EventCode": "0xcb", + "BriefDescription": "MMX instructions.", + "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.", + "UMask": "0x02" + }, + { + "EventName": "ex_ret_mmx_fp_instr.x87_instr", + "EventCode": "0xcb", + "BriefDescription": "x87 instructions.", + "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.", + "UMask": "0x01" + }, + { + "EventName": "ex_ret_ind_brch_instr", + "EventCode": "0xcc", + "BriefDescription": "Retired Indirect Branch Instructions. The number of indirect branches retired." + }, + { + "EventName": "ex_ret_cond", + "EventCode": "0xd1", + "BriefDescription": "Retired Conditional Branch Instructions." + }, + { + "EventName": "ex_div_busy", + "EventCode": "0xd3", + "BriefDescription": "Div Cycles Busy count." + }, + { + "EventName": "ex_div_count", + "EventCode": "0xd4", + "BriefDescription": "Div Op Count." + }, + { + "EventName": "ex_ret_msprd_brnch_instr_dir_msmtch", + "EventCode": "0x1c7", + "BriefDescription": "Retired Mispredicted Branch Instructions due to Direction Mismatch", + "PublicDescription": "The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch." + }, + { + "EventName": "ex_tagged_ibs_ops.ibs_count_rollover", + "EventCode": "0x1cf", + "BriefDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.", + "UMask": "0x04" + }, + { + "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret", + "EventCode": "0x1cf", + "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.", + "UMask": "0x02" + }, + { + "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops", + "EventCode": "0x1cf", + "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.", + "UMask": "0x01" + }, + { + "EventName": "ex_ret_fused_instr", + "EventCode": "0x1d0", + "BriefDescription": "Counts retired Fused Instructions." + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json b/tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json new file mode 100644 index 000000000000..40271df40015 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/data-fabric.json @@ -0,0 +1,98 @@ +[ + { + "EventName": "remote_outbound_data_controller_0", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0", + "EventCode": "0x7c7", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "remote_outbound_data_controller_1", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1", + "EventCode": "0x807", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "remote_outbound_data_controller_2", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2", + "EventCode": "0x847", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "remote_outbound_data_controller_3", + "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3", + "EventCode": "0x887", + "UMask": "0x02", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_0", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x07", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_1", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x47", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_2", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x87", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_3", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0xc7", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_4", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x107", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_5", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x147", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_6", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x187", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + }, + { + "EventName": "dram_channel_data_controller_7", + "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0", + "EventCode": "0x1c7", + "UMask": "0x38", + "PerPkg": "1", + "Unit": "DFPMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json b/tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json new file mode 100644 index 000000000000..98cfcb9c78ec --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/floating-point.json @@ -0,0 +1,139 @@ +[ + { + "EventName": "fpu_pipe_assignment.total", + "EventCode": "0x00", + "BriefDescription": "Total number of fp uOps.", + "PublicDescription": "Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS.", + "UMask": "0x0f" + }, + { + "EventName": "fpu_pipe_assignment.total3", + "EventCode": "0x00", + "BriefDescription": "Total number uOps assigned to pipe 3.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3.", + "UMask": "0x08" + }, + { + "EventName": "fpu_pipe_assignment.total2", + "EventCode": "0x00", + "BriefDescription": "Total number uOps assigned to pipe 2.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2.", + "UMask": "0x04" + }, + { + "EventName": "fpu_pipe_assignment.total1", + "EventCode": "0x00", + "BriefDescription": "Total number uOps assigned to pipe 1.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1.", + "UMask": "0x02" + }, + { + "EventName": "fpu_pipe_assignment.total0", + "EventCode": "0x00", + "BriefDescription": "Total number of fp uOps on pipe 0.", + "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0.", + "UMask": "0x01" + }, + { + "EventName": "fp_ret_sse_avx_ops.all", + "EventCode": "0x03", + "BriefDescription": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.", + "UMask": "0xff" + }, + { + "EventName": "fp_ret_sse_avx_ops.mac_flops", + "EventCode": "0x03", + "BriefDescription": "Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x08" + }, + { + "EventName": "fp_ret_sse_avx_ops.div_flops", + "EventCode": "0x03", + "BriefDescription": "Divide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x04" + }, + { + "EventName": "fp_ret_sse_avx_ops.mult_flops", + "EventCode": "0x03", + "BriefDescription": "Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x02" + }, + { + "EventName": "fp_ret_sse_avx_ops.add_sub_flops", + "EventCode": "0x03", + "BriefDescription": "Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.", + "UMask": "0x01" + }, + { + "EventName": "fp_num_mov_elim_scal_op.optimized", + "EventCode": "0x04", + "BriefDescription": "Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x08" + }, + { + "EventName": "fp_num_mov_elim_scal_op.opt_potential", + "EventCode": "0x04", + "BriefDescription": "Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x04" + }, + { + "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops_elim", + "EventCode": "0x04", + "BriefDescription": "Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x02" + }, + { + "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops", + "EventCode": "0x04", + "BriefDescription": "Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.", + "UMask": "0x01" + }, + { + "EventName": "fp_retired_ser_ops.sse_bot_ret", + "EventCode": "0x05", + "BriefDescription": "SSE/AVX bottom-executing ops retired. The number of serializing Ops retired.", + "UMask": "0x08" + }, + { + "EventName": "fp_retired_ser_ops.sse_ctrl_ret", + "EventCode": "0x05", + "BriefDescription": "SSE/AVX control word mispredict traps. The number of serializing Ops retired.", + "UMask": "0x04" + }, + { + "EventName": "fp_retired_ser_ops.x87_bot_ret", + "EventCode": "0x05", + "BriefDescription": "x87 bottom-executing ops retired. The number of serializing Ops retired.", + "UMask": "0x02" + }, + { + "EventName": "fp_retired_ser_ops.x87_ctrl_ret", + "EventCode": "0x05", + "BriefDescription": "x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired.", + "UMask": "0x01" + }, + { + "EventName": "fp_disp_faults.ymm_spill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. YMM spill fault.", + "UMask": "0x08" + }, + { + "EventName": "fp_disp_faults.ymm_fill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. YMM fill fault.", + "UMask": "0x04" + }, + { + "EventName": "fp_disp_faults.xmm_fill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. XMM fill fault.", + "UMask": "0x02" + }, + { + "EventName": "fp_disp_faults.x87_fill_fault", + "EventCode": "0x0e", + "BriefDescription": "Floating Point Dispatch Faults. x87 fill fault.", + "UMask": "0x01" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/memory.json b/tools/perf/pmu-events/arch/x86/amdzen3/memory.json new file mode 100644 index 000000000000..a2833955dcd2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/memory.json @@ -0,0 +1,428 @@ +[ + { + "EventName": "ls_bad_status2.stli_other", + "EventCode": "0x24", + "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.", + "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.", + "UMask": "0x02" + }, + { + "EventName": "ls_locks.spec_lock_hi_spec", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.", + "UMask": "0x08" + }, + { + "EventName": "ls_locks.spec_lock_lo_spec", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.", + "UMask": "0x04" + }, + { + "EventName": "ls_locks.non_spec_lock", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", + "UMask": "0x02" + }, + { + "EventName": "ls_locks.bus_lock", + "EventCode": "0x25", + "BriefDescription": "Retired lock instructions. Comparable to legacy bus lock.", + "UMask": "0x01" + }, + { + "EventName": "ls_ret_cl_flush", + "EventCode": "0x26", + "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." + }, + { + "EventName": "ls_ret_cpuid", + "EventCode": "0x27", + "BriefDescription": "The number of CPUID instructions retired." + }, + { + "EventName": "ls_dispatch.ld_st_dispatch", + "EventCode": "0x29", + "BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", + "UMask": "0x04" + }, + { + "EventName": "ls_dispatch.store_dispatch", + "EventCode": "0x29", + "BriefDescription": "Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", + "UMask": "0x02" + }, + { + "EventName": "ls_dispatch.ld_dispatch", + "EventCode": "0x29", + "BriefDescription": "Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.", + "UMask": "0x01" + }, + { + "EventName": "ls_smi_rx", + "EventCode": "0x2b", + "BriefDescription": "Counts the number of SMIs received." + }, + { + "EventName": "ls_int_taken", + "EventCode": "0x2c", + "BriefDescription": "Counts the number of interrupts taken." + }, + { + "EventName": "ls_rdtsc", + "EventCode": "0x2d", + "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative." + }, + { + "EventName": "ls_stlf", + "EventCode": "0x35", + "BriefDescription": "Number of STLF hits." + }, + { + "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full", + "EventCode": "0x37", + "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", + "UMask": "0x01" + }, + { + "EventName": "ls_dc_accesses", + "EventCode": "0x40", + "BriefDescription": "Number of accesses to the dcache for load/store references.", + "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event." + }, + { + "EventName": "ls_mab_alloc.all_allocations", + "EventCode": "0x41", + "BriefDescription": "All Allocations. Counts when a LS pipe allocates a MAB entry.", + "UMask": "0x7f" + }, + { + "EventName": "ls_mab_alloc.hardware_prefetcher_allocations", + "EventCode": "0x41", + "BriefDescription": "Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry.", + "UMask": "0x40" + }, + { + "EventName": "ls_mab_alloc.load_store_allocations", + "EventCode": "0x41", + "BriefDescription": "Load Store Allocations. Counts when a LS pipe allocates a MAB entry.", + "UMask": "0x3f" + }, + { + "EventName": "ls_mab_alloc.dc_prefetcher", + "EventCode": "0x41", + "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.", + "UMask": "0x08" + }, + { + "EventName": "ls_mab_alloc.stores", + "EventCode": "0x41", + "BriefDescription": "LS MAB Allocates by Type. Stores.", + "UMask": "0x02" + }, + { + "EventName": "ls_mab_alloc.loads", + "EventCode": "0x41", + "BriefDescription": "LS MAB Allocates by Type. Loads.", + "UMask": "0x01" + }, + { + "EventName": "ls_dmnd_fills_from_sys.mem_io_remote", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_dmnd_fills_from_sys.ext_cache_remote", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_dmnd_fills_from_sys.mem_io_local", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_dmnd_fills_from_sys.ext_cache_local", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_dmnd_fills_from_sys.int_cache", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_dmnd_fills_from_sys.lcl_l2", + "EventCode": "0x43", + "BriefDescription": "Demand Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_any_fills_from_sys.mem_io_remote", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_any_fills_from_sys.ext_cache_remote", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_any_fills_from_sys.mem_io_local", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_any_fills_from_sys.ext_cache_local", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_any_fills_from_sys.int_cache", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_any_fills_from_sys.lcl_l2", + "EventCode": "0x44", + "BriefDescription": "Any Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_l1_d_tlb_miss.all", + "EventCode": "0x45", + "BriefDescription": "All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead.", + "UMask": "0xff" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB.", + "UMask": "0x80" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB.", + "UMask": "0x40" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB.", + "UMask": "0x20" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB.", + "UMask": "0x10" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.", + "UMask": "0x08" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.", + "UMask": "0x04" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB.", + "UMask": "0x02" + }, + { + "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.", + "UMask": "0x01" + }, + { + "EventName": "ls_tablewalker.iside", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks on I-side.", + "UMask": "0x0c" + }, + { + "EventName": "ls_tablewalker.ic_type1", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks IC Type 1.", + "UMask": "0x08" + }, + { + "EventName": "ls_tablewalker.ic_type0", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks IC Type 0.", + "UMask": "0x04" + }, + { + "EventName": "ls_tablewalker.dside", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks on D-side.", + "UMask": "0x03" + }, + { + "EventName": "ls_tablewalker.dc_type1", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks DC Type 1.", + "UMask": "0x02" + }, + { + "EventName": "ls_tablewalker.dc_type0", + "EventCode": "0x46", + "BriefDescription": "Total Page Table Walks DC Type 0.", + "UMask": "0x01" + }, + { + "EventName": "ls_misal_loads.ma4k", + "EventCode": "0x47", + "BriefDescription": "The number of 4KB misaligned (i.e., page crossing) loads.", + "UMask": "0x02" + }, + { + "EventName": "ls_misal_loads.ma64", + "EventCode": "0x47", + "BriefDescription": "The number of 64B misaligned (i.e., cacheline crossing) loads.", + "UMask": "0x01" + }, + { + "EventName": "ls_pref_instr_disp", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).", + "UMask": "0xff" + }, + { + "EventName": "ls_pref_instr_disp.prefetch_nta", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.", + "UMask": "0x04" + }, + { + "EventName": "ls_pref_instr_disp.prefetch_w", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW.", + "UMask": "0x02" + }, + { + "EventName": "ls_pref_instr_disp.prefetch", + "EventCode": "0x4b", + "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.", + "UMask": "0x01" + }, + { + "EventName": "ls_inef_sw_pref.mab_mch_cnt", + "EventCode": "0x52", + "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.", + "UMask": "0x02" + }, + { + "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit", + "EventCode": "0x52", + "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.", + "UMask": "0x01" + }, + { + "EventName": "ls_sw_pf_dc_fills.mem_io_remote", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_sw_pf_dc_fills.ext_cache_remote", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_sw_pf_dc_fills.mem_io_local", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_sw_pf_dc_fills.ext_cache_local", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_sw_pf_dc_fills.int_cache", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_sw_pf_dc_fills.lcl_l2", + "EventCode": "0x59", + "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_hw_pf_dc_fills.mem_io_remote", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.", + "UMask": "0x40" + }, + { + "EventName": "ls_hw_pf_dc_fills.ext_cache_remote", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.", + "UMask": "0x10" + }, + { + "EventName": "ls_hw_pf_dc_fills.mem_io_local", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.", + "UMask": "0x08" + }, + { + "EventName": "ls_hw_pf_dc_fills.ext_cache_local", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.", + "UMask": "0x04" + }, + { + "EventName": "ls_hw_pf_dc_fills.int_cache", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.", + "UMask": "0x02" + }, + { + "EventName": "ls_hw_pf_dc_fills.lcl_l2", + "EventCode": "0x5a", + "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core.", + "UMask": "0x01" + }, + { + "EventName": "ls_alloc_mab_count", + "EventCode": "0x5f", + "BriefDescription": "Count of Allocated Mabs", + "PublicDescription": "This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]." + }, + { + "EventName": "ls_not_halted_cyc", + "EventCode": "0x76", + "BriefDescription": "Cycles not in Halt." + }, + { + "EventName": "ls_tlb_flush.all_tlb_flushes", + "EventCode": "0x78", + "BriefDescription": "All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead", + "UMask": "0xff" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/other.json b/tools/perf/pmu-events/arch/x86/amdzen3/other.json new file mode 100644 index 000000000000..7da5d0791ea3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/other.json @@ -0,0 +1,103 @@ +[ + { + "EventName": "de_dis_uop_queue_empty_di0", + "EventCode": "0xa9", + "BriefDescription": "Cycles where the Micro-Op Queue is empty." + }, + { + "EventName": "de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch", + "EventCode": "0xab", + "BriefDescription": "Any Integer dispatch. Types of Oops Dispatched from Decoder.", + "UMask": "0x08" + }, + { + "EventName": "de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch", + "EventCode": "0xab", + "BriefDescription": "Any FP dispatch. Types of Oops Dispatched from Decoder.", + "UMask": "0x04" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.fp_flush_recovery_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stall.", + "UMask": "0x80" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP scheduler.", + "UMask": "0x40" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination register.", + "UMask": "0x20" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stall.", + "UMask": "0x10" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.int_sched_misc_token_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall.", + "UMask": "0x08" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.store_queue_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semantics.", + "UMask": "0x04" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.load_queue_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semantics.", + "UMask": "0x02" + }, + { + "EventName": "de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall", + "EventCode": "0xae", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register.", + "UMask": "0x01" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.retire_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens available.", + "UMask": "0x20" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.agsq_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.", + "UMask": "0x10" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch3_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 available.", + "UMask": "0x08" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch2_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 available.", + "UMask": "0x04" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch1_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 available.", + "UMask": "0x02" + }, + { + "EventName": "de_dis_dispatch_token_stalls2.int_sch0_token_stall", + "EventCode": "0xaf", + "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 available.", + "UMask": "0x01" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen3/recommended.json b/tools/perf/pmu-events/arch/x86/amdzen3/recommended.json new file mode 100644 index 000000000000..988cf68ae825 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen3/recommended.json @@ -0,0 +1,214 @@ +[ + { + "MetricName": "branch_misprediction_ratio", + "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", + "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)", + "MetricGroup": "branch_prediction", + "ScaleUnit": "100%" + }, + { + "EventName": "all_data_cache_accesses", + "EventCode": "0x29", + "BriefDescription": "All L1 Data Cache Accesses", + "UMask": "0x07" + }, + { + "MetricName": "all_l2_cache_accesses", + "BriefDescription": "All L2 Cache Accesses", + "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "EventName": "l2_cache_accesses_from_ic_misses", + "EventCode": "0x60", + "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", + "UMask": "0x10" + }, + { + "EventName": "l2_cache_accesses_from_dc_misses", + "EventCode": "0x60", + "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", + "UMask": "0xe8" + }, + { + "MetricName": "l2_cache_accesses_from_l2_hwpf", + "BriefDescription": "L2 Cache Accesses from L2 HWPF", + "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "MetricName": "all_l2_cache_misses", + "BriefDescription": "All L2 Cache Misses", + "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "EventName": "l2_cache_misses_from_ic_miss", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", + "UMask": "0x01" + }, + { + "EventName": "l2_cache_misses_from_dc_misses", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", + "UMask": "0x08" + }, + { + "MetricName": "l2_cache_misses_from_l2_hwpf", + "BriefDescription": "L2 Cache Misses from L2 Cache HWPF", + "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", + "MetricGroup": "l2_cache" + }, + { + "MetricName": "all_l2_cache_hits", + "BriefDescription": "All L2 Cache Hits", + "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2", + "MetricGroup": "l2_cache" + }, + { + "EventName": "l2_cache_hits_from_ic_misses", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", + "UMask": "0x06" + }, + { + "EventName": "l2_cache_hits_from_dc_misses", + "EventCode": "0x64", + "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", + "UMask": "0xf0" + }, + { + "EventName": "l2_cache_hits_from_l2_hwpf", + "EventCode": "0x70", + "BriefDescription": "L2 Cache Hits from L2 Cache HWPF", + "UMask": "0xff" + }, + { + "EventName": "l3_cache_accesses", + "EventCode": "0x04", + "BriefDescription": "L3 Cache Accesses", + "UMask": "0xff", + "Unit": "L3PMC" + }, + { + "EventName": "l3_misses", + "EventCode": "0x04", + "BriefDescription": "L3 Misses (includes cacheline state change requests)", + "UMask": "0x01", + "Unit": "L3PMC" + }, + { + "MetricName": "l3_read_miss_latency", + "BriefDescription": "Average L3 Read Miss Latency (in core clocks)", + "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1", + "MetricGroup": "l3_cache", + "ScaleUnit": "1core clocks" + }, + { + "MetricName": "op_cache_fetch_miss_ratio", + "BriefDescription": "Op Cache (64B) Fetch Miss Ratio", + "MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)", + "MetricGroup": "l2_cache" + }, + { + "MetricName": "ic_fetch_miss_ratio", + "BriefDescription": "Instruction Cache (32B) Fetch Miss Ratio", + "MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)", + "MetricGroup": "l2_cache", + "ScaleUnit": "100%" + }, + { + "EventName": "l1_data_cache_fills_from_memory", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From Memory", + "UMask": "0x48" + }, + { + "EventName": "l1_data_cache_fills_from_remote_node", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From Remote Node", + "UMask": "0x50" + }, + { + "EventName": "l1_data_cache_fills_from_within_same_ccx", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From within same CCX", + "UMask": "0x03" + }, + { + "EventName": "l1_data_cache_fills_from_external_ccx_cache", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: From External CCX Cache", + "UMask": "0x14" + }, + { + "EventName": "l1_data_cache_fills_all", + "EventCode": "0x44", + "BriefDescription": "L1 Data Cache Fills: All", + "UMask": "0xff" + }, + { + "MetricName": "l1_itlb_misses", + "BriefDescription": "L1 ITLB Misses", + "MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss", + "MetricGroup": "tlb" + }, + { + "EventName": "l2_itlb_misses", + "EventCode": "0x85", + "BriefDescription": "L2 ITLB Misses & Instruction page walks", + "UMask": "0x07" + }, + { + "EventName": "l1_dtlb_misses", + "EventCode": "0x45", + "BriefDescription": "L1 DTLB Misses", + "UMask": "0xff" + }, + { + "EventName": "l2_dtlb_misses", + "EventCode": "0x45", + "BriefDescription": "L2 DTLB Misses & Data page walks", + "UMask": "0xf0" + }, + { + "EventName": "all_tlbs_flushed", + "EventCode": "0x78", + "BriefDescription": "All TLBs Flushed", + "UMask": "0xff" + }, + { + "MetricName": "macro_ops_dispatched", + "BriefDescription": "Macro-ops Dispatched", + "MetricExpr": "de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch", + "MetricGroup": "decoder" + }, + { + "EventName": "sse_avx_stalls", + "EventCode": "0x0e", + "BriefDescription": "Mixed SSE/AVX Stalls", + "UMask": "0x0e" + }, + { + "EventName": "macro_ops_retired", + "EventCode": "0xc1", + "BriefDescription": "Macro-ops Retired" + }, + { + "MetricName": "all_remote_links_outbound", + "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)", + "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3", + "MetricGroup": "data_fabric", + "PerPkg": "1", + "ScaleUnit": "3e-5MiB" + }, + { + "MetricName": "nps1_die_to_dram", + "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)", + "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7", + "MetricGroup": "data_fabric", + "PerPkg": "1", + "ScaleUnit": "6.1e-5MiB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 2f2a209e87e1..9f97b32533a0 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -38,4 +38,4 @@ GenuineIntel-6-7E,v1,icelake,core GenuineIntel-6-86,v1,tremontx,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core -AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen2,core +AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core -- 2.20.1

1 21

Re: [PATCH] ipmi_si: Phytium S2500 workaround for MMIO-based IPMI
by QiuLaibin 20 Jan '22

20 Jan '22

您好，您的补丁已经提交 CI 进行检查。后续合入进展可以在以下issue下关注 https://gitee.com/openeuler/kernel/issues/I4RK58 谢谢 BR Laibin On 2022/1/20 10:35, Chen Baozi wrote: > phytium inclusion > category: bugfix > bugzilla: NA > CVE: NA > > -------------------------------- > > The system would hang up when the Phytium S2500 communicates with > some BMCs after several rounds of transactions, unless we reset > the controller timeout counter manually by calling firmware through > SMC. > > Signed-off-by: Wang Yinfeng <wangyinfeng(a)phytium.com.cn> > Signed-off-by: Chen Baozi <chenbaozi(a)phytium.com.cn> > --- > drivers/char/ipmi/ipmi_si_mem_io.c | 117 ++++++++++++++++++++++++++++- > 1 file changed, 113 insertions(+), 4 deletions(-) > > diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c > index 75583612ab10..73a3d6979eaa 100644 > --- a/drivers/char/ipmi/ipmi_si_mem_io.c > +++ b/drivers/char/ipmi/ipmi_si_mem_io.c > @@ -3,6 +3,105 @@ > #include <linux/io.h> > #include "ipmi_si.h" > > +#ifdef CONFIG_ARM_GIC_PHYTIUM_2500 > +#include <linux/arm-smccc.h> > + > +#define CTL_RST_FUNC_ID 0xC2000011 > + > +static void ctl_smc(unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(arg0, arg1, arg2, arg3, 0, 0, 0, 0, &res); > + if (res.a0 != 0) > + pr_err("Error: Firmware call SMC reset Failed: %d, addr: 0x%lx\n", > + (int)res.a0, arg2); > +} > + > +static void ctl_timeout_reset(void) > +{ > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x28100208, 0x1); > + ctl_smc(CTL_RST_FUNC_ID, 0x1, 0x2810020C, 0x1); > +} > + > +static unsigned char intf_mem_inb_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return readb((io->addr)+(offset * io->regspacing)); > +} > + > +static unsigned char intf_mem_inw_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readw((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char intf_mem_inl_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readl((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > + > +static unsigned char mem_inq_2500(const struct si_sm_io *io, > + unsigned int offset) > +{ > + ctl_timeout_reset(); > + > + return (readq((io->addr)+(offset * io->regspacing)) >> io->regshift) > + & 0xff; > +} > +#else > +#define intf_mem_inb_2500 intf_mem_inb > +#define intf_mem_inw_2500 intf_mem_inw > +#define intf_mem_inl_2500 intf_mem_inl > +#define mem_inq_2500 mem_inq > +#endif > + > +static bool apply_phytium2500_workaround; > + > +#ifdef CONFIG_ACPI > +struct ipmi_workaround_oem_info { > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > +}; > + > +static struct ipmi_workaround_oem_info wa_info[] = { > + { > + .oem_id = "KPSVVJ", > + } > +}; > + > +static void ipmi_check_phytium_workaround(void) > +{ > + struct acpi_table_header tbl; > + int i; > + > + if (ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_DSDT, 0, &tbl))) > + return; > + > + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { > + if (strncmp(wa_info[i].oem_id, tbl.oem_id, ACPI_OEM_ID_SIZE)) > + continue; > + > + apply_phytium2500_workaround = true; > + break; > + } > +} > +#else > +static void ipmi_check_phytium_workaround(void) > +{ > + apply_phytium2500_workaround = false; > +} > +#endif > + > static unsigned char intf_mem_inb(const struct si_sm_io *io, > unsigned int offset) > { > @@ -81,26 +180,36 @@ int ipmi_si_mem_setup(struct si_sm_io *io) > if (!addr) > return -ENODEV; > > + ipmi_check_phytium_workaround(); > + > /* > * Figure out the actual readb/readw/readl/etc routine to use based > * upon the register size. > */ > switch (io->regsize) { > case 1: > - io->inputb = intf_mem_inb; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inb_2500 : > + intf_mem_inb; > io->outputb = intf_mem_outb; > break; > case 2: > - io->inputb = intf_mem_inw; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inw_2500 : > + intf_mem_inw; > io->outputb = intf_mem_outw; > break; > case 4: > - io->inputb = intf_mem_inl; > + io->inputb = apply_phytium2500_workaround ? > + intf_mem_inl_2500 : > + intf_mem_inl; > io->outputb = intf_mem_outl; > break; > #ifdef readq > case 8: > - io->inputb = mem_inq; > + io->inputb = apply_phytium2500_workaround ? > + mem_inq_2500 : > + mem_inq; > io->outputb = mem_outq; > break; > #endif >

1 0

[PATCH openEuler-1.0-LTS] audit: bugfix for infinite loop when flush the hold queue
by Yang Yingliang 20 Jan '22

20 Jan '22

From: Cui GaoSheng <cuigaosheng1(a)huawei.com> hulk inclusion category: bugfix bugzilla: 186105, https://gitee.com/openeuler/kernel/issues/I4RGWS?from=project-issue CVE: NA ----------------------------------------------------------------- When we add "audit=1" to the cmdline, if we keep the audit_hold_queue non-empty, flush the hold queue will fall into an infinite loop. So we need to fix it by stoping flush the hold queue when netlink abnormal. Fixes: 3413ddc91e02a ("audit: improve robustness of the audit queue handling") Signed-off-by: Cui GaoSheng <cuigaosheng1(a)huawei.com> Reviewed-by: Xiu Jianfeng <xiujianfeng(a)huawei.com> Reviewed-by: weiyang wang <wangweiyang2(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- kernel/audit.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/kernel/audit.c b/kernel/audit.c index c5e034fe14bbb..3de5ebb945592 100644 --- a/kernel/audit.c +++ b/kernel/audit.c @@ -740,6 +740,8 @@ static int kauditd_send_queue(struct sock *sk, u32 portid, if (!sk) { if (err_hook) (*err_hook)(skb); + if (queue == &audit_hold_queue) + goto out; continue; } @@ -756,6 +758,8 @@ static int kauditd_send_queue(struct sock *sk, u32 portid, (*err_hook)(skb); if (rc == -EAGAIN) rc = 0; + if (queue == &audit_hold_queue) + goto out; /* continue to drain the queue */ continue; } else @@ -767,6 +771,7 @@ static int kauditd_send_queue(struct sock *sk, u32 portid, } } +out: return (rc >= 0 ? 0 : rc); } -- 2.25.1

1 0

[PATCH openEuler-1.0-LTS] blk-throttle: enable hierarchical throttle in cgroup v1
by Yang Yingliang 19 Jan '22

19 Jan '22

From: Yu Kuai <yukuai3(a)huawei.com> hulk inclusion category: feature bugzilla: 186072, https://gitee.com/openeuler/kernel/issues/I4RH0V CVE: NA ----------------------------------------------- blkio subsytem is not under default hierarchy in cgroup v1 by default, which means configurations will only be effective on current cgroup for io throttle. This patch introduces a new feature that enable default hierarchy for io throttle, which means configurations will be effective on child cgroups. Such feature is disabled by default, and can be enabled by adding "blkcg_global_limit=1" or "blkcg_global_limit=Y" or "blkcg_global_limit=y" in boot cmd. Signed-off-by: Yu Kuai <yukuai3(a)huawei.com> Reviewed-by: Hou Tao <houtao1(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- block/blk-throttle.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/block/blk-throttle.c b/block/blk-throttle.c index ceeb17104aa82..6b3ced8ae1a5f 100644 --- a/block/blk-throttle.c +++ b/block/blk-throttle.c @@ -43,6 +43,19 @@ static struct blkcg_policy blkcg_policy_throtl; /* A workqueue to queue throttle related work */ static struct workqueue_struct *kthrotld_workqueue; +/* True if global limit is enabled in cgroup v1 */ +static bool global_limit; + +static int __init setup_global_limit(char *str) +{ + if (!strcmp(str, "1") || !strcmp(str, "Y") || !strcmp(str, "y")) + global_limit = true; + + return 1; +} + +__setup("blkcg_global_limit=", setup_global_limit); + /* * To implement hierarchical throttling, throtl_grps form a tree and bios * are dispatched upwards level by level until they reach the top and get @@ -537,7 +550,8 @@ static void throtl_pd_init(struct blkg_policy_data *pd) * regardless of the position of the group in the hierarchy. */ sq->parent_sq = &td->service_queue; - if (cgroup_subsys_on_dfl(io_cgrp_subsys) && blkg->parent) + if ((cgroup_subsys_on_dfl(io_cgrp_subsys) || global_limit) && + blkg->parent) sq->parent_sq = &blkg_to_tg(blkg->parent)->service_queue; tg->td = td; } -- 2.25.1

1 0

[PATCH openEuler-1.0-LTS] xfs: map unwritten blocks in XFS_IOC_{ALLOC,FREE}SP just like fallocate
by Yang Yingliang 19 Jan '22

19 Jan '22

From: "Darrick J. Wong" <djwong(a)kernel.org> mainline inclusion from mainline-v5.16-rc5 commit 983d8e60f50806f90534cc5373d0ce867e5aaf79 category: bugfix bugzilla: 186083 CVE: CVE-2021-4155 Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… -------------------------------- The old ALLOCSP/FREESP ioctls in XFS can be used to preallocate space at the end of files, just like fallocate and RESVSP. Make the behavior consistent with the other ioctls. Reported-by: Kirill Tkhai <ktkhai(a)virtuozzo.com> Signed-off-by: Darrick J. Wong <djwong(a)kernel.org> Signed-off-by: Darrick J. Wong <darrick.wong(a)oracle.com> Reviewed-by: Dave Chinner <dchinner(a)redhat.com> Reviewed-by: Eric Sandeen <sandeen(a)redhat.com> Signed-off-by: Guo Xuenan <guoxuenan(a)huawei.com> Reviewed-by: Zhang Yi <yi.zhang(a)huawei.com> Reviewed-by: Xiu Jianfeng <xiujianfeng(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- fs/xfs/xfs_ioctl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/xfs/xfs_ioctl.c b/fs/xfs/xfs_ioctl.c index 263436977c39e..b6d85da7f3508 100644 --- a/fs/xfs/xfs_ioctl.c +++ b/fs/xfs/xfs_ioctl.c @@ -701,7 +701,8 @@ xfs_ioc_space( flags |= XFS_PREALLOC_CLEAR; if (bf->l_start > XFS_ISIZE(ip)) { error = xfs_alloc_file_space(ip, XFS_ISIZE(ip), - bf->l_start - XFS_ISIZE(ip), 0); + bf->l_start - XFS_ISIZE(ip), + XFS_BMAPI_PREALLOC); if (error) goto out_unlock; } -- 2.25.1

1 0

openEuler 20.03 support AMD Milan
by QiuLaibin 19 Jan '22

19 Jan '22

Hi Liu 感谢您的提交，针对先前提交的AMD适配milan V2相关patch，我们总共有两条意见，麻烦再确认下。 1、Essential下 08ed77e414ab v5.10-rc1 perf vendor events amd: Add recommended events 未合入 2、41cd02c6f7f6：kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID 后向有两个bugfix需要确认 new fix: 36fa06f9ff39 ("KVM: x86: Add support for RDPID without RDTSCP") new fix: 8aec21c04caa ("KVM: VMX: Do not advertise RDPID if ENABLE_RDTSCP control is unsupported") BR Laibin On 2021/12/16 10:27, Jackie Liu wrote: > Hi, ALL > > 附件是加入到 KYLIN 内核的 AMD patch 并且基于欧拉分支 rebase 了一下 > ，head 的创建规则没搞懂，这个脚本好像也不合适，就没有更改。请查收。 > > -- > Jackie Liu > > 在 2021/12/15 上午11:44, Zheng Zengkai 写道: >> #!/bin/sh >> # >> # Usage: >> # >> # prerequisite: >> # The patches to add header should be patches from linux mainline. >> # >> # command: >> # add-openeuler-patch-header.sh commit1..commit2 gitee_issue_url >> # >> # commit1: mainline start commit id; >> # commit2: mainline end commit id >> # gitee_issue_url: for example: >> https://gitee.com/openeuler/kernel/issues/I4MKP4 >> >> # Example: >> # add-openeuler-patch-header.sh afd2ff9b7e1b..8bb7eca972a >> https://gitee.com/openeuler/kernel/issues/I4MKP4 >> # >> >> for p in `ls *.patch` >> do >> if [ $p == "0000-cover-letter.patch" ]; then >> continue >> fi >> >> title=$(sed '/^Subject: \[PATCH .*\]/{N;s/\n / /g}' $p | grep >> -E "^Subject: \[PATCH .*\]" | cut -d ']' -f 2) >> commit=$(git log --pretty=oneline $1 | grep -F "$title" | cut >> -d ' ' -f 1) >> if [ -n "$multi" ]; then >> echo "$p" has multi-commits >> commit="multi" >> continue >> fi >> if [ -z "$commit" ]; then >> echo "$p" commit is null >> commit="null" >> continue >> fi >> >> # find insert line >> i=5 >> while true >> do >> ln=""$i"p" >> sub=`cat $p | sed -n "$ln"` >> i=$(($i+1)) >> if [ -z "$sub" ]; then >> break >> fi >> done >> i=$(($i-1)) >> >> version=`git name-rev $commit | awk -F '[v~^]' '{print $2}'` >> >> sed ""$i"a mainline inclusion\nfrom >> mainline-v$version\ncommit $commit\ncategory: feature\nbugzilla: >> $2\nCVE: NA\n\n--------------------------------\n" -i $p >> done >> > > No virus found > Checked by Hillstone Network AntiVirus >

1 0

[PATCH openEuler-1.0-LTS V2 00/90] Enabling AMD Milan series processor support
by Laibin Qiu 19 Jan '22

19 Jan '22

bugzilla: https://gitee.com/openeuler/kernel/issues/I4MKP4 Babu Moger (1): KVM: SVM: Clear the CR4 register on reset David Edmondson (1): KVM: x86: clflushopt should be treated as a no-op by emulation Fenghua Yu (2): x86/cpufeatures: Enumerate MOVDIRI instruction x86/cpufeatures: Enumerate MOVDIR64B instruction Haiyan Song (2): perf vendor events intel: Add Icelake V1.00 event file perf vendor events intel: Add Tremontx event file v1.02 Isaac Vaughn (1): EDAC/amd64: Add PCI device IDs for family 17h, model 70h Jan H. Schönherr (1): x86/mce: Fix use of uninitialized MCE message string Jim Mattson (1): kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID John Allen (2): kvm/svm: PKU not currently supported x86/microcode/AMD: Increase microcode PATCH_MAX_SIZE Kai Huang (3): kvm: x86: Move kvm_set_mmio_spte_mask() from x86.c to mmu.c kvm: x86: Fix reserved bits related calculation errors caused by MKTME kvm: x86: Fix L1TF mitigation for shadow MMU Kan Liang (1): perf vendor events intel: Add uncore_upi JSON support Kim Phillips (17): x86/cpu/amd: Call init_amd_zn() om Family 19h processors too perf/amd/uncore: Prepare L3 thread mask code for Family 19h perf/amd/uncore: Make L3 thread mask code more readable perf/amd/uncore: Add support for Family 19h L3 PMU arch/x86/amd/ibs: Fix re-arming IBS Fetch perf/x86/amd/ibs: Fix raw sample data accumulation perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour perf/x86/amd/ibs: Don't include randomized bits in get_ibs_op_count() perf/amd/uncore: Prepare to scale for more attributes that vary per family perf/amd/uncore: Allow F17h user threadmask and slicemask specification perf/amd/uncore: Allow F19h user coreid, threadmask, and sliceid specification perf vendor events amd: Add L3 cache events for Family 17h perf vendor events amd: Remove redundant '[' perf vendor events amd: Enable Family 19h users by matching Zen2 events perf/x86/amd/ibs: Support 27-bit extended Op/cycle counter tools/power turbostat: Support AMD Family 19h perf vendor events amd: Add L2 Prefetch events for zen1 Krish Sadhukhan (1): KVM: SVM: Replace hard-coded value with #define Like Xu (1): perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest Liu Jingqi (2): KVM: x86: expose MOVDIRI CPU feature into VM. KVM: x86: expose MOVDIR64B CPU feature into VM. Maciej S. Szmigiero (1): KVM: mmu: Fix SPTE encoding of MMIO generation upper half Marcel Bocu (1): x86/amd_nb: Add PCI device IDs for family 17h, model 70h Martin Liška (1): perf vendor events amd: perf PMU events for AMD Family 17h Nathan Chancellor (1): perf/amd/uncore: Fix sysfs type mismatch Paolo Bonzini (3): KVM: x86: only do L1TF workaround on affected processors KVM: x86: assign two bits to track SPTE kinds KVM: x86: fix overlap between SPTE_MMIO_MASK and generation Rasmus Villemoes (1): build_bug.h: add wrapper for _Static_assert Sean Christopherson (13): KVM: nVMX: Allocate and configure VM{READ,WRITE} bitmaps iff enable_shadow_vmcs KVM: x86: Add requisite includes to kvm_cache_regs.h KVM: x86: Add requisite includes to hyperv.h KVM: x86: Use a u64 when passing the MMIO gen around KVM: Explicitly define the "memslot update in-progress" bit KVM: x86: Refactor the MMIO SPTE generation handling KVM: x86: Rename access permissions cache member in struct kvm_vcpu_arch KVM: x86/mmu: Add explicit access mask for MMIO SPTEs KVM: x86/mmu: Consolidate "is MMIO SPTE" code KVM: x86/mmu: Apply max PA check for MMIO sptes to 32-bit KVM KVM: x86/mmu: Set mmio_value to '0' if reserved #PF can't be generated KVM: Remove the hack to trigger memslot generation wraparound KVM: Move the memslot update in-progress flag to bit 63 Sebastian Andrzej Siewior (3): x86/pkeys: Provide *pkru() helpers x86/fpu: Only write PKRU if it is different from current x86/pkeys: Don't check if PKRU is zero before writing it Tom Lendacky (1): KVM: SVM: Override default MMIO mask if memory encryption is enabled Vijay Thakkar (3): perf vendor events amd: Restrict model detection for zen1 based processors perf vendor events amd: Add Zen2 events perf vendor events amd: Update Zen1 events to V2 Woods, Brian (2): hwmon/k10temp, x86/amd_nb: Consolidate shared device IDs x86/amd_nb: Add PCI device IDs for family 17h, model 30h Yazen Ghannam (24): EDAC/amd64: Drop some family checks for newer systems x86/amd_nb: Add Family 19h PCI IDs EDAC/mce_amd: Always load on SMCA systems x86/MCE/AMD, EDAC/mce_amd: Add new MP5, NBIO, and PCIE SMCA bank types x86/MCE/AMD, EDAC/mce_amd: Add new McaTypes for CS, PSP, and SMU units x86/MCE/AMD, EDAC/mce_amd: Add new error descriptions for some SMCA bank types x86/MCE/AMD, EDAC/mce_amd: Add new Load Store unit McaType EDAC/amd64: Use a macro for iterating over Unified Memory Controllers EDAC/amd64: Support more than two controllers for chip selects handling EDAC/amd64: Initialize DIMM info for systems with more than two channels EDAC/amd64: Add Family 17h Model 30h PCI IDs EDAC/amd64: Support more than two Unified Memory Controllers EDAC/amd64: Set maximum channel layer size depending on family EDAC/amd64: Recognize x16 symbol size EDAC/amd64: Adjust printed chip select sizes when interleaved EDAC/amd64: Find Chip Select memory size using Address Mask EDAC/amd64: Cache secondary Chip Select registers EDAC/amd64: Support asymmetric dual-rank DIMMs EDAC/amd64: Set grain per DIMM EDAC/amd64: Make struct amd64_family_type global EDAC/amd64: Gather hardware information early EDAC/amd64: Save max number of controllers to family type EDAC/amd64: Add family ops for Family 19h Models 00h-0Fh EDAC/amd64: Handle three rank interleaving mode Documentation/virtual/kvm/mmu.txt | 13 +- arch/x86/events/amd/ibs.c | 93 +- arch/x86/events/amd/uncore.c | 179 ++-- arch/x86/events/perf_event.h | 3 +- arch/x86/include/asm/cpufeatures.h | 4 +- arch/x86/include/asm/kvm_host.h | 10 +- arch/x86/include/asm/mce.h | 7 + arch/x86/include/asm/microcode_amd.h | 2 +- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/perf_event.h | 16 +- arch/x86/include/asm/pgtable.h | 2 +- arch/x86/include/asm/special_insns.h | 19 +- arch/x86/kernel/amd_nb.c | 15 +- arch/x86/kernel/cpu/amd.c | 3 +- arch/x86/kernel/cpu/mce/amd.c | 28 +- arch/x86/kernel/cpu/mce/core.c | 4 +- arch/x86/kvm/cpuid.c | 6 +- arch/x86/kvm/emulate.c | 8 +- arch/x86/kvm/hyperv.h | 2 + arch/x86/kvm/kvm_cache_regs.h | 2 + arch/x86/kvm/mmu.c | 215 +++-- arch/x86/kvm/mmu.h | 2 +- arch/x86/kvm/svm.c | 53 +- arch/x86/kvm/vmx.c | 53 +- arch/x86/kvm/x86.c | 33 +- arch/x86/kvm/x86.h | 4 +- arch/x86/mm/pkeys.c | 7 - drivers/edac/amd64_edac.c | 609 ++++++++---- drivers/edac/amd64_edac.h | 31 +- drivers/edac/mce_amd.c | 134 ++- drivers/hwmon/k10temp.c | 9 +- include/linux/build_bug.h | 19 + include/linux/kvm_host.h | 21 + include/linux/pci_ids.h | 5 + .../pmu-events/arch/x86/amdzen1/branch.json | 23 + .../pmu-events/arch/x86/amdzen1/cache.json | 312 ++++++ .../pmu-events/arch/x86/amdzen1/core.json | 125 +++ .../arch/x86/amdzen1/floating-point.json | 224 +++++ .../pmu-events/arch/x86/amdzen1/memory.json | 184 ++++ .../pmu-events/arch/x86/amdzen1/other.json | 56 ++ .../pmu-events/arch/x86/amdzen2/branch.json | 52 + .../pmu-events/arch/x86/amdzen2/cache.json | 338 +++++++ .../pmu-events/arch/x86/amdzen2/core.json | 130 +++ .../arch/x86/amdzen2/floating-point.json | 140 +++ .../pmu-events/arch/x86/amdzen2/memory.json | 341 +++++++ .../pmu-events/arch/x86/amdzen2/other.json | 115 +++ .../pmu-events/arch/x86/icelake/cache.json | 552 +++++++++++ .../arch/x86/icelake/floating-point.json | 102 ++ .../pmu-events/arch/x86/icelake/frontend.json | 424 +++++++++ .../pmu-events/arch/x86/icelake/memory.json | 410 ++++++++ .../pmu-events/arch/x86/icelake/other.json | 121 +++ .../pmu-events/arch/x86/icelake/pipeline.json | 892 ++++++++++++++++++ .../arch/x86/icelake/virtual-memory.json | 236 +++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 6 + .../pmu-events/arch/x86/tremontx/cache.json | 111 +++ .../arch/x86/tremontx/frontend.json | 26 + .../pmu-events/arch/x86/tremontx/memory.json | 26 + .../pmu-events/arch/x86/tremontx/other.json | 26 + .../arch/x86/tremontx/pipeline.json | 111 +++ .../arch/x86/tremontx/uncore-memory.json | 73 ++ .../arch/x86/tremontx/uncore-other.json | 431 +++++++++ .../arch/x86/tremontx/uncore-power.json | 11 + .../arch/x86/tremontx/virtual-memory.json | 86 ++ tools/perf/pmu-events/jevents.c | 2 + tools/power/x86/turbostat/turbostat.c | 34 +- virt/kvm/kvm_main.c | 36 +- 66 files changed, 6839 insertions(+), 529 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/branch.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/core.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen1/other.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/branch.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/core.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/amdzen2/other.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/other.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/other.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-power.json create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json -- 2.22.0

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[PATCH OLK-5.10 v2 0/2] change arm64 and x86 configs
by Chao Liu 19 Jan '22

19 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 288 ++++++++----- arch/x86/configs/openeuler_defconfig | 544 +++++++++---------------- 2 files changed, 376 insertions(+), 456 deletions(-) -- 2.27.0

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[PATCH OLK-5.10 v2 0/2] change arm64 and x86 configs
by Chao Liu 19 Jan '22

19 Jan '22

openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 287 ++++++++----- arch/x86/configs/openeuler_defconfig | 544 +++++++++---------------- 2 files changed, 375 insertions(+), 456 deletions(-) -- 2.27.0

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[PATCH OLK-5.10 v4 1/3] arm64: register persistent memory
by Zhuling 19 Jan '22

19 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I?from=project-issue CVE: NA ------------------------------ Register pmem in arm64: Use memmap(memmap=nn[KMG]!ss[KMG]) reserve memory for pmem to register persistent memory in arm64. when the kernel restart or update, the data in PMEM will not be lost and can be loaded faster. this is a general features. Currently, only one pmem can be registered and use. If you want use this features, you need do as follows: 1.Reserve memory: add memmap to reserve memory in grub.cfg memmap=nn[KMG]!ss[KMG] exp:memmap=100K!0x1a0000000. 2.Insmod nd_e820.ko: modprobe nd_e820. 3.Check pmem device in /dev exp: /dev/pmem0 driver/nvdimm/e820.c: The function of this file is scan "iomem_resource" and take advantage of nvdimm resource discovery mechanism by registering a resource named "Persistent Memory (legacy)", this function doesn't depend on architecture. We will push the feature to linux kernel community and discuss to modify the file name. because people have a mistaken notion that the e820.c is depend on x86. Signed-off-by: Zhuling <zhuling8(a)huawei.com> --- arch/arm64/Kconfig | 12 ++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/pmem.c | 34 ++++++++++++++++++++++++++++++++++ drivers/nvdimm/Kconfig | 7 +++++++ drivers/nvdimm/Makefile | 1 + 5 files changed, 55 insertions(+) create mode 100644 arch/arm64/kernel/pmem.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 2cab963..105221c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1325,6 +1325,18 @@ config RODATA_FULL_DEFAULT_ENABLED This requires the linear region to be mapped down to pages, which may adversely affect performance in some cases. +config ARM64_PMEM_LEGACY_DEVICE + bool "Create persistent storage" + depends on BLK_DEV + depends on LIBNVDIMM + select ARM64_PMEM_RESERVE + help + Use reserved memory for persistent storage when the kernel + restart or update. the data in PMEM will not be lost and + can be loaded faster. + + Say y if unsure. + config ARM64_SW_TTBR0_PAN bool "Emulate Privileged Access Never using TTBR0_EL1 switching" help diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 169d90f..f615325 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_ARM64_PTR_AUTH) += pointer_auth.o obj-$(CONFIG_SHADOW_CALL_STACK) += scs.o obj-$(CONFIG_ARM64_MTE) += mte.o obj-$(CONFIG_MPAM) += mpam/ +obj-$(CONFIG_ARM64_PMEM_LEGACY_DEVICE) += pmem.o obj-y += vdso/ probes/ obj-$(CONFIG_COMPAT_VDSO) += vdso32/ diff --git a/arch/arm64/kernel/pmem.c b/arch/arm64/kernel/pmem.c new file mode 100644 index 0000000..2312ac0 --- /dev/null +++ b/arch/arm64/kernel/pmem.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arm64 implement PMEM. + * based on arch/x86/kernel/pmem.c + */ +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/module.h> + +static int found(struct resource *res, void *data) +{ + return 1; +} + +static int __init register_e820_pmem(void) +{ + struct platform_device *pdev; + int rc; + + rc = walk_iomem_res_desc(IORES_DESC_PERSISTENT_MEMORY_LEGACY, + IORESOURCE_MEM, 0, -1, NULL, found); + if (rc <= 0) + return 0; + + /* + * See drivers/nvdimm/e820.c for the implementation, this is + * simply here to trigger the module to load on demand. + */ + pdev = platform_device_alloc("e820_pmem", -1); + +return platform_device_add(pdev); +} +device_initcall(register_e820_pmem); diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index b7d1eb3..ce5d4fd 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -132,3 +132,10 @@ config NVDIMM_TEST_BUILD infrastructure. endif + +config PMEM_LEGACY + tristate "Pmem_legacy" + depends on X86 || ARM64 + select X86_PMEM_LEGACY if X86 + select ARM64_PMEM_LEGACY_DEVICE if ARM64 + diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 0407753..6f8dc92 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o obj-$(CONFIG_ND_BTT) += nd_btt.o obj-$(CONFIG_ND_BLK) += nd_blk.o +obj-$(CONFIG_PMEM_LEGACY) += nd_e820.o obj-$(CONFIG_OF_PMEM) += of_pmem.o obj-$(CONFIG_VIRTIO_PMEM) += virtio_pmem.o nd_virtio.o -- 2.9.5

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[PATCH openEuler-5.10 01/24] mm: declare several functions
by Zheng Zengkai 18 Jan '22

18 Jan '22

From: Liu Shixin <liushixin2(a)huawei.com> hulk inclusion category: feature bugzilla: 46904, https://gitee.com/openeuler/kernel/issues/I4QSHG CVE: NA -------------------------------- There are several functions that will be used in next patches for dynamic hugetlb feature. Declare them. No functional changes. Signed-off-by: Liu Shixin <liushixin2(a)huawei.com> Reviewed-by: Kefeng Wang <wangkefeng.wang(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- include/linux/hugetlb.h | 3 +++ include/linux/memcontrol.h | 16 ++++++++++++++++ include/linux/memory_hotplug.h | 6 ++++++ mm/hugetlb.c | 2 +- mm/internal.h | 3 +++ mm/memcontrol.c | 16 ---------------- mm/memory_hotplug.c | 3 +-- mm/page_alloc.c | 6 +++--- 8 files changed, 33 insertions(+), 22 deletions(-) diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index 61c38e6c6c43..a1135c43719e 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -471,6 +471,9 @@ static inline struct hstate *hstate_inode(struct inode *i) { return HUGETLBFS_SB(i->i_sb)->hstate; } + +bool prep_compound_gigantic_page(struct page *page, unsigned int order); + #else /* !CONFIG_HUGETLBFS */ #define is_file_hugepages(file) false diff --git a/include/linux/memcontrol.h b/include/linux/memcontrol.h index e5826f1ff337..2e0a480a8665 100644 --- a/include/linux/memcontrol.h +++ b/include/linux/memcontrol.h @@ -1239,6 +1239,22 @@ unsigned long mem_cgroup_soft_limit_reclaim(pg_data_t *pgdat, int order, gfp_t gfp_mask, unsigned long *total_scanned); +/* + * Test whether @memcg has children, dead or alive. Note that this + * function doesn't care whether @memcg has use_hierarchy enabled and + * returns %true if there are child csses according to the cgroup + * hierarchy. Testing use_hierarchy is the caller's responsibility. + */ +static inline bool memcg_has_children(struct mem_cgroup *memcg) +{ + bool ret; + + rcu_read_lock(); + ret = css_next_child(NULL, &memcg->css); + rcu_read_unlock(); + return ret; +} + #else /* CONFIG_MEMCG */ #define MEM_CGROUP_ID_SHIFT 0 diff --git a/include/linux/memory_hotplug.h b/include/linux/memory_hotplug.h index c60bda5cbb17..b9aeabcce49a 100644 --- a/include/linux/memory_hotplug.h +++ b/include/linux/memory_hotplug.h @@ -284,6 +284,7 @@ static inline void pgdat_resize_init(struct pglist_data *pgdat) {} #ifdef CONFIG_MEMORY_HOTREMOVE +extern int do_migrate_range(unsigned long start_pfn, unsigned long end_pfn); extern void try_offline_node(int nid); extern int offline_pages(unsigned long start_pfn, unsigned long nr_pages); extern int remove_memory(int nid, u64 start, u64 size); @@ -291,6 +292,11 @@ extern void __remove_memory(int nid, u64 start, u64 size); extern int offline_and_remove_memory(int nid, u64 start, u64 size); #else +static inline int do_migrate_range(unsigned long start_pfn, unsigned long end_pfn) +{ + return -ENOSYS; +} + static inline void try_offline_node(int nid) {} static inline int offline_pages(unsigned long start_pfn, unsigned long nr_pages) diff --git a/mm/hugetlb.c b/mm/hugetlb.c index 219bf083dc8a..fa3cba3571cc 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c @@ -1633,7 +1633,7 @@ static void prep_new_huge_page(struct hstate *h, struct page *page, int nid) spin_unlock_irq(&hugetlb_lock); } -static bool prep_compound_gigantic_page(struct page *page, unsigned int order) +bool prep_compound_gigantic_page(struct page *page, unsigned int order) { int i, j; int nr_pages = 1 << order; diff --git a/mm/internal.h b/mm/internal.h index db9546707695..31517354f3c7 100644 --- a/mm/internal.h +++ b/mm/internal.h @@ -197,6 +197,9 @@ extern void __free_pages_core(struct page *page, unsigned int order); extern void prep_compound_page(struct page *page, unsigned int order); extern void post_alloc_hook(struct page *page, unsigned int order, gfp_t gfp_flags); +extern void prep_new_page(struct page *page, unsigned int order, gfp_t gfp_flags, + unsigned int alloc_flags); +extern bool free_pages_prepare(struct page *page, unsigned int order, bool check_free); extern int user_min_free_kbytes; extern void zone_pcp_update(struct zone *zone); diff --git a/mm/memcontrol.c b/mm/memcontrol.c index 8acf7ff56294..011aff396af2 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -3402,22 +3402,6 @@ unsigned long mem_cgroup_soft_limit_reclaim(pg_data_t *pgdat, int order, return nr_reclaimed; } -/* - * Test whether @memcg has children, dead or alive. Note that this - * function doesn't care whether @memcg has use_hierarchy enabled and - * returns %true if there are child csses according to the cgroup - * hierarchy. Testing use_hierarchy is the caller's responsibility. - */ -static inline bool memcg_has_children(struct mem_cgroup *memcg) -{ - bool ret; - - rcu_read_lock(); - ret = css_next_child(NULL, &memcg->css); - rcu_read_unlock(); - return ret; -} - /* * Reclaims as many pages from the given memcg as possible. * diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c index 1549b19b36f6..73ea92dae74a 100644 --- a/mm/memory_hotplug.c +++ b/mm/memory_hotplug.c @@ -1165,8 +1165,7 @@ static int scan_movable_pages(unsigned long start, unsigned long end, return 0; } -static int -do_migrate_range(unsigned long start_pfn, unsigned long end_pfn) +int do_migrate_range(unsigned long start_pfn, unsigned long end_pfn) { unsigned long pfn; struct page *page, *head; diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 988051bf6795..0ff4f4e3a538 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -1203,7 +1203,7 @@ static void kernel_init_free_pages(struct page *page, int numpages) kasan_enable_current(); } -static __always_inline bool free_pages_prepare(struct page *page, +__always_inline bool free_pages_prepare(struct page *page, unsigned int order, bool check_free) { int bad = 0; @@ -2283,8 +2283,8 @@ inline void post_alloc_hook(struct page *page, unsigned int order, set_page_owner(page, order, gfp_flags); } -static void prep_new_page(struct page *page, unsigned int order, gfp_t gfp_flags, - unsigned int alloc_flags) +void prep_new_page(struct page *page, unsigned int order, gfp_t gfp_flags, + unsigned int alloc_flags) { post_alloc_hook(page, order, gfp_flags); -- 2.20.1

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[PATCH OLK-5.10] reboot: allow to specify reboot mode via sysfs
by Hongyu Li 18 Jan '22

18 Jan '22

From: Matteo Croce <mcroce(a)microsoft.com> mainline inclusion category: feature from mainline-v5.11 commit 2c622ed0eaa38b68d7440bedb8c6cdd138b5a860 bugzilla: https://gitee.com/openeuler/kernel/issues/I4BULZ CVE: NA -------------------------------- The kernel cmdline reboot= option offers some sort of control on how the reboot is issued. We don't always know in advance what type of reboot to perform. Sometimes a warm reboot is preferred to persist certain memory regions across the reboot. Others a cold one is needed to apply a future system update that makes a memory memory model change, like changing the base page size or resizing a persistent memory region. Or simply we want to enable reboot_force because we noticed that something bad happened. Add handles in sysfs to allow setting these reboot options, so they can be changed when the system is booted, other than at boot time. The handlers are under <sysfs>/kernel/reboot, can be read to get the current configuration and written to alter it. # cd /sys/kernel/reboot/ # grep . * cpu:0 force:0 mode:cold type:acpi # echo 2 >cpu # echo yes >force # echo soft >mode # echo bios >type # grep . * cpu:2 force:1 mode:soft type:bios Before setting anything, check for CAP_SYS_BOOT capability, so it's possible to allow an unpriviledged process to change these settings simply by relaxing the handles permissions, without opening them to the world. [natechancellor(a)gmail.com: fix variable assignments in type_store] Link: https://lkml.kernel.org/r/20201112035023.974748-1-natechancellor@gmail.com Link: https://github.com/ClangBuiltLinux/linux/issues/1197 Link: https://lkml.kernel.org/r/20201110202746.9690-1-mcroce@linux.microsoft.com Signed-off-by: Matteo Croce <mcroce(a)microsoft.com> Signed-off-by: Nathan Chancellor <natechancellor(a)gmail.com> Reviewed-by: Petr Mladek <pmladek(a)suse.com> Cc: Mike Rapoport <rppt(a)kernel.org> Cc: Guenter Roeck <linux(a)roeck-us.net> Cc: Arnd Bergmann <arnd(a)arndb.de> Cc: Pavel Tatashin <pasha.tatashin(a)soleen.com> Cc: Kees Cook <keescook(a)chromium.org> Cc: Tyler Hicks <tyhicks(a)linux.microsoft.com> Cc: Nathan Chancellor <natechancellor(a)gmail.com> Signed-off-by: Andrew Morton <akpm(a)linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds(a)linux-foundation.org> Signed-off-by: Li Hongyu <543306408(a)qq.com> --- Documentation/ABI/testing/sysfs-kernel-reboot | 32 +++ kernel/reboot.c | 206 ++++++++++++++++++ 2 files changed, 238 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-kernel-reboot diff --git a/Documentation/ABI/testing/sysfs-kernel-reboot b/Documentation/ABI/testing/sysfs-kernel-reboot new file mode 100644 index 000000000000..837330fb2511 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-kernel-reboot @@ -0,0 +1,32 @@ +What: /sys/kernel/reboot +Date: November 2020 +KernelVersion: 5.11 +Contact: Matteo Croce <mcroce(a)microsoft.com> +Description: Interface to set the kernel reboot behavior, similarly to + what can be done via the reboot= cmdline option. + (see Documentation/admin-guide/kernel-parameters.txt) + +What: /sys/kernel/reboot/mode +Date: November 2020 +KernelVersion: 5.11 +Contact: Matteo Croce <mcroce(a)microsoft.com> +Description: Reboot mode. Valid values are: cold warm hard soft gpio + +What: /sys/kernel/reboot/type +Date: November 2020 +KernelVersion: 5.11 +Contact: Matteo Croce <mcroce(a)microsoft.com> +Description: Reboot type. Valid values are: bios acpi kbd triple efi pci + +What: /sys/kernel/reboot/cpu +Date: November 2020 +KernelVersion: 5.11 +Contact: Matteo Croce <mcroce(a)microsoft.com> +Description: CPU number to use to reboot. + +What: /sys/kernel/reboot/force +Date: November 2020 +KernelVersion: 5.11 +Contact: Matteo Croce <mcroce(a)microsoft.com> +Description: Don't wait for any other CPUs on reboot and + avoid anything that could hang. diff --git a/kernel/reboot.c b/kernel/reboot.c index aa3bfd6c673b..940cbb784e17 100644 --- a/kernel/reboot.c +++ b/kernel/reboot.c @@ -600,3 +600,209 @@ static int __init reboot_setup(char *str) return 1; } __setup("reboot=", reboot_setup); + +#ifdef CONFIG_SYSFS + +#define REBOOT_COLD_STR "cold" +#define REBOOT_WARM_STR "warm" +#define REBOOT_HARD_STR "hard" +#define REBOOT_SOFT_STR "soft" +#define REBOOT_GPIO_STR "gpio" +#define REBOOT_UNDEFINED_STR "undefined" + +#define BOOT_TRIPLE_STR "triple" +#define BOOT_KBD_STR "kbd" +#define BOOT_BIOS_STR "bios" +#define BOOT_ACPI_STR "acpi" +#define BOOT_EFI_STR "efi" +#define BOOT_CF9_FORCE_STR "cf9_force" +#define BOOT_CF9_SAFE_STR "cf9_safe" + +static ssize_t mode_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + const char *val; + + switch (reboot_mode) { + case REBOOT_COLD: + val = REBOOT_COLD_STR; + break; + case REBOOT_WARM: + val = REBOOT_WARM_STR; + break; + case REBOOT_HARD: + val = REBOOT_HARD_STR; + break; + case REBOOT_SOFT: + val = REBOOT_SOFT_STR; + break; + case REBOOT_GPIO: + val = REBOOT_GPIO_STR; + break; + default: + val = REBOOT_UNDEFINED_STR; + } + + return sprintf(buf, "%s\n", val); +} +static ssize_t mode_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + if (!capable(CAP_SYS_BOOT)) + return -EPERM; + + if (!strncmp(buf, REBOOT_COLD_STR, strlen(REBOOT_COLD_STR))) + reboot_mode = REBOOT_COLD; + else if (!strncmp(buf, REBOOT_WARM_STR, strlen(REBOOT_WARM_STR))) + reboot_mode = REBOOT_WARM; + else if (!strncmp(buf, REBOOT_HARD_STR, strlen(REBOOT_HARD_STR))) + reboot_mode = REBOOT_HARD; + else if (!strncmp(buf, REBOOT_SOFT_STR, strlen(REBOOT_SOFT_STR))) + reboot_mode = REBOOT_SOFT; + else if (!strncmp(buf, REBOOT_GPIO_STR, strlen(REBOOT_GPIO_STR))) + reboot_mode = REBOOT_GPIO; + else + return -EINVAL; + + return count; +} +static struct kobj_attribute reboot_mode_attr = __ATTR_RW(mode); + +static ssize_t type_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + const char *val; + + switch (reboot_type) { + case BOOT_TRIPLE: + val = BOOT_TRIPLE_STR; + break; + case BOOT_KBD: + val = BOOT_KBD_STR; + break; + case BOOT_BIOS: + val = BOOT_BIOS_STR; + break; + case BOOT_ACPI: + val = BOOT_ACPI_STR; + break; + case BOOT_EFI: + val = BOOT_EFI_STR; + break; + case BOOT_CF9_FORCE: + val = BOOT_CF9_FORCE_STR; + break; + case BOOT_CF9_SAFE: + val = BOOT_CF9_SAFE_STR; + break; + default: + val = REBOOT_UNDEFINED_STR; + } + + return sprintf(buf, "%s\n", val); +} +static ssize_t type_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + if (!capable(CAP_SYS_BOOT)) + return -EPERM; + + if (!strncmp(buf, BOOT_TRIPLE_STR, strlen(BOOT_TRIPLE_STR))) + reboot_type = BOOT_TRIPLE; + else if (!strncmp(buf, BOOT_KBD_STR, strlen(BOOT_KBD_STR))) + reboot_type = BOOT_KBD; + else if (!strncmp(buf, BOOT_BIOS_STR, strlen(BOOT_BIOS_STR))) + reboot_type = BOOT_BIOS; + else if (!strncmp(buf, BOOT_ACPI_STR, strlen(BOOT_ACPI_STR))) + reboot_type = BOOT_ACPI; + else if (!strncmp(buf, BOOT_EFI_STR, strlen(BOOT_EFI_STR))) + reboot_type = BOOT_EFI; + else if (!strncmp(buf, BOOT_CF9_FORCE_STR, strlen(BOOT_CF9_FORCE_STR))) + reboot_type = BOOT_CF9_FORCE; + else if (!strncmp(buf, BOOT_CF9_SAFE_STR, strlen(BOOT_CF9_SAFE_STR))) + reboot_type = BOOT_CF9_SAFE; + else + return -EINVAL; + + return count; +} +static struct kobj_attribute reboot_type_attr = __ATTR_RW(type); + +static ssize_t cpu_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", reboot_cpu); +} +static ssize_t cpu_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + unsigned int cpunum; + int rc; + + if (!capable(CAP_SYS_BOOT)) + return -EPERM; + + rc = kstrtouint(buf, 0, &cpunum); + + if (rc) + return rc; + + if (cpunum >= num_possible_cpus()) + return -ERANGE; + + reboot_cpu = cpunum; + + return count; +} +static struct kobj_attribute reboot_cpu_attr = __ATTR_RW(cpu); + +static ssize_t force_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", reboot_force); +} +static ssize_t force_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + bool res; + + if (!capable(CAP_SYS_BOOT)) + return -EPERM; + + if (kstrtobool(buf, &res)) + return -EINVAL; + + reboot_force = res; + + return count; +} +static struct kobj_attribute reboot_force_attr = __ATTR_RW(force); + +static struct attribute *reboot_attrs[] = { + &reboot_mode_attr.attr, + &reboot_type_attr.attr, + &reboot_cpu_attr.attr, + &reboot_force_attr.attr, + NULL, +}; + +static const struct attribute_group reboot_attr_group = { + .attrs = reboot_attrs, +}; + +static int __init reboot_ksysfs_init(void) +{ + struct kobject *reboot_kobj; + int ret; + + reboot_kobj = kobject_create_and_add("reboot", kernel_kobj); + if (!reboot_kobj) + return -ENOMEM; + + ret = sysfs_create_group(reboot_kobj, &reboot_attr_group); + if (ret) { + kobject_put(reboot_kobj); + return ret; + } + + return 0; +} +late_initcall(reboot_ksysfs_init); + +#endif -- 2.17.1

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[PATCH OLK-5.10] mm: introduce process_mrelease system call
by Wen Zhiwei 18 Jan '22

18 Jan '22

mainline inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4FHN2?from=project-issue CVE: NA --------------------------- In modern systems it's not unusual to have a system component monitoring memory conditions of the system and tasked with keeping system memory pressure under control. One way to accomplish that is to kill non-essential processes to free up memory for more important ones. Examples of this are Facebook's OOM killer daemon called oomd and Android's low memory killer daemon called lmkd. For such system component it's important to be able to free memory quickly and efficiently. Unfortunately the time process takes to free up its memory after receiving a SIGKILL might vary based on the state of the process (uninterruptible sleep), size and OPP level of the core the process is running. A mechanism to free resources of the target process in a more predictable way would improve system's ability to control its memory pressure. Introduce process_mrelease system call that releases memory of a dying process from the context of the caller. This way the memory is freed in a more controllable way with CPU affinity and priority of the caller. The workload of freeing the memory will also be charged to the caller. The operation is allowed only on a dying process. Signed-off-by: Suren Baghdasaryan <surenb(a)google.com> Reviewed-by: Shakeel Butt <shakeelb(a)google.com> Acked-by: David Hildenbrand <david(a)redhat.com> Acked-by: Michal Hocko <mhocko(a)suse.com> Acked-by: Christian Brauner <christian.brauner(a)ubuntu.com> Cc: David Rientjes <rientjes(a)google.com> Cc: Matthew Wilcox (Oracle) <willy(a)infradead.org> Cc: Johannes Weiner <hannes(a)cmpxchg.org> Cc: Roman Gushchin <guro(a)fb.com> Cc: Rik van Riel <riel(a)surriel.com> Cc: Minchan Kim <minchan(a)kernel.org> Cc: Christoph Hellwig <hch(a)infradead.org> Cc: Oleg Nesterov <oleg(a)redhat.com> Cc: Jann Horn <jannh(a)google.com> Cc: Geert Uytterhoeven <geert(a)linux-m68k.org> Cc: Andy Lutomirski <luto(a)kernel.org> Cc: Christian Brauner <christian.brauner(a)ubuntu.com> Cc: Florian Weimer <fweimer(a)redhat.com> Cc: Jan Engelhardt <jengelh(a)inai.de> Cc: Tim Murray <timmurray(a)google.com> Signed-off-by: Andrew Morton <akpm(a)linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds(a)linux-foundation.org> Signed-off-by: Wen Zhiwei <wenzhiwei(a)kylinos.cn> --- arch/arm64/include/asm/unistd32.h | 3 +- arch/x86/entry/syscalls/syscall_64.tbl | 2 +- include/linux/syscalls.h | 3 ++ include/uapi/asm-generic/unistd.h | 5 +- kernel/sys_ni.c | 1 + mm/oom_kill.c | 72 +++++++++++++++++++++++++ tools/include/uapi/asm-generic/unistd.h | 4 +- 7 files changed, 86 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h index 107f08e03b9f..e1786b2e8551 100644 --- a/arch/arm64/include/asm/unistd32.h +++ b/arch/arm64/include/asm/unistd32.h @@ -889,7 +889,8 @@ __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd) __SYSCALL(__NR_faccessat2, sys_faccessat2) #define __NR_process_madvise 440 __SYSCALL(__NR_process_madvise, sys_process_madvise) - +#define __NR_process_mrelease 441 +__SYSCALL(__NR_process_mrelease, sys_process_mrelease) /* * Please add new compat syscalls above this comment and update * __NR_compat_syscalls in asm/unistd.h. diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl index 379819244b91..6eec6496d72c 100644 --- a/arch/x86/entry/syscalls/syscall_64.tbl +++ b/arch/x86/entry/syscalls/syscall_64.tbl @@ -362,7 +362,7 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise - +441 common process_mrelease sys_process_mrelease # # Due to a historical design error, certain syscalls are numbered differently # in x32 as compared to native x86_64. These syscalls have numbers 512-547. diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index aea0ce9f3b74..764bfcdbbcb0 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -905,6 +905,9 @@ asmlinkage long sys_mincore(unsigned long start, size_t len, asmlinkage long sys_madvise(unsigned long start, size_t len, int behavior); asmlinkage long sys_process_madvise(int pidfd, const struct iovec __user *vec, size_t vlen, int behavior, unsigned int flags); + +asmlinkage long sys_process_mrelease(int pidfd, unsigned int flags); + asmlinkage long sys_remap_file_pages(unsigned long start, unsigned long size, unsigned long prot, unsigned long pgoff, unsigned long flags); diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h index 2056318988f7..e5f38ea960c4 100644 --- a/include/uapi/asm-generic/unistd.h +++ b/include/uapi/asm-generic/unistd.h @@ -859,9 +859,12 @@ __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd) __SYSCALL(__NR_faccessat2, sys_faccessat2) #define __NR_process_madvise 440 __SYSCALL(__NR_process_madvise, sys_process_madvise) +#define __NR_process_mrelease 441 +__SYSCALL(__NR_process_mrelease, sys_process_mrelease) #undef __NR_syscalls -#define __NR_syscalls 441 +#define __NR_syscalls 442 + /* * 32 bit systems traditionally used different diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c index f27ac94d5fa7..6b8203edf531 100644 --- a/kernel/sys_ni.c +++ b/kernel/sys_ni.c @@ -281,6 +281,7 @@ COND_SYSCALL(munlockall); COND_SYSCALL(mincore); COND_SYSCALL(madvise); COND_SYSCALL(process_madvise); +COND_SYSCALL(process_mrelease); COND_SYSCALL(remap_file_pages); COND_SYSCALL(mbind); COND_SYSCALL_COMPAT(mbind); diff --git a/mm/oom_kill.c b/mm/oom_kill.c index fb39b0902476..d169eb511518 100644 --- a/mm/oom_kill.c +++ b/mm/oom_kill.c @@ -43,6 +43,7 @@ #include <linux/kthread.h> #include <linux/init.h> #include <linux/mmu_notifier.h> +#include <linux/syscalls.h> #include <asm/tlb.h> #include "internal.h" @@ -1186,3 +1187,74 @@ void pagefault_out_of_memory(void) out_of_memory(&oc); mutex_unlock(&oom_lock); } + +SYSCALL_DEFINE2(process_mrelease, int, pidfd, unsigned int, flags) +{ +#ifdef CONFIG_MMU + struct mm_struct *mm = NULL; + struct task_struct *task; + struct task_struct *p; + unsigned int f_flags; + bool reap = false; + struct pid *pid; + long ret = 0; + + if (flags) + return -EINVAL; + + pid = pidfd_get_pid(pidfd, &f_flags); + if (IS_ERR(pid)) + return PTR_ERR(pid); + + task = get_pid_task(pid, PIDTYPE_TGID); + if (!task) { + ret = -ESRCH; + goto put_pid; + } + + /* + * Make sure to choose a thread which still has a reference to mm + * during the group exit + */ + p = find_lock_task_mm(task); + if (!p) { + ret = -ESRCH; + goto put_task; + } + + if (mmget_not_zero(p->mm)) { + mm = p->mm; + if (task_will_free_mem(p)) + reap = true; + else { + /* Error only if the work has not been done already */ + if (!test_bit(MMF_OOM_SKIP, &mm->flags)) + ret = -EINVAL; + } + } + task_unlock(p); + + if (!reap) + goto drop_mm; + + if (mmap_read_lock_killable(mm)) { + ret = -EINTR; + goto drop_mm; + } + if (!__oom_reap_task_mm(mm)) + ret = -EAGAIN; + mmap_read_unlock(mm); + +drop_mm: + if (mm) + mmput(mm); +put_task: + put_task_struct(task); +put_pid: + put_pid(pid); + return ret; +#else + return -ENOSYS; +#endif /* CONFIG_MMU */ +} + diff --git a/tools/include/uapi/asm-generic/unistd.h b/tools/include/uapi/asm-generic/unistd.h index 2056318988f7..c252faa802d3 100644 --- a/tools/include/uapi/asm-generic/unistd.h +++ b/tools/include/uapi/asm-generic/unistd.h @@ -859,9 +859,11 @@ __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd) __SYSCALL(__NR_faccessat2, sys_faccessat2) #define __NR_process_madvise 440 __SYSCALL(__NR_process_madvise, sys_process_madvise) +#define __NR_process_mrelease 441 +__SYSCALL(__NR_process_mrelease, sys_process_mrelease) #undef __NR_syscalls -#define __NR_syscalls 441 +#define __NR_syscalls 442 /* * 32 bit systems traditionally used different -- 2.30.0

2 1

[PATCH OLK-5.10] crypto:rmd320 rmd128 rmd256-remove RIPE-MD 320 128 256 hash algorithm
by Wen Zhiwei 18 Jan '22

18 Jan '22

mainlin inclusion category: performance bugzilla: NA CVE: NA ----------------------------------------------------------- RIPE-MD 256 is never referenced anywhere in the kernel, and unlikely to be depended upon by userspace via AF_ALG. So let's remove it Signed-off-by: Ard Biesheuvel <ardb(a)kernel.org> Signed-off-by: Herbert Xu <herbert(a)gondor.apana.org.au> Signed-off-by: Wen Zhiwei <wenzhiwei(a)kylinos.cn> --- crypto/tcrypt.c | 42 +----------------------------------------- 1 file changed, 1 insertion(+), 41 deletions(-) diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c index 8609174e036e..c8b0d31631f5 100644 --- a/crypto/tcrypt.c +++ b/crypto/tcrypt.c @@ -71,7 +71,7 @@ static const char *check[] = { "blowfish", "twofish", "serpent", "sha384", "sha512", "md4", "aes", "cast6", "arc4", "michael_mic", "deflate", "crc32c", "tea", "xtea", "khazad", "wp512", "wp384", "wp256", "tnepres", "xeta", "fcrypt", - "camellia", "seed", "salsa20", "rmd128", "rmd160", "rmd256", "rmd320", + "camellia", "seed", "salsa20", "rmd160", "lzo", "lzo-rle", "cts", "sha3-224", "sha3-256", "sha3-384", "sha3-512", "streebog256", "streebog512", NULL @@ -1860,22 +1860,10 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) ret += tcrypt_test("cts(cbc(aes))"); break; - case 39: - ret += tcrypt_test("rmd128"); - break; - case 40: ret += tcrypt_test("rmd160"); break; - case 41: - ret += tcrypt_test("rmd256"); - break; - - case 42: - ret += tcrypt_test("rmd320"); - break; - case 43: ret += tcrypt_test("ecb(seed)"); break; @@ -1948,10 +1936,6 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) ret += tcrypt_test("xcbc(aes)"); break; - case 107: - ret += tcrypt_test("hmac(rmd128)"); - break; - case 108: ret += tcrypt_test("hmac(rmd160)"); break; @@ -2402,22 +2386,10 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) test_hash_speed("sha224", sec, generic_hash_speed_template); if (mode > 300 && mode < 400) break; fallthrough; - case 314: - test_hash_speed("rmd128", sec, generic_hash_speed_template); - if (mode > 300 && mode < 400) break; - fallthrough; case 315: test_hash_speed("rmd160", sec, generic_hash_speed_template); if (mode > 300 && mode < 400) break; fallthrough; - case 316: - test_hash_speed("rmd256", sec, generic_hash_speed_template); - if (mode > 300 && mode < 400) break; - fallthrough; - case 317: - test_hash_speed("rmd320", sec, generic_hash_speed_template); - if (mode > 300 && mode < 400) break; - fallthrough; case 318: klen = 16; test_hash_speed("ghash", sec, generic_hash_speed_template); @@ -2526,22 +2498,10 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) test_ahash_speed("sha224", sec, generic_hash_speed_template); if (mode > 400 && mode < 500) break; fallthrough; - case 414: - test_ahash_speed("rmd128", sec, generic_hash_speed_template); - if (mode > 400 && mode < 500) break; - fallthrough; case 415: test_ahash_speed("rmd160", sec, generic_hash_speed_template); if (mode > 400 && mode < 500) break; fallthrough; - case 416: - test_ahash_speed("rmd256", sec, generic_hash_speed_template); - if (mode > 400 && mode < 500) break; - fallthrough; - case 417: - test_ahash_speed("rmd320", sec, generic_hash_speed_template); - if (mode > 400 && mode < 500) break; - fallthrough; case 418: test_ahash_speed("sha3-224", sec, generic_hash_speed_template); if (mode > 400 && mode < 500) break; -- 2.30.0

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[PATCH OLK-5.10 0/2] change arm64 and x86 configs
by Chao Liu 18 Jan '22

18 Jan '22

change arm64 and x86 configs openEuler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4OFDI CVE: NA -------------------------------- Chao Liu (2): change arm64 configs change x86 configs arch/arm64/configs/openeuler_defconfig | 287 ++++++++----- arch/x86/configs/openeuler_defconfig | 540 +++++++++---------------- 2 files changed, 374 insertions(+), 453 deletions(-) -- 2.27.0

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[PATCH openEuler-1.0-LTS] ip_gre: validate csum_start only on pull
by Yang Yingliang 18 Jan '22

18 Jan '22

From: Willem de Bruijn <willemb(a)google.com> mainline inclusion from mainline-v5.14 commit 8a0ed250f911da31a2aef52101bc707846a800ff category: bugfix bugzilla: NA CVE: CVE-2021-39633 ------------------------------------------------- The GRE tunnel device can pull existing outer headers in ipge_xmit. This is a rare path, apparently unique to this device. The below commit ensured that pulling does not move skb->data beyond csum_start. But it has a false positive if ip_summed is not CHECKSUM_PARTIAL and thus csum_start is irrelevant. Refine to exclude this. At the same time simplify and strengthen the test. Simplify, by moving the check next to the offending pull, making it more self documenting and removing an unnecessary branch from other code paths. Strengthen, by also ensuring that the transport header is correct and therefore the inner headers will be after skb_reset_inner_headers. The transport header is set to csum_start in skb_partial_csum_set. Link: https://lore.kernel.org/netdev/YS+h%2FtqCJJiQei+W@shredder/ Fixes: 1d011c4803c7 ("ip_gre: add validation for csum_start") Reported-by: Ido Schimmel <idosch(a)idosch.org> Suggested-by: Alexander Duyck <alexander.duyck(a)gmail.com> Signed-off-by: Willem de Bruijn <willemb(a)google.com> Reviewed-by: Alexander Duyck <alexanderduyck(a)fb.com> Signed-off-by: David S. Miller <davem(a)davemloft.net> Signed-off-by: Huang Guobin <huangguobin4(a)huawei.com> Reviewed-by: Wei Yongjun <weiyongjun1(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- net/ipv4/ip_gre.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c index a8a37d1128201..0c431fd4b1200 100644 --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c @@ -449,8 +449,6 @@ static void __gre_xmit(struct sk_buff *skb, struct net_device *dev, static int gre_handle_offloads(struct sk_buff *skb, bool csum) { - if (csum && skb_checksum_start(skb) < skb->data) - return -EINVAL; return iptunnel_handle_offloads(skb, csum ? SKB_GSO_GRE_CSUM : SKB_GSO_GRE); } @@ -682,15 +680,20 @@ static netdev_tx_t ipgre_xmit(struct sk_buff *skb, } if (dev->header_ops) { + const int pull_len = tunnel->hlen + sizeof(struct iphdr); + if (skb_cow_head(skb, 0)) goto free_skb; tnl_params = (const struct iphdr *)skb->data; + if (pull_len > skb_transport_offset(skb)) + goto free_skb; + /* Pull skb since ip_tunnel_xmit() needs skb->data pointing * to gre header. */ - skb_pull(skb, tunnel->hlen + sizeof(struct iphdr)); + skb_pull(skb, pull_len); skb_reset_mac_header(skb); } else { if (skb_cow_head(skb, dev->needed_headroom)) -- 2.25.1

1 0

[PATCH openEuler-5.10 01/82] clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses
by Zheng Zengkai 17 Jan '22

17 Jan '22

From: Marc Zyngier <maz(a)kernel.org> mainline inclusion from mainline-v5.16-rc1 commit 4775bc63f880 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4QCBG CVE: NA -------------------------- As we are about to change the registers that are used by the driver, start by adding build-time checks to ensure that we always handle all registers and access modes. Suggested-by: Mark Rutland <mark.rutland(a)arm.com> Signed-off-by: Marc Zyngier <maz(a)kernel.org> Link: https://lore.kernel.org/r/20211017124225.3018098-2-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano(a)linaro.org> Signed-off-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> Reviewed-by: Hanjun Guo <guohanjun(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> --- arch/arm/include/asm/arch_timer.h | 12 ++++++++++++ arch/arm64/include/asm/arch_timer.h | 13 ++++++++++++- drivers/clocksource/arm_arch_timer.c | 8 ++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 99175812d903..a5d27cff28fa 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -34,6 +34,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) case ARCH_TIMER_REG_TVAL: asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); break; + default: + BUILD_BUG(); } } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { @@ -43,7 +45,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) case ARCH_TIMER_REG_TVAL: asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); break; + default: + BUILD_BUG(); } + } else { + BUILD_BUG(); } isb(); @@ -62,6 +68,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) case ARCH_TIMER_REG_TVAL: asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); break; + default: + BUILD_BUG(); } } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { @@ -71,7 +79,11 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) case ARCH_TIMER_REG_TVAL: asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); break; + default: + BUILD_BUG(); } + } else { + BUILD_BUG(); } return val; diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index ce37c14f9417..7dfb7c6261bb 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -112,6 +112,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) case ARCH_TIMER_REG_TVAL: write_sysreg(val, cntp_tval_el0); break; + default: + BUILD_BUG(); } } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { @@ -121,7 +123,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) case ARCH_TIMER_REG_TVAL: write_sysreg(val, cntv_tval_el0); break; + default: + BUILD_BUG(); } + } else { + BUILD_BUG(); } isb(); @@ -136,6 +142,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) return read_sysreg(cntp_ctl_el0); case ARCH_TIMER_REG_TVAL: return arch_timer_reg_read_stable(cntp_tval_el0); + default: + BUILD_BUG(); } } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { @@ -143,10 +151,13 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) return read_sysreg(cntv_ctl_el0); case ARCH_TIMER_REG_TVAL: return arch_timer_reg_read_stable(cntv_tval_el0); + default: + BUILD_BUG(); } } - BUG(); + BUILD_BUG(); + unreachable(); } static inline u32 arch_timer_get_cntfrq(void) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 3ea1c22314f9..f3c65e5181ec 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -103,6 +103,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, case ARCH_TIMER_REG_TVAL: writel_relaxed(val, timer->base + CNTP_TVAL); break; + default: + BUILD_BUG(); } } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { struct arch_timer *timer = to_arch_timer(clk); @@ -113,6 +115,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, case ARCH_TIMER_REG_TVAL: writel_relaxed(val, timer->base + CNTV_TVAL); break; + default: + BUILD_BUG(); } } else { arch_timer_reg_write_cp15(access, reg, val); @@ -134,6 +138,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, case ARCH_TIMER_REG_TVAL: val = readl_relaxed(timer->base + CNTP_TVAL); break; + default: + BUILD_BUG(); } } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { struct arch_timer *timer = to_arch_timer(clk); @@ -144,6 +150,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, case ARCH_TIMER_REG_TVAL: val = readl_relaxed(timer->base + CNTV_TVAL); break; + default: + BUILD_BUG(); } } else { val = arch_timer_reg_read_cp15(access, reg); -- 2.20.1

1 81

[PATCH OLK-5.10 v3 1/3] arm64: Add memmap parameter for pmem
by Zhuling 17 Jan '22

17 Jan '22

hulk inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4O31I?from=project-issue CVE: NA Add "!" in memmap parameter, use memmap(memmap=nn[KMG]!ss[KMG]) reserve memory for pmem which register persistent memory in arm64. Signed-off-by: Zhuling <zhuling8(a)huawei.com> --- Documentation/admin-guide/kernel-parameters.txt | 9 +++++++-- arch/arm64/mm/init.c | 8 ++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 64be32b..1953570 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2829,10 +2829,15 @@ will be eaten. memmap=nn[KMG]!ss[KMG] - [KNL,X86] Mark specific memory as protected. + [KNL,X86,ARM64] Mark specific memory as protected. Region of memory to be used, from ss to ss+nn. - The memory region may be marked as e820 type 12 (0xc) + [X86]The memory region may be marked as e820 type 12 (0xc) and is NVDIMM or ADR memory. + [ARM64]Reserve memory for persistent storage when the kernel + restart or update. the data in PMEM will not be lost and can + be loaded faster + Example: + memmap=100K!0x1a0000000 memmap=<size>%<offset>-<oldtype>+<newtype> [KNL,ACPI] Convert memory within the specified region diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 6ebfabd..b9eb312 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -56,6 +56,8 @@ s64 memstart_addr __ro_after_init = -1; EXPORT_SYMBOL(memstart_addr); +phys_addr_t start_at, mem_size; + #ifdef CONFIG_PIN_MEMORY struct resource pin_memory_resource = { .name = "Pin memory", @@ -111,6 +113,8 @@ static void __init reserve_pin_memory_res(void) */ phys_addr_t arm64_dma_phys_limit __ro_after_init; +static unsigned long long pmem_size, pmem_start; + #ifndef CONFIG_KEXEC_CORE static void __init reserve_crashkernel(void) { @@ -442,6 +446,10 @@ static int __init parse_memmap_one(char *p) start_at = memparse(p + 1, &p); memblock_reserve(start_at, mem_size); memblock_mark_memmap(start_at, mem_size); + } else if (*p == '!') { + start_at = memparse(p+1, &p); + pmem_start = start_at; + pmem_size = mem_size; } else pr_info("Unrecognized memmap option, please check the parameter.\n"); -- 2.9.5

3 7

[PATCH openEuler-1.0-LTS 1/2] hugetlbfs: extend the definition of hugepages parameter to support node allocation
by Yang Yingliang 17 Jan '22

17 Jan '22

From: Zhenguo Yao <yaozhenguo1(a)gmail.com> mainline inclusion from mainline-v5.16-rc1 commit b5389086ad7be0453c55e0069a89856d1fbdf605 category: feature bugzilla: 186043 CVE: NA -------------------------------- We can specify the number of hugepages to allocate at boot. But the hugepages is balanced in all nodes at present. In some scenarios, we only need hugepages in one node. For example: DPDK needs hugepages which are in the same node as NIC. If DPDK needs four hugepages of 1G size in node1 and system has 16 numa nodes we must reserve 64 hugepages on the kernel cmdline. But only four hugepages are used. The others should be free after boot. If the system memory is low(for example: 64G), it will be an impossible task. So extend the hugepages parameter to support specifying hugepages on a specific node. For example add following parameter: hugepagesz=1G hugepages=0:1,1:3 It will allocate 1 hugepage in node0 and 3 hugepages in node1. Link: https://lkml.kernel.org/r/20211005054729.86457-1-yaozhenguo1@gmail.com Signed-off-by: Zhenguo Yao <yaozhenguo1(a)gmail.com> Reviewed-by: Mike Kravetz <mike.kravetz(a)oracle.com> Cc: Zhenguo Yao <yaozhenguo1(a)gmail.com> Cc: Dan Carpenter <dan.carpenter(a)oracle.com> Cc: Nathan Chancellor <nathan(a)kernel.org> Cc: Michael Ellerman <mpe(a)ellerman.id.au> Cc: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> Cc: Paul Mackerras <paulus(a)samba.org> Cc: Jonathan Corbet <corbet(a)lwn.net> Cc: Mike Rapoport <rppt(a)kernel.org> Cc: Matthew Wilcox (Oracle) <willy(a)infradead.org> Signed-off-by: Andrew Morton <akpm(a)linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds(a)linux-foundation.org> Conflicts: Documentation/admin-guide/kernel-parameters.txt Documentation/admin-guide/mm/hugetlbpage.rst arch/powerpc/mm/hugetlbpage.c include/linux/hugetlb.h mm/hugetlb.c Signed-off-by: Liu Shixin <liushixin2(a)huawei.com> Reviewed-by: Kefeng Wang<wangkefeng.wang(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- .../admin-guide/kernel-parameters.txt | 5 + arch/powerpc/mm/hugetlbpage.c | 9 +- include/linux/hugetlb.h | 6 +- mm/hugetlb.c | 142 +++++++++++++++--- 4 files changed, 137 insertions(+), 25 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 420f7317aa6af..5623a9d1cf813 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1402,6 +1402,11 @@ registers. Default set by CONFIG_HPET_MMAP_DEFAULT. hugepages= [HW,X86-32,IA-64] HugeTLB pages to allocate at boot. + If using node format, the number of pages to allocate + per-node can be specified. + Format: <integer> or (node format) + <node>:<integer>[,<node>:<integer>] + hugepagesz= [HW,IA-64,PPC,X86-64] The size of the HugeTLB pages. On x86-64 and powerpc, this option can be specified multiple times interleaved with hugepages= to reserve diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c index cef0b7ee10246..163b0ef7d156e 100644 --- a/arch/powerpc/mm/hugetlbpage.c +++ b/arch/powerpc/mm/hugetlbpage.c @@ -241,17 +241,22 @@ int __init pseries_alloc_bootmem_huge_page(struct hstate *hstate) m->hstate = hstate; return 1; } + +bool __init hugetlb_node_alloc_supported(void) +{ + return false; +} #endif -int __init alloc_bootmem_huge_page(struct hstate *h) +int __init alloc_bootmem_huge_page(struct hstate *h, int nid) { #ifdef CONFIG_PPC_BOOK3S_64 if (firmware_has_feature(FW_FEATURE_LPAR) && !radix_enabled()) return pseries_alloc_bootmem_huge_page(h); #endif - return __alloc_bootmem_huge_page(h); + return __alloc_bootmem_huge_page(h, nid); } #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx) diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index 561e7679fadc4..588f9f2a44fce 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -347,6 +347,7 @@ struct hstate { unsigned long nr_overcommit_huge_pages; struct list_head hugepage_activelist; struct list_head hugepage_freelists[MAX_NUMNODES]; + unsigned int max_huge_pages_node[MAX_NUMNODES]; unsigned int nr_huge_pages_node[MAX_NUMNODES]; unsigned int free_huge_pages_node[MAX_NUMNODES]; unsigned int surplus_huge_pages_node[MAX_NUMNODES]; @@ -409,8 +410,9 @@ int hugetlb_insert_hugepage(struct vm_area_struct *vma, unsigned long addr, struct page *hpage, pgprot_t prot); /* arch callback */ -int __init __alloc_bootmem_huge_page(struct hstate *h); -int __init alloc_bootmem_huge_page(struct hstate *h); +int __init __alloc_bootmem_huge_page(struct hstate *h, int nid); +int __init alloc_bootmem_huge_page(struct hstate *h, int nid); +bool __init hugetlb_node_alloc_supported(void); void __init hugetlb_bad_size(void); void __init hugetlb_add_hstate(unsigned order); diff --git a/mm/hugetlb.c b/mm/hugetlb.c index b2ed9174bfd73..8286a6f8cb050 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c @@ -56,6 +56,7 @@ static struct hstate * __initdata parsed_hstate; static unsigned long __initdata default_hstate_max_huge_pages; static unsigned long __initdata default_hstate_size; static bool __initdata parsed_valid_hugepagesz = true; +static unsigned int default_hugepages_in_node[MAX_NUMNODES] __initdata; int enable_charge_mighp __read_mostly; /* @@ -2241,33 +2242,39 @@ struct page *alloc_huge_page(struct vm_area_struct *vma, return ERR_PTR(-ENOSPC); } -int alloc_bootmem_huge_page(struct hstate *h) +int alloc_bootmem_huge_page(struct hstate *h, int nid) __attribute__ ((weak, alias("__alloc_bootmem_huge_page"))); -int __alloc_bootmem_huge_page(struct hstate *h) +int __alloc_bootmem_huge_page(struct hstate *h, int nid) { - struct huge_bootmem_page *m; + struct huge_bootmem_page *m = NULL; /* initialize for clang */ int nr_nodes, node; + if (nid >= nr_online_nodes) + return 0; + /* do node specific alloc */ + if (nid != NUMA_NO_NODE) { + m = memblock_virt_alloc_try_nid_raw(huge_page_size(h), huge_page_size(h), + 0, MEMBLOCK_ALLOC_ACCESSIBLE, nid); + if (!m) + return 0; + goto found; + } + /* allocate from next node when distributing huge pages */ for_each_node_mask_to_alloc(h, nr_nodes, node, &node_states[N_MEMORY]) { - void *addr; - - addr = memblock_virt_alloc_try_nid_raw( + m = memblock_virt_alloc_try_nid_raw( huge_page_size(h), huge_page_size(h), 0, BOOTMEM_ALLOC_ACCESSIBLE, node); - if (addr) { - /* - * Use the beginning of the huge page to store the - * huge_bootmem_page struct (until gather_bootmem - * puts them into the mem_map). - */ - m = addr; - goto found; - } + /* + * Use the beginning of the huge page to store the + * huge_bootmem_page struct (until gather_bootmem + * puts them into the mem_map). + */ + if (!m) + return 0; + goto found; } - return 0; found: - BUG_ON(!IS_ALIGNED(virt_to_phys(m), huge_page_size(h))); /* Put them into a private list first because mem_map is not up yet */ INIT_LIST_HEAD(&m->list); list_add(&m->list, &huge_boot_pages); @@ -2310,12 +2317,55 @@ static void __init gather_bootmem_prealloc(void) cond_resched(); } } +static void __init hugetlb_hstate_alloc_pages_onenode(struct hstate *h, int nid) +{ + unsigned long i; + char buf[32]; + + for (i = 0; i < h->max_huge_pages_node[nid]; ++i) { + if (hstate_is_gigantic(h)) { + if (!alloc_bootmem_huge_page(h, nid)) + break; + } else { + struct page *page; + gfp_t gfp_mask = htlb_alloc_mask(h) | __GFP_THISNODE; + + page = alloc_fresh_huge_page(h, gfp_mask, nid, + &node_states[N_MEMORY], NULL); + if (!page) + break; + put_page(page); /* free it into the hugepage allocator */ + } + cond_resched(); + } + if (i == h->max_huge_pages_node[nid]) + return; + + string_get_size(huge_page_size(h), 1, STRING_UNITS_2, buf, 32); + pr_warn("HugeTLB: allocating %u of page size %s failed node%d. Only allocated %lu hugepages.\n", + h->max_huge_pages_node[nid], buf, nid, i); + h->max_huge_pages -= (h->max_huge_pages_node[nid] - i); + h->max_huge_pages_node[nid] = i; +} static void __init hugetlb_hstate_alloc_pages(struct hstate *h) { unsigned long i; nodemask_t *node_alloc_noretry; + bool node_specific_alloc = false; + + /* do node specific alloc */ + for (i = 0; i < nr_online_nodes; i++) { + if (h->max_huge_pages_node[i] > 0) { + hugetlb_hstate_alloc_pages_onenode(h, i); + node_specific_alloc = true; + } + } + + if (node_specific_alloc) + return; + /* below will do all node balanced alloc */ if (!hstate_is_gigantic(h)) { /* * Bit mask controlling how hard we retry per-node allocations. @@ -2336,7 +2386,7 @@ static void __init hugetlb_hstate_alloc_pages(struct hstate *h) for (i = 0; i < h->max_huge_pages; ++i) { if (hstate_is_gigantic(h)) { - if (!alloc_bootmem_huge_page(h)) + if (!alloc_bootmem_huge_page(h, NUMA_NO_NODE)) break; } else if (!alloc_pool_huge_page(h, &node_states[N_MEMORY], @@ -2991,8 +3041,13 @@ static int __init hugetlb_init(void) } default_hstate_idx = hstate_index(size_to_hstate(default_hstate_size)); if (default_hstate_max_huge_pages) { - if (!default_hstate.max_huge_pages) + if (!default_hstate.max_huge_pages) { default_hstate.max_huge_pages = default_hstate_max_huge_pages; + + for (i = 0; i < nr_online_nodes; i++) + default_hstate.max_huge_pages_node[i] = + default_hugepages_in_node[i]; + } } hugetlb_init_hstates(); @@ -3052,10 +3107,19 @@ void __init hugetlb_add_hstate(unsigned int order) parsed_hstate = h; } +bool __init __weak hugetlb_node_alloc_supported(void) +{ + return true; +} + static int __init hugetlb_nrpages_setup(char *s) { unsigned long *mhp; static unsigned long *last_mhp; + int node = NUMA_NO_NODE; + int count; + unsigned long tmp; + char *p = s; if (!parsed_valid_hugepagesz) { pr_warn("hugepages = %s preceded by " @@ -3077,8 +3141,40 @@ static int __init hugetlb_nrpages_setup(char *s) return 1; } - if (sscanf(s, "%lu", mhp) <= 0) - *mhp = 0; + while (*p) { + count = 0; + if (sscanf(p, "%lu%n", &tmp, &count) != 1) + goto invalid; + /* Parameter is node format */ + if (p[count] == ':') { + if (!hugetlb_node_alloc_supported()) { + pr_warn("HugeTLB: architecture can't support node specific alloc, ignoring!\n"); + return 0; + } + node = tmp; + p += count + 1; + if (node < 0 || node >= nr_online_nodes) + goto invalid; + /* Parse hugepages */ + if (sscanf(p, "%lu%n", &tmp, &count) != 1) + goto invalid; + if (!hugetlb_max_hstate) + default_hugepages_in_node[node] = tmp; + else + parsed_hstate->max_huge_pages_node[node] = tmp; + *mhp += tmp; + /* Go to parse next node*/ + if (p[count] == ',') + p += count + 1; + else + break; + } else { + if (p != s) + goto invalid; + *mhp = tmp; + break; + } + } /* * Global state is always initialized later in hugetlb_init. @@ -3091,6 +3187,10 @@ static int __init hugetlb_nrpages_setup(char *s) last_mhp = mhp; return 1; + +invalid: + pr_warn("HugeTLB: Invalid hugepages parameter %s\n", p); + return 0; } __setup("hugepages=", hugetlb_nrpages_setup); -- 2.25.1

1 1

回复:答复: openEuler kernel技术分享第十七期 & 双周例会
by Zhengyuan Liu 17 Jan '22

17 Jan '22

你好 rdma这个议题什么气候开始呢 ---------- 该邮件从移动设备发送 --------------原始邮件-------------- 发件人："tangjiayuan "<tangjiayuan(a)huawei.com>; 发送时间：2022年1月17日(星期一) 下午3:10 收件人："kernel(a)openeuler.org" <kernel(a)openeuler.org>;"kernel-discuss(a)openeuler.org" <kernel-discuss(a)openeuler.org>; 抄送："xie xiuqi "<xiexiuqi(a)huawei.com>;"chengjian (D) "<cj.chengjian(a)huawei.com>;"qiulaibin "<qiulaibin(a)huawei.com>; 主题：答复: openEuler kernel技术分享第十七期 & 双周例会 ----------------------------------- Kernel SIG增加一个议题：希望在内核态支持RDMA通信 -----邮件原件----- 发件人: openEuler conference [mailto:public@openeuler.org] 发送时间: 2021年12月27日 10:20 收件人: kernel(a)openeuler.org; tc(a)openeuler.org; dev(a)openeuler.org; kernel-discuss(a)openeuler.org 主题: openEuler kernel技术分享第十七期 & 双周例会您好！ Kernel SIG 邀请您参加 2021-12-31 14:00 召开的ZOOM会议(自动录制) 会议主题：openEuler kernel技术分享第十七期 & 双周例会会议内容： 14:10-15:30 openEuler kernel 技术分享第17期 - cgroup介绍会议链接：https://us06web.zoom.us/j/83118407147?pwd=elVzMVhGc2YzaDQ1TGorN2tPa1NhZz09 温馨提醒：建议接入会议后修改参会人的姓名，也可以使用您在gitee.com的ID 更多资讯尽在：https://openeuler.org/zh/ Hello! openEuler Kernel SIG invites you to attend the ZOOM conference(auto recording) will be held at 2021-12-31 14:00, The subject of the conference is openEuler kernel技术分享第十七期 & 双周例会, Summary: 14:10-15:30 openEuler kernel 技术分享第17期 - cgroup介绍 You can join the meeting at https://us06web.zoom.us/j/83118407147?pwd=elVzMVhGc2YzaDQ1TGorN2tPa1NhZz09. Note: You are advised to change the participant name after joining the conference or use your ID at gitee.com. More information: https://openeuler.org/en/ _______________________________________________ Kernel-discuss mailing list -- kernel-discuss(a)openeuler.org To unsubscribe send an email to kernel-discuss-leave(a)openeuler.org _______________________________________________ Kernel mailing list -- kernel(a)openeuler.org To unsubscribe send an email to kernel-leave(a)openeuler.org

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[PATCH openEuler-1.0-LTS 1/2] share pool: use rwsem to protect sp group exit
by Yang Yingliang 17 Jan '22

17 Jan '22

From: Guo Mengqi <guomengqi3(a)huawei.com> ascend inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4ODMN CVE: NA ------------------------------------------------- Fix following situation: when the last process in a group exits, and a second process tries to add to this group. The second process may get a invalid spg. However the group's use_count is increased by 1, which caused the first process failed to free the group when it exits. And then second process called sp_group_drop --> free_sp_group and cause a double request of rwsem. Signed-off-by: Guo Mengqi <guomengqi3(a)huawei.com> Reviewed-by: Weilong Chen <chenweilong(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- mm/share_pool.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/mm/share_pool.c b/mm/share_pool.c index 428742f5d4044..c79ea4bb06026 100644 --- a/mm/share_pool.c +++ b/mm/share_pool.c @@ -711,20 +711,25 @@ static void free_new_spg_id(bool new, int spg_id) free_sp_group_id(spg_id); } -static void free_sp_group(struct sp_group *spg) +static void free_sp_group_locked(struct sp_group *spg) { fput(spg->file); fput(spg->file_hugetlb); free_spg_stat(spg->id); - down_write(&sp_group_sem); idr_remove(&sp_group_idr, spg->id); - up_write(&sp_group_sem); free_sp_group_id((unsigned int)spg->id); kfree(spg); system_group_count--; WARN(system_group_count < 0, "unexpected group count\n"); } +static void free_sp_group(struct sp_group *spg) +{ + down_write(&sp_group_sem); + free_sp_group_locked(spg); + up_write(&sp_group_sem); +} + static void sp_group_drop(struct sp_group *spg) { if (atomic_dec_and_test(&spg->use_count)) @@ -4460,14 +4465,15 @@ void sp_group_post_exit(struct mm_struct *mm) sp_proc_stat_drop(stat); } - /* lockless traverse */ + down_write(&sp_group_sem); list_for_each_entry_safe(spg_node, tmp, &master->node_list, group_node) { spg = spg_node->spg; /* match with refcount inc in sp_group_add_task */ - sp_group_drop(spg); + if (atomic_dec_and_test(&spg->use_count)) + free_sp_group_locked(spg); kfree(spg_node); } - + up_write(&sp_group_sem); kfree(master); } -- 2.25.1

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[PATCH openEuler-1.0-LTS 1/9] Revert "svm: Add svm_set_user_mpam_en to enable/disable mpam for smmu"
by Yang Yingliang 17 Jan '22

17 Jan '22

From: Xingang Wang <wangxingang5(a)huawei.com> ascend inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I49RB2 CVE: NA ------------------------------------------------- This reverts commit c50ad40d63ef0cc9e0b158354af08f1f98419273. The commit "svm: Add svm_set_user_mpam_en to enable/disable mpam for smmu" add and export interface in svm module, this makes the mpam depend on the svm module, just revert this to avoid coupling. Signed-off-by: Xingang Wang <wangxingang5(a)huawei.com> Reviewed-by: Weilong Chen <chenweilong(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- drivers/char/svm.c | 64 ------------------------------------- include/linux/ascend_smmu.h | 3 -- 2 files changed, 67 deletions(-) diff --git a/drivers/char/svm.c b/drivers/char/svm.c index c877c75fdcd5f..000b9ad01c350 100644 --- a/drivers/char/svm.c +++ b/drivers/char/svm.c @@ -135,14 +135,11 @@ struct meminfo { struct svm_mpam { #define SVM_GET_DEV_MPAM (1 << 0) #define SVM_SET_DEV_MPAM (1 << 1) -#define SVM_GET_USER_MPAM_EN (1 << 2) -#define SVM_SET_USER_MPAM_EN (1 << 3) int flags; int pasid; int partid; int pmg; int s1mpam; - int user_mpam_en; }; struct phymeminfo { @@ -1505,14 +1502,6 @@ static int svm_get_core_mpam(struct device *dev, void *data) } } - if (mpam->flags & SVM_GET_USER_MPAM_EN) { - err = arm_smmu_get_dev_user_mpam_en(dev, &mpam->user_mpam_en); - if (err) { - dev_err(dev, "set user_mpam_en failed, %d\n", err); - return err; - } - } - return err; } @@ -1554,14 +1543,6 @@ static int svm_set_core_mpam(struct device *dev, void *data) } } - if (mpam->flags & SVM_SET_USER_MPAM_EN) { - err = arm_smmu_set_dev_user_mpam_en(dev, mpam->user_mpam_en); - if (err) { - dev_err(dev, "set user_mpam_en failed, %d\n", err); - return err; - } - } - return 0; } @@ -1655,51 +1636,6 @@ int svm_get_mpam(int pasid, int *partid, int *pmg, int *s1mpam) } EXPORT_SYMBOL_GPL(svm_get_mpam); -/** - * svm_set_user_mpam_en() - set user_mpam_en - * @user_mpam_en: 0 for smmu mpam, 1 for user mpam - */ -int svm_set_user_mpam_en(int user_mpam_en) -{ - int err; - struct svm_mpam mpam, old_mpam; - - old_mpam.flags = SVM_GET_USER_MPAM_EN; - err = __svm_get_mpam(&old_mpam); - - mpam.flags = SVM_SET_USER_MPAM_EN, - mpam.user_mpam_en = user_mpam_en, - err = __svm_set_mpam(&mpam); - if (err) - goto rollback; - - return 0; - -rollback: - __svm_set_mpam(&mpam); - return err; -} -EXPORT_SYMBOL_GPL(svm_set_user_mpam_en); - -/** - * svm_set_user_mpam_en() - set user_mpam_en - * @user_mpam_en: pointer to user_mpam_en - */ -int svm_get_user_mpam_en(int *user_mpam_en) -{ - int err; - struct svm_mpam mpam; - - mpam.flags = SVM_GET_USER_MPAM_EN; - err = __svm_get_mpam(&mpam); - if (err) - return err; - - *user_mpam_en = mpam.user_mpam_en; - return 0; -} -EXPORT_SYMBOL_GPL(svm_get_user_mpam_en); - static int svm_set_rc(unsigned long __user *arg) { unsigned long addr, size, rc; diff --git a/include/linux/ascend_smmu.h b/include/linux/ascend_smmu.h index 32241a02a8a89..e570acfc8f6ac 100644 --- a/include/linux/ascend_smmu.h +++ b/include/linux/ascend_smmu.h @@ -15,7 +15,4 @@ extern int arm_smmu_get_dev_user_mpam_en(struct device *dev, int *user_mpam_en); extern int svm_get_mpam(int pasid, int *partid, int *pmg, int *s1mpam); extern int svm_set_mpam(int pasid, int partid, int pmg, int s1mpam); -extern int svm_set_user_mpam_en(int user_mpam_en); -extern int svm_get_user_mpam_en(int *user_mpam_en); - #endif /* __LINUX_ASCEND_SMMU_H */ -- 2.25.1

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[PATCH openEuler-1.0-LTS 1/3] Revert "svm: Add svm_set_user_mpam_en to enable/disable mpam for smmu"
by Yang Yingliang 17 Jan '22

17 Jan '22

From: Xingang Wang <wangxingang5(a)huawei.com> ascend inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I49RB2 CVE: NA ------------------------------------------------- This reverts commit c50ad40d63ef0cc9e0b158354af08f1f98419273. The commit "svm: Add svm_set_user_mpam_en to enable/disable mpam for smmu" add and export interface in svm module, this makes the mpam depend on the svm module, just revert this to avoid coupling. Signed-off-by: Xingang Wang <wangxingang5(a)huawei.com> Reviewed-by: Weilong Chen <chenweilong(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- drivers/char/svm.c | 64 ------------------------------------- include/linux/ascend_smmu.h | 3 -- 2 files changed, 67 deletions(-) diff --git a/drivers/char/svm.c b/drivers/char/svm.c index c877c75fdcd5f..000b9ad01c350 100644 --- a/drivers/char/svm.c +++ b/drivers/char/svm.c @@ -135,14 +135,11 @@ struct meminfo { struct svm_mpam { #define SVM_GET_DEV_MPAM (1 << 0) #define SVM_SET_DEV_MPAM (1 << 1) -#define SVM_GET_USER_MPAM_EN (1 << 2) -#define SVM_SET_USER_MPAM_EN (1 << 3) int flags; int pasid; int partid; int pmg; int s1mpam; - int user_mpam_en; }; struct phymeminfo { @@ -1505,14 +1502,6 @@ static int svm_get_core_mpam(struct device *dev, void *data) } } - if (mpam->flags & SVM_GET_USER_MPAM_EN) { - err = arm_smmu_get_dev_user_mpam_en(dev, &mpam->user_mpam_en); - if (err) { - dev_err(dev, "set user_mpam_en failed, %d\n", err); - return err; - } - } - return err; } @@ -1554,14 +1543,6 @@ static int svm_set_core_mpam(struct device *dev, void *data) } } - if (mpam->flags & SVM_SET_USER_MPAM_EN) { - err = arm_smmu_set_dev_user_mpam_en(dev, mpam->user_mpam_en); - if (err) { - dev_err(dev, "set user_mpam_en failed, %d\n", err); - return err; - } - } - return 0; } @@ -1655,51 +1636,6 @@ int svm_get_mpam(int pasid, int *partid, int *pmg, int *s1mpam) } EXPORT_SYMBOL_GPL(svm_get_mpam); -/** - * svm_set_user_mpam_en() - set user_mpam_en - * @user_mpam_en: 0 for smmu mpam, 1 for user mpam - */ -int svm_set_user_mpam_en(int user_mpam_en) -{ - int err; - struct svm_mpam mpam, old_mpam; - - old_mpam.flags = SVM_GET_USER_MPAM_EN; - err = __svm_get_mpam(&old_mpam); - - mpam.flags = SVM_SET_USER_MPAM_EN, - mpam.user_mpam_en = user_mpam_en, - err = __svm_set_mpam(&mpam); - if (err) - goto rollback; - - return 0; - -rollback: - __svm_set_mpam(&mpam); - return err; -} -EXPORT_SYMBOL_GPL(svm_set_user_mpam_en); - -/** - * svm_set_user_mpam_en() - set user_mpam_en - * @user_mpam_en: pointer to user_mpam_en - */ -int svm_get_user_mpam_en(int *user_mpam_en) -{ - int err; - struct svm_mpam mpam; - - mpam.flags = SVM_GET_USER_MPAM_EN; - err = __svm_get_mpam(&mpam); - if (err) - return err; - - *user_mpam_en = mpam.user_mpam_en; - return 0; -} -EXPORT_SYMBOL_GPL(svm_get_user_mpam_en); - static int svm_set_rc(unsigned long __user *arg) { unsigned long addr, size, rc; diff --git a/include/linux/ascend_smmu.h b/include/linux/ascend_smmu.h index 32241a02a8a89..e570acfc8f6ac 100644 --- a/include/linux/ascend_smmu.h +++ b/include/linux/ascend_smmu.h @@ -15,7 +15,4 @@ extern int arm_smmu_get_dev_user_mpam_en(struct device *dev, int *user_mpam_en); extern int svm_get_mpam(int pasid, int *partid, int *pmg, int *s1mpam); extern int svm_set_mpam(int pasid, int partid, int pmg, int s1mpam); -extern int svm_set_user_mpam_en(int user_mpam_en); -extern int svm_get_user_mpam_en(int *user_mpam_en); - #endif /* __LINUX_ASCEND_SMMU_H */ -- 2.25.1

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[PATCH openEuler-1.0-LTS 1/7] cgroup: Use open-time credentials for process migraton perm checks
by Yang Yingliang 17 Jan '22

17 Jan '22

From: Tejun Heo <tj(a)kernel.org> mainline inclusion from mainline-v5.16-9 commit 1756d7994ad85c2479af6ae5a9750b92324685af category: bugfix bugzilla: NA CVE: CVE-2021-4197 --------------------------------------------------- cgroup process migration permission checks are performed at write time as whether a given operation is allowed or not is dependent on the content of the write - the PID. This currently uses current's credentials which is a potential security weakness as it may allow scenarios where a less privileged process tricks a more privileged one into writing into a fd that it created. This patch makes both cgroup2 and cgroup1 process migration interfaces to use the credentials saved at the time of open (file->f_cred) instead of current's. Reported-by: "Eric W. Biederman" <ebiederm(a)xmission.com> Suggested-by: Linus Torvalds <torvalds(a)linuxfoundation.org> Fixes: 187fe84067bd ("cgroup: require write perm on common ancestor when moving processes on the default hierarchy") Reviewed-by: Michal Koutný <mkoutny(a)suse.com> Signed-off-by: Tejun Heo <tj(a)kernel.org> Conflicts: kernel/cgroup/cgroup.c Signed-off-by: Lu Jialin <lujialin4(a)huawei.com> Reviewed-by: Xiu Jianfeng <xiujianfeng(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- kernel/cgroup/cgroup-v1.c | 7 ++++--- kernel/cgroup/cgroup.c | 19 ++++++++++++++++++- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c index 055063c9c2a38..7a3ea4d6b54cf 100644 --- a/kernel/cgroup/cgroup-v1.c +++ b/kernel/cgroup/cgroup-v1.c @@ -535,10 +535,11 @@ static ssize_t __cgroup1_procs_write(struct kernfs_open_file *of, goto out_unlock; /* - * Even if we're attaching all tasks in the thread group, we only - * need to check permissions on one of them. + * Even if we're attaching all tasks in the thread group, we only need + * to check permissions on one of them. Check permissions using the + * credentials from file open to protect against inherited fd attacks. */ - cred = current_cred(); + cred = of->file->f_cred; tcred = get_task_cred(task); if (!uid_eq(cred->euid, GLOBAL_ROOT_UID) && !uid_eq(cred->euid, tcred->uid) && diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 6f4dcdd6f77b2..49e8bf7ee9c73 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -4490,6 +4490,7 @@ static ssize_t cgroup_procs_write(struct kernfs_open_file *of, { struct cgroup *src_cgrp, *dst_cgrp; struct task_struct *task; + const struct cred *saved_cred; ssize_t ret; dst_cgrp = cgroup_kn_lock_live(of->kn, false); @@ -4506,8 +4507,16 @@ static ssize_t cgroup_procs_write(struct kernfs_open_file *of, src_cgrp = task_cgroup_from_root(task, &cgrp_dfl_root); spin_unlock_irq(&css_set_lock); + /* + * Process and thread migrations follow same delegation rule. Check + * permissions using the credentials from file open to protect against + * inherited fd attacks. + */ + + saved_cred = override_creds(of->file->f_cred); ret = cgroup_procs_write_permission(src_cgrp, dst_cgrp, of->file->f_path.dentry->d_sb); + revert_creds(saved_cred); if (ret) goto out_finish; @@ -4531,6 +4540,7 @@ static ssize_t cgroup_threads_write(struct kernfs_open_file *of, { struct cgroup *src_cgrp, *dst_cgrp; struct task_struct *task; + const struct cred *saved_cred; ssize_t ret; buf = strstrip(buf); @@ -4549,9 +4559,16 @@ static ssize_t cgroup_threads_write(struct kernfs_open_file *of, src_cgrp = task_cgroup_from_root(task, &cgrp_dfl_root); spin_unlock_irq(&css_set_lock); - /* thread migrations follow the cgroup.procs delegation rule */ + /* + * Process and thread migrations follow same delegation rule. Check + * permissions using the credentials from file open to protect against + * inherited fd attacks. + */ + + saved_cred = override_creds(of->file->f_cred); ret = cgroup_procs_write_permission(src_cgrp, dst_cgrp, of->file->f_path.dentry->d_sb); + revert_creds(saved_cred); if (ret) goto out_finish; -- 2.25.1

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